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OpenXG
OpenXG-RAN
Commits
f265729e
Commit
f265729e
authored
Feb 13, 2025
by
francescomani
Browse files
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Plain Diff
functions for 7-3-1-1-2 tables
parent
9aafec3e
Changes
4
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Showing
4 changed files
with
122 additions
and
62 deletions
+122
-62
openair2/LAYER2/NR_MAC_UE/mac_extern.h
openair2/LAYER2/NR_MAC_UE/mac_extern.h
+0
-12
openair2/LAYER2/NR_MAC_UE/mac_proto.h
openair2/LAYER2/NR_MAC_UE/mac_proto.h
+12
-1
openair2/LAYER2/NR_MAC_UE/mac_vars.c
openair2/LAYER2/NR_MAC_UE/mac_vars.c
+72
-0
openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c
openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c
+38
-49
No files found.
openair2/LAYER2/NR_MAC_UE/mac_extern.h
View file @
f265729e
...
@@ -32,17 +32,5 @@
...
@@ -32,17 +32,5 @@
#include "mac_defs.h"
#include "mac_defs.h"
extern
const
uint8_t
table_7_3_1_1_2_12
[
14
][
3
];
extern
const
uint8_t
table_7_3_1_1_2_13
[
10
][
4
];
extern
const
uint8_t
table_7_3_1_1_2_14
[
3
][
5
];
extern
const
uint8_t
table_7_3_1_1_2_15
[
4
][
6
];
extern
const
uint8_t
table_7_3_1_1_2_16
[
12
][
2
];
extern
const
uint8_t
table_7_3_1_1_2_17
[
7
][
3
];
extern
const
uint8_t
table_7_3_1_1_2_18
[
3
][
4
];
extern
const
uint8_t
table_7_3_1_1_2_19
[
2
][
5
];
extern
const
uint8_t
table_7_3_1_1_2_20
[
28
][
3
];
extern
const
uint8_t
table_7_3_1_1_2_21
[
19
][
4
];
extern
const
uint8_t
table_7_3_1_1_2_22
[
6
][
5
];
extern
const
uint8_t
table_7_3_1_1_2_23
[
5
][
6
];
openair2/LAYER2/NR_MAC_UE/mac_proto.h
View file @
f265729e
...
@@ -268,9 +268,20 @@ float nr_get_Pcmax(int p_Max,
...
@@ -268,9 +268,20 @@ float nr_get_Pcmax(int p_Max,
float
nr_get_Pcmin
(
int
bandwidth_index
);
float
nr_get_Pcmin
(
int
bandwidth_index
);
void
set_antenna_port_parameters
(
fapi_nr_dl_config_dlsch_pdu_rel15_t
*
dlsch_pdu
,
int
n_cw
,
long
*
max_length
,
long
*
dmrs
,
int
ant
);
void
set_antenna_port_parameters
(
fapi_nr_dl_config_dlsch_pdu_rel15_t
*
dlsch_pdu
,
int
n_cw
,
long
*
max_length
,
long
*
dmrs
,
int
ant
);
int
get_sum_delta_pucch
(
NR_UE_MAC_INST_t
*
mac
,
int
slot
,
frame_t
frame
);
int
get_sum_delta_pucch
(
NR_UE_MAC_INST_t
*
mac
,
int
slot
,
frame_t
frame
);
uint8_t
get_table_7_3_1_1_2_12_value
(
int
ap
,
int
idx
);
uint8_t
get_table_7_3_1_1_2_13_value
(
int
ap
,
int
idx
);
uint8_t
get_table_7_3_1_1_2_14_value
(
int
ap
,
int
idx
);
uint8_t
get_table_7_3_1_1_2_15_value
(
int
ap
,
int
idx
);
uint8_t
get_table_7_3_1_1_2_16_value
(
int
ap
,
int
idx
);
uint8_t
get_table_7_3_1_1_2_17_value
(
int
ap
,
int
idx
);
uint8_t
get_table_7_3_1_1_2_18_value
(
int
ap
,
int
idx
);
uint8_t
get_table_7_3_1_1_2_19_value
(
int
ap
,
int
idx
);
uint8_t
get_table_7_3_1_1_2_20_value
(
int
ap
,
int
idx
);
uint8_t
get_table_7_3_1_1_2_21_value
(
int
ap
,
int
idx
);
uint8_t
get_table_7_3_1_1_2_22_value
(
int
ap
,
int
idx
);
uint8_t
get_table_7_3_1_1_2_23_value
(
int
ap
,
int
idx
);
/* Random Access */
/* Random Access */
/* \brief This function schedules the PRACH according to prach_ConfigurationIndex and TS 38.211 tables 6.3.3.2.x
/* \brief This function schedules the PRACH according to prach_ConfigurationIndex and TS 38.211 tables 6.3.3.2.x
and fills the PRACH PDU per each FD occasion.
and fills the PRACH PDU per each FD occasion.
@param mac pointer to MAC instance
@param mac pointer to MAC instance
...
...
openair2/LAYER2/NR_MAC_UE/mac_vars.c
View file @
f265729e
...
@@ -122,6 +122,12 @@ const uint8_t table_7_3_1_1_2_12[14][3] = {
...
@@ -122,6 +122,12 @@ const uint8_t table_7_3_1_1_2_12[14][3] = {
{
2
,
7
,
2
}
{
2
,
7
,
2
}
};
};
uint8_t
get_table_7_3_1_1_2_12_value
(
int
ap
,
int
idx
)
{
AssertFatal
(
ap
<
14
&&
idx
<
3
,
"Invalid inputs for table_7_3_1_1_2_12
\n
"
);
return
table_7_3_1_1_2_12
[
ap
][
idx
];
}
const
uint8_t
table_7_3_1_1_2_13
[
10
][
4
]
=
{
const
uint8_t
table_7_3_1_1_2_13
[
10
][
4
]
=
{
{
1
,
0
,
1
,
1
},
{
1
,
0
,
1
,
1
},
{
2
,
0
,
1
,
1
},
{
2
,
0
,
1
,
1
},
...
@@ -135,12 +141,24 @@ const uint8_t table_7_3_1_1_2_13[10][4] = {
...
@@ -135,12 +141,24 @@ const uint8_t table_7_3_1_1_2_13[10][4] = {
{
2
,
2
,
6
,
2
}
{
2
,
2
,
6
,
2
}
};
};
uint8_t
get_table_7_3_1_1_2_13_value
(
int
ap
,
int
idx
)
{
AssertFatal
(
ap
<
10
&&
idx
<
4
,
"Invalid inputs for table_7_3_1_1_2_13
\n
"
);
return
table_7_3_1_1_2_13
[
ap
][
idx
];
}
const
uint8_t
table_7_3_1_1_2_14
[
3
][
5
]
=
{
const
uint8_t
table_7_3_1_1_2_14
[
3
][
5
]
=
{
{
2
,
0
,
1
,
2
,
1
},
{
2
,
0
,
1
,
2
,
1
},
{
2
,
0
,
1
,
4
,
2
},
{
2
,
0
,
1
,
4
,
2
},
{
2
,
2
,
3
,
6
,
2
}
{
2
,
2
,
3
,
6
,
2
}
};
};
uint8_t
get_table_7_3_1_1_2_14_value
(
int
ap
,
int
idx
)
{
AssertFatal
(
ap
<
3
&&
idx
<
5
,
"Invalid inputs for table_7_3_1_1_2_14
\n
"
);
return
table_7_3_1_1_2_14
[
ap
][
idx
];
}
const
uint8_t
table_7_3_1_1_2_15
[
4
][
6
]
=
{
const
uint8_t
table_7_3_1_1_2_15
[
4
][
6
]
=
{
{
2
,
0
,
1
,
2
,
3
,
1
},
{
2
,
0
,
1
,
2
,
3
,
1
},
{
2
,
0
,
1
,
4
,
5
,
2
},
{
2
,
0
,
1
,
4
,
5
,
2
},
...
@@ -148,6 +166,12 @@ const uint8_t table_7_3_1_1_2_15[4][6] = {
...
@@ -148,6 +166,12 @@ const uint8_t table_7_3_1_1_2_15[4][6] = {
{
2
,
0
,
2
,
4
,
6
,
2
}
{
2
,
0
,
2
,
4
,
6
,
2
}
};
};
uint8_t
get_table_7_3_1_1_2_15_value
(
int
ap
,
int
idx
)
{
AssertFatal
(
ap
<
4
&&
idx
<
6
,
"Invalid inputs for table_7_3_1_1_2_15
\n
"
);
return
table_7_3_1_1_2_15
[
ap
][
idx
];
}
const
uint8_t
table_7_3_1_1_2_16
[
12
][
2
]
=
{
const
uint8_t
table_7_3_1_1_2_16
[
12
][
2
]
=
{
{
1
,
0
},
{
1
,
0
},
{
1
,
1
},
{
1
,
1
},
...
@@ -163,6 +187,12 @@ const uint8_t table_7_3_1_1_2_16[12][2] = {
...
@@ -163,6 +187,12 @@ const uint8_t table_7_3_1_1_2_16[12][2] = {
{
3
,
5
}
{
3
,
5
}
};
};
uint8_t
get_table_7_3_1_1_2_16_value
(
int
ap
,
int
idx
)
{
AssertFatal
(
ap
<
12
&&
idx
<
2
,
"Invalid inputs for table_7_3_1_1_2_16
\n
"
);
return
table_7_3_1_1_2_16
[
ap
][
idx
];
}
const
uint8_t
table_7_3_1_1_2_17
[
7
][
3
]
=
{
const
uint8_t
table_7_3_1_1_2_17
[
7
][
3
]
=
{
{
1
,
0
,
1
},
{
1
,
0
,
1
},
{
2
,
0
,
1
},
{
2
,
0
,
1
},
...
@@ -173,17 +203,35 @@ const uint8_t table_7_3_1_1_2_17[7][3] = {
...
@@ -173,17 +203,35 @@ const uint8_t table_7_3_1_1_2_17[7][3] = {
{
2
,
0
,
2
}
{
2
,
0
,
2
}
};
};
uint8_t
get_table_7_3_1_1_2_17_value
(
int
ap
,
int
idx
)
{
AssertFatal
(
ap
<
7
&&
idx
<
3
,
"Invalid inputs for table_7_3_1_1_2_17
\n
"
);
return
table_7_3_1_1_2_17
[
ap
][
idx
];
}
const
uint8_t
table_7_3_1_1_2_18
[
3
][
4
]
=
{
const
uint8_t
table_7_3_1_1_2_18
[
3
][
4
]
=
{
{
2
,
0
,
1
,
2
},
{
2
,
0
,
1
,
2
},
{
3
,
0
,
1
,
2
},
{
3
,
0
,
1
,
2
},
{
3
,
3
,
4
,
5
}
{
3
,
3
,
4
,
5
}
};
};
uint8_t
get_table_7_3_1_1_2_18_value
(
int
ap
,
int
idx
)
{
AssertFatal
(
ap
<
3
&&
idx
<
4
,
"Invalid inputs for table_7_3_1_1_2_18
\n
"
);
return
table_7_3_1_1_2_18
[
ap
][
idx
];
}
const
uint8_t
table_7_3_1_1_2_19
[
2
][
5
]
=
{
const
uint8_t
table_7_3_1_1_2_19
[
2
][
5
]
=
{
{
2
,
0
,
1
,
2
,
3
},
{
2
,
0
,
1
,
2
,
3
},
{
3
,
0
,
1
,
2
,
3
}
{
3
,
0
,
1
,
2
,
3
}
};
};
uint8_t
get_table_7_3_1_1_2_19_value
(
int
ap
,
int
idx
)
{
AssertFatal
(
ap
<
2
&&
idx
<
5
,
"Invalid inputs for table_7_3_1_1_2_19
\n
"
);
return
table_7_3_1_1_2_19
[
ap
][
idx
];
}
const
uint8_t
table_7_3_1_1_2_20
[
28
][
3
]
=
{
const
uint8_t
table_7_3_1_1_2_20
[
28
][
3
]
=
{
{
1
,
0
,
1
},
{
1
,
0
,
1
},
{
1
,
1
,
1
},
{
1
,
1
,
1
},
...
@@ -215,6 +263,12 @@ const uint8_t table_7_3_1_1_2_20[28][3] = {
...
@@ -215,6 +263,12 @@ const uint8_t table_7_3_1_1_2_20[28][3] = {
{
1
,
7
,
2
}
{
1
,
7
,
2
}
};
};
uint8_t
get_table_7_3_1_1_2_20_value
(
int
ap
,
int
idx
)
{
AssertFatal
(
ap
<
28
&&
idx
<
3
,
"Invalid inputs for table_7_3_1_1_2_20
\n
"
);
return
table_7_3_1_1_2_20
[
ap
][
idx
];
}
const
uint8_t
table_7_3_1_1_2_21
[
19
][
4
]
=
{
const
uint8_t
table_7_3_1_1_2_21
[
19
][
4
]
=
{
{
1
,
0
,
1
,
1
},
{
1
,
0
,
1
,
1
},
{
2
,
0
,
1
,
1
},
{
2
,
0
,
1
,
1
},
...
@@ -237,6 +291,12 @@ const uint8_t table_7_3_1_1_2_21[19][4] = {
...
@@ -237,6 +291,12 @@ const uint8_t table_7_3_1_1_2_21[19][4] = {
{
2
,
8
,
9
,
2
}
{
2
,
8
,
9
,
2
}
};
};
uint8_t
get_table_7_3_1_1_2_21_value
(
int
ap
,
int
idx
)
{
AssertFatal
(
ap
<
19
&&
idx
<
4
,
"Invalid inputs for table_7_3_1_1_2_21
\n
"
);
return
table_7_3_1_1_2_21
[
ap
][
idx
];
}
const
uint8_t
table_7_3_1_1_2_22
[
6
][
5
]
=
{
const
uint8_t
table_7_3_1_1_2_22
[
6
][
5
]
=
{
{
2
,
0
,
1
,
2
,
1
},
{
2
,
0
,
1
,
2
,
1
},
{
3
,
0
,
1
,
2
,
1
},
{
3
,
0
,
1
,
2
,
1
},
...
@@ -246,6 +306,12 @@ const uint8_t table_7_3_1_1_2_22[6][5] = {
...
@@ -246,6 +306,12 @@ const uint8_t table_7_3_1_1_2_22[6][5] = {
{
3
,
4
,
5
,
10
,
2
}
{
3
,
4
,
5
,
10
,
2
}
};
};
uint8_t
get_table_7_3_1_1_2_22_value
(
int
ap
,
int
idx
)
{
AssertFatal
(
ap
<
6
&&
idx
<
5
,
"Invalid inputs for table_7_3_1_1_2_22
\n
"
);
return
table_7_3_1_1_2_22
[
ap
][
idx
];
}
const
uint8_t
table_7_3_1_1_2_23
[
5
][
6
]
=
{
const
uint8_t
table_7_3_1_1_2_23
[
5
][
6
]
=
{
{
2
,
0
,
1
,
2
,
3
,
1
},
{
2
,
0
,
1
,
2
,
3
,
1
},
{
3
,
0
,
1
,
2
,
3
,
1
},
{
3
,
0
,
1
,
2
,
3
,
1
},
...
@@ -254,6 +320,12 @@ const uint8_t table_7_3_1_1_2_23[5][6] = {
...
@@ -254,6 +320,12 @@ const uint8_t table_7_3_1_1_2_23[5][6] = {
{
3
,
4
,
5
,
10
,
11
,
2
}
{
3
,
4
,
5
,
10
,
11
,
2
}
};
};
uint8_t
get_table_7_3_1_1_2_23_value
(
int
ap
,
int
idx
)
{
AssertFatal
(
ap
<
5
&&
idx
<
6
,
"Invalid inputs for table_7_3_1_1_2_23
\n
"
);
return
table_7_3_1_1_2_23
[
ap
][
idx
];
}
const
uint8_t
table_7_3_2_3_3_1
[
12
][
5
]
=
{
const
uint8_t
table_7_3_2_3_3_1
[
12
][
5
]
=
{
{
1
,
1
,
0
,
0
,
0
},
{
1
,
1
,
0
,
0
,
0
},
{
1
,
0
,
1
,
0
,
0
},
{
1
,
0
,
1
,
0
,
0
},
...
...
openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c
View file @
f265729e
...
@@ -378,66 +378,59 @@ void ul_ports_config(NR_UE_MAC_INST_t *mac, int *n_front_load_symb, nfapi_nr_ue_
...
@@ -378,66 +378,59 @@ void ul_ports_config(NR_UE_MAC_INST_t *mac, int *n_front_load_symb, nfapi_nr_ue_
}
}
}
}
if
((
transformPrecoder
==
NR_PUSCH_Config__transformPrecoder_disabled
)
&&
(
dmrs_type
==
NULL
)
if
((
transformPrecoder
==
NR_PUSCH_Config__transformPrecoder_disabled
)
&&
(
dmrs_type
==
NULL
)
&&
(
max_length
!=
NULL
))
{
// tables 7.3.1.1.2-12/13/14/15
&&
(
max_length
!=
NULL
))
{
// tables 7.3.1.1.2-12/13/14/15
if
(
rank
==
1
){
if
(
rank
==
1
){
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
(
dci
->
antenna_ports
.
val
>
1
)
?
2
:
1
;
//TBC
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
(
dci
->
antenna_ports
.
val
>
1
)
?
2
:
1
;
//TBC
pusch_config_pdu
->
dmrs_ports
=
1
<<
((
dci
->
antenna_ports
.
val
>
1
)
?
(
dci
->
antenna_ports
.
val
>
5
?
(
dci
->
antenna_ports
.
val
-
6
)
:
(
dci
->
antenna_ports
.
val
-
2
))
:
dci
->
antenna_ports
.
val
);
pusch_config_pdu
->
dmrs_ports
=
1
<<
((
dci
->
antenna_ports
.
val
>
1
)
?
(
dci
->
antenna_ports
.
val
>
5
?
(
dci
->
antenna_ports
.
val
-
6
)
:
(
dci
->
antenna_ports
.
val
-
2
))
:
dci
->
antenna_ports
.
val
);
*
n_front_load_symb
=
(
dci
->
antenna_ports
.
val
>
6
)
?
2
:
1
;
*
n_front_load_symb
=
(
dci
->
antenna_ports
.
val
>
6
)
?
2
:
1
;
}
}
if
(
rank
==
2
){
if
(
rank
==
2
){
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
(
dci
->
antenna_ports
.
val
>
0
)
?
2
:
1
;
//TBC
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
(
dci
->
antenna_ports
.
val
>
0
)
?
2
:
1
;
//TBC
pusch_config_pdu
->
dmrs_ports
=
0
;
//FIXME
pusch_config_pdu
->
dmrs_ports
=
0
;
//FIXME
//pusch_config_pdu->dmrs_ports[0] =
table_7_3_1_1_2_13[dci->antenna_ports.val][1]
;
//pusch_config_pdu->dmrs_ports[0] =
get_table_7_3_1_1_2_13_value(dci->antenna_ports.val, 1)
;
//pusch_config_pdu->dmrs_ports[1] =
table_7_3_1_1_2_13[dci->antenna_ports.val][2]
;
//pusch_config_pdu->dmrs_ports[1] =
get_table_7_3_1_1_2_13_value(dci->antenna_ports.val, 2)
;
//n_front_load_symb = (dci->antenna_ports.val > 3)?2:1; // FIXME
//n_front_load_symb = (dci->antenna_ports.val > 3)?2:1; // FIXME
}
}
if
(
rank
==
3
){
if
(
rank
==
3
){
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
2
;
//TBC
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
2
;
//TBC
pusch_config_pdu
->
dmrs_ports
=
0
;
//FIXME
pusch_config_pdu
->
dmrs_ports
=
0
;
//FIXME
//pusch_config_pdu->dmrs_ports[0] =
table_7_3_1_1_2_14[dci->antenna_ports.val][1]
;
//pusch_config_pdu->dmrs_ports[0] =
get_table_7_3_1_1_2_14_value(dci->antenna_ports.val, 1)
;
//pusch_config_pdu->dmrs_ports[1] =
table_7_3_1_1_2_14[dci->antenna_ports.val][2]
;
//pusch_config_pdu->dmrs_ports[1] =
get_table_7_3_1_1_2_14_value(dci->antenna_ports.val, 2)
;
//pusch_config_pdu->dmrs_ports[2] =
table_7_3_1_1_2_14[dci->antenna_ports.val][3]
;
//pusch_config_pdu->dmrs_ports[2] =
get_table_7_3_1_1_2_14_value(dci->antenna_ports.val, 3)
;
//n_front_load_symb = (dci->antenna_ports.val > 1)?2:1; //FIXME
//n_front_load_symb = (dci->antenna_ports.val > 1)?2:1; //FIXME
}
}
if
(
rank
==
4
){
if
(
rank
==
4
){
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
2
;
//TBC
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
2
;
//TBC
pusch_config_pdu
->
dmrs_ports
=
0
;
//FIXME
pusch_config_pdu
->
dmrs_ports
=
0
;
//FIXME
//pusch_config_pdu->dmrs_ports[0] =
table_7_3_1_1_2_15[dci->antenna_ports.val][1]
;
//pusch_config_pdu->dmrs_ports[0] =
get_table_7_3_1_1_2_15_value(dci->antenna_ports.val, 1)
;
//pusch_config_pdu->dmrs_ports[1] =
table_7_3_1_1_2_15[dci->antenna_ports.val][2]
;
//pusch_config_pdu->dmrs_ports[1] =
get_table_7_3_1_1_2_15_value(dci->antenna_ports.val, 2)
;
//pusch_config_pdu->dmrs_ports[2] =
table_7_3_1_1_2_15[dci->antenna_ports.val][3]
;
//pusch_config_pdu->dmrs_ports[2] =
get_table_7_3_1_1_2_15_value(dci->antenna_ports.val, 3)
;
//pusch_config_pdu->dmrs_ports[3] =
table_7_3_1_1_2_15[dci->antenna_ports.val][4]
;
//pusch_config_pdu->dmrs_ports[3] =
get_table_7_3_1_1_2_15_value(dci->antenna_ports.val, 4)
;
//n_front_load_symb = (dci->antenna_ports.val > 1)?2:1; //FIXME
//n_front_load_symb = (dci->antenna_ports.val > 1)?2:1; //FIXME
}
}
}
}
if
((
transformPrecoder
==
NR_PUSCH_Config__transformPrecoder_disabled
)
if
((
transformPrecoder
==
NR_PUSCH_Config__transformPrecoder_disabled
)
&&
(
dmrs_type
!=
NULL
)
&&
(
dmrs_type
!=
NULL
)
&&
(
max_length
==
NULL
))
{
// tables 7.3.1.1.2-16/17/18/19
&&
(
max_length
==
NULL
))
{
// tables 7.3.1.1.2-16/17/18/19
if
(
rank
==
1
){
if
(
rank
==
1
){
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
(
dci
->
antenna_ports
.
val
>
1
)
?
((
dci
->
antenna_ports
.
val
>
5
)
?
3
:
2
)
:
1
;
//TBC
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
(
dci
->
antenna_ports
.
val
>
1
)
?
((
dci
->
antenna_ports
.
val
>
5
)
?
3
:
2
)
:
1
;
//TBC
pusch_config_pdu
->
dmrs_ports
=
(
dci
->
antenna_ports
.
val
>
1
)
?
(
dci
->
antenna_ports
.
val
>
5
?
(
dci
->
antenna_ports
.
val
-
6
)
:
(
dci
->
antenna_ports
.
val
-
2
))
:
dci
->
antenna_ports
.
val
;
//TBC
pusch_config_pdu
->
dmrs_ports
=
(
dci
->
antenna_ports
.
val
>
1
)
?
(
dci
->
antenna_ports
.
val
>
5
?
(
dci
->
antenna_ports
.
val
-
6
)
:
(
dci
->
antenna_ports
.
val
-
2
))
:
dci
->
antenna_ports
.
val
;
//TBC
}
}
if
(
rank
==
2
){
if
(
rank
==
2
){
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
(
dci
->
antenna_ports
.
val
>
0
)
?
((
dci
->
antenna_ports
.
val
>
2
)
?
3
:
2
)
:
1
;
//TBC
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
(
dci
->
antenna_ports
.
val
>
0
)
?
((
dci
->
antenna_ports
.
val
>
2
)
?
3
:
2
)
:
1
;
//TBC
pusch_config_pdu
->
dmrs_ports
=
0
;
//FIXME
pusch_config_pdu
->
dmrs_ports
=
0
;
//FIXME
//pusch_config_pdu->dmrs_ports[0] =
table_7_3_1_1_2_17[dci->antenna_ports.val][1]
;
//pusch_config_pdu->dmrs_ports[0] =
get_table_7_3_1_1_2_17_value(dci->antenna_ports.val, 1)
;
//pusch_config_pdu->dmrs_ports[1] =
table_7_3_1_1_2_17[dci->antenna_ports.val][2]
;
//pusch_config_pdu->dmrs_ports[1] =
get_table_7_3_1_1_2_18_value(dci->antenna_ports.val, 2)
;
}
}
if
(
rank
==
3
){
if
(
rank
==
3
){
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
(
dci
->
antenna_ports
.
val
>
0
)
?
3
:
2
;
//TBC
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
(
dci
->
antenna_ports
.
val
>
0
)
?
3
:
2
;
//TBC
pusch_config_pdu
->
dmrs_ports
=
0
;
//FIXME
pusch_config_pdu
->
dmrs_ports
=
0
;
//FIXME
//pusch_config_pdu->dmrs_ports[0] =
table_7_3_1_1_2_18[dci->antenna_ports.val][1]
;
//pusch_config_pdu->dmrs_ports[0] =
get_table_7_3_1_1_2_18_value(dci->antenna_ports.val, 1)
;
//pusch_config_pdu->dmrs_ports[1] =
table_7_3_1_1_2_18[dci->antenna_ports.val][2]
;
//pusch_config_pdu->dmrs_ports[1] =
get_table_7_3_1_1_2_18_value(dci->antenna_ports.val, 2)
;
//pusch_config_pdu->dmrs_ports[2] =
table_7_3_1_1_2_18[dci->antenna_ports.val][3]
;
//pusch_config_pdu->dmrs_ports[2] =
get_table_7_3_1_1_2_18_value(dci->antenna_ports.val, 3)
;
}
}
if
(
rank
==
4
){
if
(
rank
==
4
){
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
dci
->
antenna_ports
.
val
+
2
;
//TBC
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
dci
->
antenna_ports
.
val
+
2
;
//TBC
pusch_config_pdu
->
dmrs_ports
=
0
;
//FIXME
pusch_config_pdu
->
dmrs_ports
=
0
;
//FIXME
...
@@ -447,41 +440,37 @@ void ul_ports_config(NR_UE_MAC_INST_t *mac, int *n_front_load_symb, nfapi_nr_ue_
...
@@ -447,41 +440,37 @@ void ul_ports_config(NR_UE_MAC_INST_t *mac, int *n_front_load_symb, nfapi_nr_ue_
//pusch_config_pdu->dmrs_ports[3] = 3;
//pusch_config_pdu->dmrs_ports[3] = 3;
}
}
}
}
if
((
transformPrecoder
==
NR_PUSCH_Config__transformPrecoder_disabled
)
if
((
transformPrecoder
==
NR_PUSCH_Config__transformPrecoder_disabled
)
&&
(
dmrs_type
!=
NULL
)
&&
(
dmrs_type
!=
NULL
)
&&
(
max_length
!=
NULL
))
{
// tables 7.3.1.1.2-20/21/22/23
&&
(
max_length
!=
NULL
))
{
// tables 7.3.1.1.2-20/21/22/23
if
(
rank
==
1
){
if
(
rank
==
1
){
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
table_7_3_1_1_2_20
[
dci
->
antenna_ports
.
val
][
0
]
;
//TBC
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
get_table_7_3_1_1_2_20_value
(
dci
->
antenna_ports
.
val
,
0
)
;
//TBC
pusch_config_pdu
->
dmrs_ports
=
table_7_3_1_1_2_20
[
dci
->
antenna_ports
.
val
][
1
]
;
//TBC
pusch_config_pdu
->
dmrs_ports
=
get_table_7_3_1_1_2_20_value
(
dci
->
antenna_ports
.
val
,
1
)
;
//TBC
//n_front_load_symb =
table_7_3_1_1_2_20[dci->antenna_ports.val][2]
; //FIXME
//n_front_load_symb =
get_table_7_3_1_1_2_20_value(dci->antenna_ports.val, 2)
; //FIXME
}
}
if
(
rank
==
2
){
if
(
rank
==
2
){
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
table_7_3_1_1_2_21
[
dci
->
antenna_ports
.
val
][
0
]
;
//TBC
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
get_table_7_3_1_1_2_21_value
(
dci
->
antenna_ports
.
val
,
0
)
;
//TBC
pusch_config_pdu
->
dmrs_ports
=
0
;
//FIXME
pusch_config_pdu
->
dmrs_ports
=
0
;
//FIXME
//pusch_config_pdu->dmrs_ports[0] =
table_7_3_1_1_2_21[dci->antenna_ports.val][1]
;
//pusch_config_pdu->dmrs_ports[0] =
get_table_7_3_1_1_2_21_value(dci->antenna_ports.val, 1)
;
//pusch_config_pdu->dmrs_ports[1] =
table_7_3_1_1_2_21[dci->antenna_ports.val][2]
;
//pusch_config_pdu->dmrs_ports[1] =
get_table_7_3_1_1_2_21_value(dci->antenna_ports.val, 2)
;
//n_front_load_symb =
table_7_3_1_1_2_21[dci->antenna_ports.val][3]
; //FIXME
//n_front_load_symb =
get_table_7_3_1_1_2_21_value(dci->antenna_ports.val, 3)
; //FIXME
}
}
if
(
rank
==
3
){
if
(
rank
==
3
){
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
table_7_3_1_1_2_22
[
dci
->
antenna_ports
.
val
][
0
]
;
//TBC
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
get_table_7_3_1_1_2_22_value
(
dci
->
antenna_ports
.
val
,
0
)
;
//TBC
pusch_config_pdu
->
dmrs_ports
=
0
;
//FIXME
pusch_config_pdu
->
dmrs_ports
=
0
;
//FIXME
//pusch_config_pdu->dmrs_ports[0] =
table_7_3_1_1_2_22[dci->antenna_ports.val][1]
;
//pusch_config_pdu->dmrs_ports[0] =
get_table_7_3_1_1_2_22_value(dci->antenna_ports.val, 1)
;
//pusch_config_pdu->dmrs_ports[1] =
table_7_3_1_1_2_22[dci->antenna_ports.val][2]
;
//pusch_config_pdu->dmrs_ports[1] =
get_table_7_3_1_1_2_22_value(dci->antenna_ports.val, 2)
;
//pusch_config_pdu->dmrs_ports[2] =
table_7_3_1_1_2_22[dci->antenna_ports.val][3]
;
//pusch_config_pdu->dmrs_ports[2] =
get_table_7_3_1_1_2_22_value(dci->antenna_ports.val, 3)
;
//n_front_load_symb =
table_7_3_1_1_2_22[dci->antenna_ports.val][4]
; //FIXME
//n_front_load_symb =
get_table_7_3_1_1_2_22_value(dci->antenna_ports.val, 4)
; //FIXME
}
}
if
(
rank
==
4
){
if
(
rank
==
4
){
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
table_7_3_1_1_2_23
[
dci
->
antenna_ports
.
val
][
0
]
;
//TBC
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
=
get_table_7_3_1_1_2_23_value
(
dci
->
antenna_ports
.
val
,
0
)
;
//TBC
pusch_config_pdu
->
dmrs_ports
=
0
;
//FIXME
pusch_config_pdu
->
dmrs_ports
=
0
;
//FIXME
//pusch_config_pdu->dmrs_ports[0] =
table_7_3_1_1_2_23[dci->antenna_ports.val][1]
;
//pusch_config_pdu->dmrs_ports[0] =
get_table_7_3_1_1_2_23_value(dci->antenna_ports.val, 1)
;
//pusch_config_pdu->dmrs_ports[1] =
table_7_3_1_1_2_23[dci->antenna_ports.val][2]
;
//pusch_config_pdu->dmrs_ports[1] =
get_table_7_3_1_1_2_23_value(dci->antenna_ports.val, 2)
;
//pusch_config_pdu->dmrs_ports[2] =
table_7_3_1_1_2_23[dci->antenna_ports.val][3]
;
//pusch_config_pdu->dmrs_ports[2] =
get_table_7_3_1_1_2_23_value(dci->antenna_ports.val, 3)
;
//pusch_config_pdu->dmrs_ports[3] =
table_7_3_1_1_2_23[dci->antenna_ports.val][4]
;
//pusch_config_pdu->dmrs_ports[3] =
get_table_7_3_1_1_2_23_value(dci->antenna_ports.val, 4)
;
//n_front_load_symb =
table_7_3_1_1_2_23[dci->antenna_ports.val][5]
; //FIXME
//n_front_load_symb =
get_table_7_3_1_1_2_23_value(dci->antenna_ports.val, 5)
; //FIXME
}
}
}
}
LOG_D
(
NR_MAC
,
"num_dmrs_cdm_grps_no_data %d, dmrs_ports %d
\n
"
,
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
,
pusch_config_pdu
->
dmrs_ports
);
LOG_D
(
NR_MAC
,
"num_dmrs_cdm_grps_no_data %d, dmrs_ports %d
\n
"
,
pusch_config_pdu
->
num_dmrs_cdm_grps_no_data
,
pusch_config_pdu
->
dmrs_ports
);
...
...
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