Commit 0c6b5101 authored by Francesco Mani's avatar Francesco Mani

merge between FR2 and RRC branches

parent 18d717ea
develop 1 128-ues 256_QAM_demod LTE_TRX_on_single_port NCTU_OpinConnect_LDPC NR-PHY-MAC-IF-multi-UE NRUE_usedlschparallel NR_10MHz NR_CSI_reporting NR_DCI_01 NR_DLUL_PF NR_DLUL_PF_4UL NR_DLUL_PF_rebased NR_DL_MIMO NR_DL_sched_fixes NR_DL_scheduler NR_FAPI_beamindex_SSB_RO NR_FDD_FIX NR_FR2_RA NR_FR2_RRC_SSB NR_MAC_CE_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge NR_MAC_SSB_RO_GlobalEdge NR_MAC_SSB_RO_UE_IDCC NR_MAC_SSB_RO_merge NR_MAC_TCI_UCI_GlobalEdge NR_NGAP NR_PDCP_noS1 NR_PUCCH_MultiUE NR_RA_cleanup NR_RA_updates NR_RRCConfiguragion_FR2 NR_RRCConfiguration NR_RRCConfiguration_FR2 NR_RRCConfiguration_S1U NR_RRCConfiguration_merge_develop NR_RRCConfiguration_sync_source NR_RRCConfiguration_trx_thread NR_RRC_CP_bugfix NR_RRC_PDCP NR_RRC_PRACH_procedures NR_RRC_PRACH_procedures_todevelop NR_RRC_TA NR_RRC_X2AP_AMBR_Change_Global_edge NR_RRC_X2AP_RemoveHardcodings_GlobalEdge NR_RRC_config_simplified NR_RRC_harq NR_RRC_harq_b NR_RRC_harq_hacks NR_RRC_harq_newdcipdu NR_SA_F1AP_RFSIMULATOR NR_SA_F1AP_RFSIMULATOR2 NR_SA_F1AP_dev NR_SA_NGAP_RRC NR_SA_NGAP_RRC_wk42 NR_SA_itti_sim_wk48 NR_SA_itti_sim_wk48_hs NR_SA_itti_sim_wk48_hs1 NR_SCHED NR_SCHED_HARQ NR_SCHED_PDCCH_PUCCH_HARQ NR_SCHED_PDCCH_PUCCH_HARQ_rebased NR_SCHED_fixes NR_SRB_Config NR_TRX_on_single_port NR_TRX_on_single_port2 NR_UE_MAC_scheduler NR_UE_RA_fixes NR_UE_UL_DCI_improvements NR_UE_dlsch_bugfix NR_UE_enable_parallelization NR_UE_stability_fixes NR_UL_FAPI_programming NR_UL_scheduler NR_UL_scheduler_rebased NR_UL_scheduling NR_Wireshark NR_beam_simulation NR_beamforming_test NR_gNB_SCF_Indication NR_ipaccess_testing NR_mac_uci_functions_rework NR_msg2_phytest NR_scheduling_CSIRS NR_scheduling_request NR_scheduling_request2 NR_scheduling_request3 NR_test_S1U_RRC_PRACH_procedures NR_ue_dlsch_dmrs_cdm PUSCH_TA_update RA_CI_test UE_DL_DCI_hotfix bch-fixes-bitmap benetel_5g_prach_fix benetel_driver_uldl_pf_merge benetel_driver_update benetel_phase_rotation benetel_phase_rotation_old bugfix-minor-remove-wrong-log bugfix-nr-bands bugfix-nr-ldpc-post-processing bugfix-nr-ldpc-size-typo bugfix-nr-pdcp-sn-size bugfix-nr-rate-matching-assertion bugfix-x2-SgNBAdditionRequest bupt-sa-merge cce_indexing_fix cce_indexing_fix2 ci-deploy-asterix ci-deploy-docker-compose ci-rd-july-improvements ci-test ci-ul-iperf-from-trf-container clean-5G-scope-round2 cleanup_softmodem_main constant_power debug_branch_init_sync develop-SA-RA develop-SnT develop-oriecpriupdates develop-sib1 develop-sib1-local develop-sib1-lts develop-sib1-update develop-sib1-update-test1 develop-sib1-update-ue develop_inria_ci_deployment develop_inria_ci_deployment_gp develop_integration_2020_w15 develop_integration_2020_w19 develop_stable dfts_alternatives dlsch-all-dlslots dlsch_encode_mthread dlsch_parallel dongzhanyi-zte-develop dongzhanyi-zte-develop2 extend_sharedlibusage2 fapi_for_dmrs_and_ptrs feature-4g-sched feature/make-s1-mme-port-configurable feature/make-s1-mme-port-configurable-with-astyle-fixes fembms-enb-ue finalize-oaicn-integration firas fix-ci-tun fix-itti-segv fix-softmodem-restart fix-warnings fix_NR_DLUL_PF fix_do_ra_data fix_pdsch_low_prb fix_rfsim_mimo fix_rrc_x2_ticking fixes-CE-RLC-PDU-size fixes-mac-sched-nfapi fixes-mac-sched-tun fixes-tun flexran-apps flexran-repair-mme-mgmt fujitsu_lte_contribution fujitsu_lte_contribution-128 gnb-only-test harq-hotfix hotfix-minor-remove-nr-rlc-cppcheck-error hotfix-nr-rlc-tick hotfix-ocp-executable hotfix-ue-musim-compilation improve_nr_modulation improve_ue_stability integration_2020_wk40 integration_2020_wk41 integration_2020_wk42_2 integration_2020_wk45 integration_2020_wk45_2 integration_2020_wk46 integration_2020_wk46_2 integration_2020_wk47 integration_2020_wk48 integration_2020_wk48_2 integration_2020_wk49 integration_2020_wk50 integration_2020_wk50_1 integration_2020_wk51 integration_2020_wk51_2 integration_2021_wk02 integration_2021_wk02_wMR988 integration_2021_wk04 integration_2021_wk05 inter-RRU-final inter-RRU-oairu inter-rru-UE itti-enhancement l2-fixes ldpc-decoder-codegen ldpc-decoder-codegen2 ldpc-offload ldpc_short_codeword_fixes load_gnb lte-ulsch-bugfix lte_uplink_improvement mac-fixes-wk45_2 minor-fix-doc-basic-sim mosaic5g-oai-ran mosaic5g-oai-sim nasmesh_kernel_5.8 new-gtpu new_rlc_2020 nfapi-bugfix nfapi_nr_develop ngap-dlul ngap-support ngap-w48-merge2 ngap-wf ngap-wf-1120 ngap-wf-1120-srb ngap-wf-1120-srb-gtp ngap-wf-1120-srb-gtp-hs ngap-wf-1120-srb-gtp-hs1 ngap-wf-1120-srb-gtp-hs2 ngap-wf-1120-srb-gtp-yhz ngap-wf-1203-yunsdr ngap-wf-liuyu ngap_lfq_1120 ngap_merge noCore nr-dual-connectivity nr-mac-pdu-wireshark nr-mac-remove-ue-list nr-rlc-am-bugfix-w44 nr-rlc-bugfix-w44 nrUE nrUE-hs nrUE-upper-layer nr_bsr nr_dl_dmrs_type2 nr_dl_pf nr_dl_pf2 nr_dl_ul_ptrs nr_fdd_if_fix nr_polar_decoder_improvement nr_prach_fr2 nr_pucch nr_pucch2 nr_ue_msg3 nr_ue_tti_cleanup nr_ul_pf nr_ul_scfdma nrue-multi-thread nrue_msg2_reception nsa-ue nsa_remove_band_hardcodings oai-sim oairu oairu-dockerfile-support oc-docker-october-improvements openxg/develop pdcp-benchmark polar8 ptrs_rrc_config pusch-mthread-scaling-fix pusch-retrans-fix-ue ra-dl-ul remove_nos1_hack_pdcp remove_x2_gnb_hardcoding repair-TA revert_memcpy rh-ci-add-ue-parallelization rh_ci_fix_autoterminate rh_ci_fr1_update rh_ci_oc rh_ci_py rh_ci_ra_fr2 rh_ci_rfsim_ra rh_ci_ue_parallel rh_doc_update_3 rh_fr1_newjenkins rh_fr1_update rh_gnb_compile_fix rh_wk50_debug rlc-v2-bugfix-status-reporting rlc-v2-tick rlc_v2_coverity_fixes rrc-enb-phy-testmode s1-subnormal_rewrite s1_subnormal s1_subnormal-robert s1ap-bugfix-rab_setup sa-demo sa-merge-rrc-srb sa-msg4 sa-msg4-rrc sa-msg4-rrc-yihz sa-msg4-rrc-yihz-hs sa_rrc_yihz small-bugfixes-w40 small-config-change smallcleanup split73 testing_2symb_pdcch testing_with_external_txdata tp-ota-test trx_thread_param ue-csi ue-fixes ue-fixes-ota ue_beam_selection ue_nfapi_mch ul-freq-iq-samps-to-file ul_dl_dci_same_slot ul_harq ulsch_decode_mthread ulsim_changes usrp_fix_adc_shift_and_pps_sync wireshark-T-hack-ueid wireshark-log-scheduling-requests x2-endc-processing xiangwab xiangwan yihongzheng_srb zzs 2021.w04 2021.w02 2020.w51_2 2020.w51 2020.w50 2020.w49 2020.w48_2 2020.w48 2020.w47 2020.w46_2 2020.w46 2020.w45_2 2020.w45 2020.w44 2020.w42_2 2020.w42 2020.w41 2020.w39 2020.w38 2020.w37 2020.w36 2020.w34 2020.w33 2020.w31 2020.w30 2020.w29 2020.w28 2020.w26 2020.w25 2020.w24 2020.w23 2020.w22 2020.w19 2020.w17 2020.w16 2020.w15 benetel_phase_rotation
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......@@ -1098,6 +1098,13 @@ void fill_rf_config(RU_t *ru, char *rf_config_file) {
} else {
AssertFatal(0==1,"N_RB %d not yet supported for numerology %d\n",N_RB,mu);
}
} else if (mu == NR_MU_3) {
if (N_RB == 66) {
cfg->sample_rate = 122.88e6;
cfg->samples_per_frame = 1228800;
cfg->tx_bw = 100e6;
cfg->rx_bw = 100e6;
}
} else {
AssertFatal(0 == 1,"Numerology %d not supported for the moment\n",mu);
}
......
......@@ -127,7 +127,7 @@ extern pthread_mutex_t sync_mutex;
extern int sync_var;
extern uint32_t downlink_frequency[MAX_NUM_CCs][4];
extern uint64_t downlink_frequency[MAX_NUM_CCs][4];
extern int32_t uplink_frequency_offset[MAX_NUM_CCs][4];
extern int rx_input_level_dBm;
......
......@@ -113,7 +113,7 @@ int single_thread_flag=1;
static int8_t threequarter_fs=0;
uint32_t downlink_frequency[MAX_NUM_CCs][4];
uint64_t downlink_frequency[MAX_NUM_CCs][4];
int32_t uplink_frequency_offset[MAX_NUM_CCs][4];
//Temp fix for inexisting NR upper layer
......
......@@ -170,7 +170,6 @@ static void UE_synch(void *arg) {
UE->is_synchronized = 0;
if (UE->UE_scan == 0) {
LOG_I( PHY, "[SCHED][UE] Check absolute frequency DL %"PRIu64", UL %"PRIu64" (oai_exit %d, rx_num_channels %d)\n",
UE->frame_parms.dl_CarrierFreq, UE->frame_parms.ul_CarrierFreq,
oai_exit, openair0_cfg[0].rx_num_channels);
......@@ -292,6 +291,12 @@ static void UE_synch(void *arg) {
openair0_cfg[UE->rf_map.card].tx_bw=10.0e6;
// openair0_cfg[0].rx_gain[0] -= 0;
break;
case 66:
openair0_cfg[UE->rf_map.card].sample_rate=122.88e6;
openair0_cfg[UE->rf_map.card].rx_bw=100.e6;
openair0_cfg[UE->rf_map.card].tx_bw=100.e6;
break;
}
if (UE->mode != loop_through_memory) {
......@@ -610,7 +615,6 @@ void *UE_thread(void *arg) {
openair0_timestamp timestamp;
void *rxp[NB_ANTENNAS_RX], *txp[NB_ANTENNAS_TX];
int start_rx_stream = 0;
const uint16_t table_sf_slot[20] = {0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9};
AssertFatal(0== openair0_device_load(&(UE->rfdevice), &openair0_cfg[0]), "");
UE->rfdevice.host_type = RAU_HOST;
AssertFatal(UE->rfdevice.trx_start_func(&UE->rfdevice) == 0, "Could not start the device\n");
......@@ -696,7 +700,7 @@ void *UE_thread(void *arg) {
curMsg->UE->current_thread_id[slot_nr] = thread_idx;
curMsg->proc.CC_id = 0;
curMsg->proc.nr_tti_rx= slot_nr;
curMsg->proc.subframe_rx=table_sf_slot[slot_nr];
curMsg->proc.subframe_rx=slot_nr/(nb_slot_frame/10);
curMsg->proc.nr_tti_tx = (absolute_slot + DURATION_RX_TO_TX) % nb_slot_frame;
curMsg->proc.subframe_tx=curMsg->proc.nr_tti_rx;
curMsg->proc.frame_rx = ((absolute_slot/nb_slot_frame)+UE->frame_gap) % MAX_FRAME_NUMBER;
......
......@@ -122,7 +122,7 @@ static double snr_dB=20;
int threequarter_fs=0;
uint32_t downlink_frequency[MAX_NUM_CCs][4];
uint64_t downlink_frequency[MAX_NUM_CCs][4];
int32_t uplink_frequency_offset[MAX_NUM_CCs][4];
......@@ -518,7 +518,15 @@ void init_openair0(void) {
openair0_cfg[card].configFilename = NULL;
openair0_cfg[card].threequarter_fs = frame_parms[0]->threequarter_fs;
if(frame_parms[0]->N_RB_DL == 217) {
if(frame_parms[0]->N_RB_DL == 66) {
if (numerology==3) {
openair0_cfg[card].sample_rate=122.88e6;
openair0_cfg[card].samples_per_frame = 1228800;
} else {
LOG_E(PHY,"Unsupported numerology! FR2 supports only 120KHz SCS for now.\n");
exit(-1);
}
}else if(frame_parms[0]->N_RB_DL == 217) {
if (numerology==1) {
if (frame_parms[0]->threequarter_fs) {
openair0_cfg[card].sample_rate=92.16e6;
......
......@@ -69,7 +69,7 @@
{"single-thread-disable", CONFIG_HLP_NOSNGLT, PARAMFLAG_BOOL, iptr:&single_thread_flag, defintval:1, TYPE_INT, 0}, \
{"nr-dlsch-demod-shift", CONFIG_HLP_DLSHIFT, 0, iptr:(int32_t *)&nr_dlsch_demod_shift, defintval:0, TYPE_INT, 0}, \
{"A" , CONFIG_HLP_TADV, 0, uptr:&timing_advance, defintval:0, TYPE_UINT, 0}, \
{"C" , CONFIG_HLP_DLF, 0, uptr:&(downlink_frequency[0][0]), defuintval:2680000000, TYPE_UINT, 0}, \
{"C" , CONFIG_HLP_DLF, 0, uptr:&(downlink_frequency[0][0]), defuintval:2680000000, TYPE_UINT64, 0}, \
{"a" , CONFIG_HLP_CHOFF, 0, iptr:&chain_offset, defintval:0, TYPE_INT, 0}, \
{"d" , CONFIG_HLP_SOFTS, PARAMFLAG_BOOL, uptr:&do_forms, defintval:0, TYPE_INT, 0}, \
{"E" , CONFIG_HLP_TQFS, PARAMFLAG_BOOL, iptr:&threequarter_fs, defintval:0, TYPE_INT, 0}, \
......@@ -79,7 +79,7 @@
{"S" , CONFIG_HLP_MSLOTS, PARAMFLAG_BOOL, u8ptr:&exit_missed_slots, defintval:1, TYPE_UINT8, 0}, \
{"T" , CONFIG_HLP_TDD, PARAMFLAG_BOOL, iptr:&tddflag, defintval:0, TYPE_INT, 0}, \
{"V" , CONFIG_HLP_VCD, PARAMFLAG_BOOL, iptr:&vcdflag, defintval:0, TYPE_INT, 0}, \
{"numerology" , CONFIG_HLP_NUMEROLOGY, PARAMFLAG_BOOL, iptr:&numerology, defintval:0, TYPE_INT, 0}, \
{"numerology" , CONFIG_HLP_NUMEROLOGY, 0, iptr:&numerology, defintval:0, TYPE_INT, 0}, \
{"emulate-rf" , CONFIG_HLP_EMULATE_RF, PARAMFLAG_BOOL, iptr:&emulate_rf, defintval:0, TYPE_INT, 0}, \
{"parallel-config", CONFIG_HLP_PARALLEL_CMD,0, strptr:(char **)&parallel_config, defstrval:NULL, TYPE_STRING, 0}, \
{"worker-config", CONFIG_HLP_WORKER_CMD, 0, strptr:(char **)&worker_config, defstrval:NULL, TYPE_STRING, 0}, \
......
......@@ -979,14 +979,14 @@ void set_default_frame_parms_single(nfapi_nr_config_request_t *config,
config->subframe_config.numerology_index_mu.value =1;
config->subframe_config.duplex_mode.value = 1; //FDD
config->subframe_config.dl_cyclic_prefix_type.value = 0; //NORMAL
config->rf_config.dl_carrier_bandwidth.value = 106;
config->rf_config.ul_carrier_bandwidth.value = 106;
config->rf_config.dl_carrier_bandwidth.value = 100;
config->rf_config.ul_carrier_bandwidth.value = 100;
config->sch_config.physical_cell_id.value = 0;
frame_parms->frame_type = FDD;
//frame_parms[CC_id]->tdd_config_S = 0;
frame_parms->N_RB_DL = 100;
frame_parms->N_RB_UL = 100;
frame_parms->N_RB_DL = 106;
frame_parms->N_RB_UL = 106;
frame_parms->Ncp = NORMAL;
//frame_parms[CC_id]->Ncp_UL = NORMAL;
frame_parms->Nid_cell = 0;
......
......@@ -191,9 +191,16 @@ void set_scs_parameters (NR_DL_FRAME_PARMS *fp, int mu)
break;
case NR_MU_3:
fp->subcarrier_spacing = nr_subcarrier_spacing[NR_MU_3];
fp->slots_per_subframe = nr_slots_per_subframe[NR_MU_3];
fp->ssb_type = nr_ssb_type_D;
switch(N_RB_DL){
case 66:
fp->ofdm_symbol_size = 1024;
fp->first_carrier_offset = 628; //1024 - ( (66*12) / 2 )
fp->nb_prefix_samples0 = 88;
fp->nb_prefix_samples = 72;
fp->subcarrier_spacing = nr_subcarrier_spacing[NR_MU_3];
fp->slots_per_subframe = nr_slots_per_subframe[NR_MU_3];
fp->ssb_type = nr_ssb_type_D;
}
break;
case NR_MU_4:
......
......@@ -117,8 +117,8 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue,
return(-1);
}*/
if (Ns<0 || Ns>=20) {
printf("slot_fep: Ns must be between 0 and 19\n");
if (Ns<0 || Ns>=(frame_parms->slots_per_frame-1)) {
printf("slot_fep: Ns must be between 0 and %d\n",frame_parms->slots_per_frame-1);
return(-1);
}
......
......@@ -86,7 +86,7 @@ void nr_common_signal_procedures (PHY_VARS_gNB *gNB,int frame, int slot) {
if ((slot==8) || (slot==9) || (slot==18) || (slot==19) || (slot==28) || (slot==29))
gNB->skipped_slots = gNB->skipped_slots + 1;
else {
if(rel_slot<slots_per_hf && rel_slot>=0) {
if(rel_slot<38 && rel_slot>=0) { // there is no SSB beyond slot 37
for (int i=0; i<2; i++) { // max two SSB per frame
ssb_index = i + ((rel_slot - gNB->skipped_slots)<<1); // computing the ssb_index
......@@ -95,7 +95,7 @@ void nr_common_signal_procedures (PHY_VARS_gNB *gNB,int frame, int slot) {
fp->ssb_index = ssb_index;
int ssb_start_symbol_abs = nr_get_ssb_start_symbol(fp); // computing the starting symbol for current ssb
ssb_start_symbol = ssb_start_symbol_abs % fp->symbols_per_slot; // start symbol wrt slot
nr_set_ssb_first_subcarrier(cfg, fp); // setting the first subcarrier
LOG_D(PHY,"SS TX: frame %d, slot %d, start_symbol %d\n",frame,slot, ssb_start_symbol);
......@@ -294,6 +294,7 @@ void nr_fill_rx_indication(PHY_VARS_gNB *gNB, int frame, int slot_rx, int ULSCH_
case 106: timing_advance_update /= 16; break;
case 217: timing_advance_update /= 32; break;
case 273: timing_advance_update /= 32; break;
case 66: timing_advance_update /= 12; break;
default: abort();
}
......
......@@ -128,7 +128,7 @@ int nr_generate_ue_ul_dlsch_params_from_dci(PHY_VARS_NR_UE *ue,
*/
#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
extern uint32_t downlink_frequency[MAX_NUM_CCs][4];
extern uint64_t downlink_frequency[MAX_NUM_CCs][4];
#endif
......
......@@ -78,7 +78,7 @@ extern double cpuf;
void Msg1_transmitted(module_id_t module_idP, uint8_t CC_id, frame_t frameP, uint8_t eNB_id);
void Msg3_transmitted(module_id_t module_idP, uint8_t CC_id, frame_t frameP, uint8_t eNB_id);
extern uint32_t downlink_frequency[MAX_NUM_CCs][4];
extern uint64_t downlink_frequency[MAX_NUM_CCs][4];
void get_dumpparam(PHY_VARS_UE *ue,
UE_rxtx_proc_t *proc,
......
......@@ -92,7 +92,7 @@ int main(int argc, char **argv)
//char input_val_str[50],input_val_str2[50];
//uint16_t NB_RB=25;
SCM_t channel_model = AWGN; //Rayleigh1_anticorr;
uint16_t N_RB_DL = 106, mu = 1;
uint16_t N_RB_DL = 106, mu = 1;
//unsigned char frame_type = 0;
unsigned char pbch_phase = 0;
int frame = 0, slot = 0;
......
......@@ -202,7 +202,6 @@ int main(int argc, char **argv)
int N_RB_DL=106,mu=1;
nfapi_nr_dl_tti_pdsch_pdu_rel15_t dlsch_config;
//unsigned char frame_type = 0;
int frame=0,slot=1;
......@@ -381,6 +380,7 @@ int main(int argc, char **argv)
case 'I':
run_initial_sync=1;
target_error_rate=0.1;
slot = 0;
break;
case 'L':
......@@ -546,6 +546,10 @@ int main(int argc, char **argv)
fs = 61.44e6;
bw = 40e6;
}
else if (mu == 3 && N_RB_DL == 66) {
fs = 122.88e6;
bw = 100e6;
}
else AssertFatal(1==0,"Unsupported numerology for mu %d, N_RB %d\n",mu, N_RB_DL);
gNB2UE = new_channel_desc_scm(n_tx,
......@@ -619,7 +623,6 @@ int main(int argc, char **argv)
nr_gold_pbch(UE);
nr_gold_pdcch(UE,0,2);
nr_l2_init_ue(NULL);
UE_mac = get_mac_inst(0);
......@@ -651,7 +654,6 @@ int main(int argc, char **argv)
if (mcsIndex_set==0) dlsch_config.mcsIndex[0]=9;
if (rbSize_set==0) dlsch_config.rbSize=N_RB_DL;
if (rbStart_set==0) dlsch_config.rbStart=0;
//Configure UE
......
......@@ -79,7 +79,7 @@
extern uint16_t sf_ahead;
extern int config_check_band_frequencies(int ind, int16_t band, uint32_t downlink_frequency,
extern int config_check_band_frequencies(int ind, int16_t band, uint64_t downlink_frequency,
int32_t uplink_frequency_offset, uint32_t frame_type);
void prepare_scc(NR_ServingCellConfigCommon_t *scc) {
......@@ -646,7 +646,6 @@ void RCconfig_NRRRC(MessageDef *msg_p, uint32_t i, gNB_RRC_INST *rrc) {
// Parse optional physical parameters
sprintf(gnbpath,"%s.[%i]",GNB_CONFIG_STRING_GNB_LIST,k),
printf("SSB SCO %d\n",ssb_SubcarrierOffset);
NRRRC_CONFIGURATION_REQ (msg_p).ssb_SubcarrierOffset = ssb_SubcarrierOffset;
printf("pdsch_AntennaPorts %d\n",pdsch_AntennaPorts);
......
......@@ -230,7 +230,7 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm
}
break;
default:
AssertFatal(1==0,"SSB bitmap size value %d undefined (allowed values 1,2,3) \n", scc->ssb_PositionsInBurst->present);
AssertFatal(1==0,"SSB bitmap size value %d undefined (allowed values 1,2,3) \n", scc->ssb_PositionsInBurst->present)
}
cfg->ssb_table.ssb_mask_list[0].ssb_mask.tl.tag = NFAPI_NR_CONFIG_SSB_MASK_TAG;
cfg->num_tlv++;
......
......@@ -42,6 +42,7 @@ void config_common(int Mod_idP,
int pdsch_AntennaPorts,
NR_ServingCellConfigCommon_t *scc
);
int rrc_mac_config_req_gNB(module_id_t Mod_idP,
int ssb_SubcarrierOffset,
int pdsch_AntennaPorts,
......
......@@ -64,7 +64,8 @@ nr_bandentry_t nr_bandtable[] = {
{82, 832000, 862000, 000, 000, 20, 166400},
{83, 703000, 748000, 000, 000, 20, 140600},
{84, 1920000, 1980000, 000, 000, 20, 384000},
{86, 1710000, 1785000, 000, 000, 20, 342000}
{86, 1710000, 1785000, 000, 000, 20, 342000},
{257, 26500000, 29500000,26500000,29500000, 1, 2054167}
};
#define NR_BANDTABLE_SIZE (sizeof(nr_bandtable)/sizeof(nr_bandentry_t))
......@@ -234,8 +235,8 @@ uint32_t to_nrarfcn(int nr_bandP,
int i;
LOG_I(MAC,"Searching for nr band %d DL Carrier frequency %llu bw %u\n",nr_bandP,(long long unsigned int)dl_CarrierFreq,bw);
AssertFatal(nr_bandP < 86, "nr_band %d > 86\n", nr_bandP);
for (i = 0; i < 30 && nr_bandtable[i].band != nr_bandP; i++);
AssertFatal(nr_bandP < 258, "nr_band %d > 257\n", nr_bandP);
for (i = 0; i < 33 && nr_bandtable[i].band != nr_bandP; i++);
AssertFatal(dl_CarrierFreq_by_1k >= nr_bandtable[i].dl_min,
"Band %d, bw %u : DL carrier frequency %llu kHz < %llu\n",
......@@ -267,8 +268,8 @@ uint64_t from_nrarfcn(int nr_bandP,
if (nr_bandP < 77 || nr_bandP > 79) deltaFglobal = 5;
else deltaFglobal = 15;
AssertFatal(nr_bandP < 87, "nr_band %d > 86\n", nr_bandP);
for (i = 0; i < 31 && nr_bandtable[i].band != nr_bandP; i++);
AssertFatal(nr_bandP < 258, "nr_band %d > 257\n", nr_bandP);
for (i = 0; i < 33 && nr_bandtable[i].band != nr_bandP; i++);
AssertFatal(dl_nrarfcn>=nr_bandtable[i].N_OFFs_DL,"dl_nrarfcn %u < N_OFFs_DL %llu\n",dl_nrarfcn, (long long unsigned int)nr_bandtable[i].N_OFFs_DL);
LOG_I(PHY,"Computing dl_frequency (pointA %llu => %llu (dlmin %llu, nr_bandtable[%d].N_OFFs_DL %llu))\n",
......
......@@ -264,7 +264,7 @@ extern pthread_cond_t sync_cond;
extern pthread_mutex_t sync_mutex;
extern int sync_var;
extern uint32_t downlink_frequency[MAX_NUM_CCs][4];
extern uint64_t downlink_frequency[MAX_NUM_CCs][4];
extern int32_t uplink_frequency_offset[MAX_NUM_CCs][4];
extern int rx_input_level_dBm;
......
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