Commit 284c4413 authored by Calvin HSU's avatar Calvin HSU

UE: Add DCI_IND in phy_procedures_nr_ue. Fill type0-pdcch in scheduled_response

parent bb47c46c
develop 1 128-ues 256_QAM_demod 375-syrtem-sdr-platform 408-reworked 408-ue-main-threads 445-LDPC-implementation-on-GPU 459-pusch-based-ta-updates 464-ru_beamforming_in_gpu 464-ru_beamforming_in_gpu-CPUsubfunction 472-add-pusch-dmrs-modes 481-ldpc-decoder-on-gpu 5g_fapi_scf LTE_TRX_on_single_port NCTU_CS_ISIP NCTU_CS_ISIP_CPU NCTU_CS_ISIP_GPU NCTU_OpinConnect_LDPC NR-PHY-MAC-IF-multi-UE NRUE_usedlschparallel NR_10MHz NR_CSI_reporting NR_DCI_01 NR_DLUL_PF NR_DLUL_PF_4UL NR_DLUL_PF_rebased NR_DL_MIMO NR_DL_sched_fixes NR_DL_scheduler NR_FAPI_beamindex_SSB_RO NR_FDD_FIX NR_FR2_RA NR_FR2_RRC_SSB NR_MAC_CE_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge NR_MAC_SSB_RO_GlobalEdge NR_MAC_SSB_RO_UE_IDCC NR_MAC_SSB_RO_merge NR_MAC_TCI_UCI_GlobalEdge NR_NGAP NR_PDCP_noS1 NR_PUCCH_MultiUE NR_RA_cleanup NR_RA_updates NR_RRCConfiguragion_FR2 NR_RRCConfiguration NR_RRCConfiguration_FR2 NR_RRCConfiguration_S1U NR_RRCConfiguration_merge_develop NR_RRCConfiguration_sync_source NR_RRCConfiguration_trx_thread NR_RRC_CP_bugfix NR_RRC_PDCP NR_RRC_PRACH_procedures NR_RRC_PRACH_procedures_todevelop NR_RRC_PUSCH NR_RRC_TA NR_RRC_X2AP_AMBR_Change_Global_edge NR_RRC_X2AP_RemoveHardcodings_GlobalEdge NR_RRC_config_simplified NR_RRC_harq NR_RRC_harq_b NR_RRC_harq_hacks NR_RRC_harq_newdcipdu NR_SA_F1AP_RFSIMULATOR NR_SA_F1AP_RFSIMULATOR2 NR_SA_F1AP_dev NR_SA_NGAP_RRC NR_SA_NGAP_RRC_wk42 NR_SA_itti_sim_wk48 NR_SA_itti_sim_wk48_hs NR_SA_itti_sim_wk48_hs1 NR_SCHED NR_SCHED_HARQ NR_SCHED_PDCCH_PUCCH_HARQ NR_SCHED_PDCCH_PUCCH_HARQ_rebased NR_SCHED_fixes NR_SRB_Config NR_TRX_on_single_port NR_TRX_on_single_port2 NR_UE_MAC_scheduler NR_UE_RA_fixes NR_UE_UL_DCI_improvements NR_UE_dlsch_bugfix NR_UE_enable_parallelization NR_UE_stability_fixes NR_UL_FAPI_programming NR_UL_scheduler NR_UL_scheduler_rebased NR_UL_scheduling NR_Wireshark NR_beam_simulation NR_beamforming_test NR_gNB_SCF_Indication NR_ipaccess_testing NR_mac_uci_functions_rework NR_msg2_phytest NR_scheduling_CSIRS NR_scheduling_request NR_scheduling_request2 NR_scheduling_request3 NR_test_S1U_RRC_PRACH_procedures NR_ue_dlsch_dmrs_cdm OpInConnect_ISIP PUSCH_TA_update RA_CI_test UE_DL_DCI_hotfix addoptions_nr_USRPdevice bch-fixes-bitmap benetel_5g_prach_fix benetel_driver_uldl_pf_merge benetel_driver_update benetel_phase_rotation benetel_phase_rotation_old bugfix-minor-remove-wrong-log bugfix-nr-bands bugfix-nr-ldpc-post-processing bugfix-nr-ldpc-size-typo bugfix-nr-pdcp-sn-size bugfix-nr-rate-matching-assertion bugfix-x2-SgNBAdditionRequest bupt-sa-merge cce_indexing_fix cce_indexing_fix2 ci-deploy-asterix ci-deploy-docker-compose ci-rd-july-improvements ci-test ci-ul-iperf-from-trf-container clean-5G-scope-round2 cleanup_softmodem_main constant_power debug_branch_init_sync develop-SA-RA develop-SnT develop-ci develop-nr develop-nr-adding-2018-09-asn1 develop-nr-fr2 develop-nr-fr2-rework develop-nr_cppcheck develop-oriecpriupdates develop-sib1 develop-sib1-local develop-sib1-lts develop-sib1-update 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fixes-tun flexran-apps flexran-improvements flexran-repair-mme-mgmt fr2-hw-test fujitsu_lte_contribution fujitsu_lte_contribution-128 gNB-nrUE-USRP generate_push_ptrs gnb-only-test harq-hotfix hotfix-minor-remove-nr-rlc-cppcheck-error hotfix-nr-rlc-tick hotfix-ocp-executable hotfix-ue-musim-compilation hotfix_usrp_lib improve_build_nr_lte_merge improve_nr_modulation improve_ue_stability integration-develop-nr-2019w45 integration_2020_wk40 integration_2020_wk41 integration_2020_wk42_2 integration_2020_wk45 integration_2020_wk45_2 integration_2020_wk46 integration_2020_wk46_2 integration_2020_wk47 integration_2020_wk48 integration_2020_wk48_2 integration_2020_wk49 integration_2020_wk50 integration_2020_wk50_1 integration_2020_wk51 integration_2020_wk51_2 integration_2021_wk02 integration_2021_wk02_wMR988 integration_2021_wk04 integration_2021_wk05 inter-RRU-final inter-RRU-nr inter-RRU-oairu inter-rru-UE interoperability-test isip_nr itti-enhancement l2-fixes ldpc-dec-layering ldpc-decoder-codegen ldpc-decoder-codegen2 ldpc-decoder-improvements ldpc-offload ldpc_short_codeword_fixes load_gnb lte-ulsch-bugfix lte_uplink_improvement mac-fixes-wk45_2 mbms-fix-develop-nr merging-2019-w51-to-develop-nr minor-fix-doc-basic-sim mosaic5g-oai-ran mosaic5g-oai-sim nasmesh_kernel_5.8 new-gtpu new_rlc_2020 nfapi-bugfix nfapi_nr_develop ngap-dlul ngap-support ngap-w48-merge2 ngap-wf ngap-wf-1120 ngap-wf-1120-srb ngap-wf-1120-srb-gtp ngap-wf-1120-srb-gtp-hs ngap-wf-1120-srb-gtp-hs1 ngap-wf-1120-srb-gtp-hs2 ngap-wf-1120-srb-gtp-yhz ngap-wf-1203-yunsdr ngap-wf-liuyu ngap_lfq_1120 ngap_merge noCore nr-coreset-bug-fix nr-dlsch-multi-thread nr-dlsch-thread nr-dual-connectivity nr-interdigital-test nr-ip-uplink-noS1 nr-mac-pdu-wireshark nr-mac-remove-ue-list nr-multiple-ssb nr-pdcp nr-pdsch-extraction-bugfix nr-physim-update nr-rlc-am-bugfix-w44 nr-rlc-bugfix-w44 nr-ssb-measurements nr-timing-measurement nr-timing-measurement-merge nr-ue-buffer-status nr-ue-slot-based nr-uldci nrUE nrUE-hs nrUE-upper-layer nr_beamforming nr_bsr nr_ci_dlsim nr_csi_newbranch nr_dci_procedures nr_demo_wsa2019 nr_dl_dmrs_type2 nr_dl_pf nr_dl_pf2 nr_dl_ul_ptrs nr_dlsch_parallel_measurements nr_dlsim_plot nr_fapi_for_push_tmp nr_fdd_if_fix nr_fix_easycppcheck nr_flexible_NRBDL nr_improve_build_procedures nr_increase_tp nr_mib_vsa_test nr_pdcch_testing nr_pdcch_updates nr_pdsch_integration nr_polar_decoder_improvement nr_prach nr_prach_fr2 nr_pucch nr_pucch2 nr_segmentation_fixes nr_sim_fix nr_tdd_configuration nr_ue_msg3 nr_ue_tti_cleanup nr_ul_pf nr_ul_scfdma nr_vcd nrue-multi-thread nrue_msg2_reception nsa-ue nsa_remove_band_hardcodings oai-sim oai-ubuntu-docker oai-ubuntu-docker-for-lmssdr oairu oairu-dockerfile-support oc-docker-october-improvements openxg/develop pdcp-benchmark pdsch-ch-est polar8 ptrs_rrc_config pusch-mthread-scaling-fix pusch-retrans-fix-ue ra-dl-ul reduce_memory_footprint remove-ci-workaround remove_nos1_hack_pdcp remove_x2_gnb_hardcoding repair-TA revert-f5c94279 revert_memcpy rh-ci-add-ue-parallelization rh_ci_fix_autoterminate rh_ci_fr1_update rh_ci_oc rh_ci_py rh_ci_ra_fr2 rh_ci_rfsim_ra rh_ci_ue_parallel rh_doc_update_3 rh_fr1_newjenkins rh_fr1_update rh_gnb_compile_fix rh_wk50_debug rlc-v2-bugfix-status-reporting rlc-v2-tick rlc_v2_coverity_fixes rrc-enb-phy-testmode ru-parallel-beamforming runel runel-reverse-test s1-subnormal_rewrite s1_subnormal s1_subnormal-robert s1ap-bugfix-rab_setup sa-demo sa-merge-rrc-srb sa-msg4 sa-msg4-rrc sa-msg4-rrc-yihz sa-msg4-rrc-yihz-hs sa_rrc_yihz small-bugfixes-w40 small-config-change smallcleanup softmodem_cleanup split73 test-x310-perf testing_2symb_pdcch testing_with_external_txdata thread-pool tools_5Gadapt tp-ota-test trx_thread_param trx_write_thread ue-csi ue-fixes ue-fixes-ota ue-updates-runel-test ue_adjust_gain ue_beam_selection ue_dlsch-multi-threading ue_dlsch_decoding_ldpc_offload ue_nfapi_mch uhd_priority_set_cleanup ul-freq-iq-samps-to-file ul_dl_dci_same_slot ul_harq ulsch_decode_mthread ulsim_changes update-to-2019-march-june-release usrp_fix_adc_shift_and_pps_sync usrp_gpio_test wireshark-T-hack-ueid wireshark-log-scheduling-requests x2-endc-processing xiangwab xiangwan yihongzheng_srb zzs 2021.w04 2021.w02 2020.w51_2 2020.w51 2020.w50 2020.w49 2020.w48_2 2020.w48 2020.w47 2020.w46_2 2020.w46 2020.w45_2 2020.w45 2020.w44 2020.w42_2 2020.w42 2020.w41 2020.w39 2020.w38 2020.w37 2020.w36 2020.w34 2020.w33 2020.w31 2020.w30 2020.w29 2020.w28 2020.w26 2020.w25 2020.w24 2020.w23 2020.w22 2020.w19 2020.w17 2020.w16 2020.w15 2020.w11 2020.w09 2020.w06 2020.w05 2020.w04 2020.w03 osa-etsi-ws-ue osa-etsi-ws-try2 osa-etsi-ws-try1 osa-etsi-ws-gNB nr-ip-over-lte nr-ip-over-lte-v.1.5 nr-ip-over-lte-v.1.4 nr-ip-over-lte-v.1.3 nr-ip-over-lte-v.1.2 nr-ip-over-lte-v.1.1 nr-ip-over-lte-v.1.0 develop-nr-pdcch develop-nr-2020w03 develop-nr-2020w02 develop-nr-2019w51 develop-nr-2019w50 develop-nr-2019w48 develop-nr-2019w47 develop-nr-2019w45 develop-nr-2019w43 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...@@ -34,6 +34,9 @@ ...@@ -34,6 +34,9 @@
/// DL_CONFIG_REQ /// DL_CONFIG_REQ
#define FAPI_NR_DL_CONFIG_LIST_NUM 10
#define FAPI_NR_DL_CONFIG_TYPE_DCI 0x01 #define FAPI_NR_DL_CONFIG_TYPE_DCI 0x01
#define FAPI_NR_DL_CONFIG_TYPE_DLSCH 0x02 #define FAPI_NR_DL_CONFIG_TYPE_DLSCH 0x02
...@@ -44,5 +47,7 @@ ...@@ -44,5 +47,7 @@
#define PRECODER_GRANULARITY_ALL_CONTIGUOUS_RBS 0x02 #define PRECODER_GRANULARITY_ALL_CONTIGUOUS_RBS 0x02
/// UL_CONFIG_REQ /// UL_CONFIG_REQ
#define FAPI_NR_UL_CONFIG_LIST_NUM 10
#endif #endif
\ No newline at end of file
...@@ -713,30 +713,6 @@ int nr_rx_pbch( PHY_VARS_NR_UE *ue, ...@@ -713,30 +713,6 @@ int nr_rx_pbch( PHY_VARS_NR_UE *ue,
ue->if_inst->dl_indication(&ue->dl_indication); ue->if_inst->dl_indication(&ue->dl_indication);
// dci reception part, should be put into dci_nr.c ? TBD
#if 0
ue->dl_indication.dci_ind = &ue->dci_ind; // hang on rx_ind instance
//ue->dci_ind.sfn_slot = 0; //should be set by higher-1-layer, i.e. clean_and_set_if_instance()
uint32_t num_dci = 1;
uint32_t ii;
ue->dci_ind.number_of_dcis = num_dci;
ue->dci_ind.dci_list = (fapi_nr_dci_indication_pdu_t *)malloc(num_dci * sizeof(fapi_nr_dci_indication_pdu_t));
for(ii=0; ii<num_dci; ++ii){
//TODO check this part
(ue->dci_ind.dci_list+ii)->rnti = 0x0000;
(ue->dci_ind.dci_list+ii)->dci_type = 0;
// TODO to be fill with TCL
//ue->dci_ind.dci_list[ii]->dci.
}
ue->if_inst->dl_indication(&ue->dl_indication);
#endif
return 0; return 0;
} }
......
...@@ -921,6 +921,8 @@ typedef struct { ...@@ -921,6 +921,8 @@ typedef struct {
// SEARCHSPACE structure, where maximum number of SEARCHSPACEs to be handled is 10 (according to 38.331 V15.1.0) // SEARCHSPACE structure, where maximum number of SEARCHSPACEs to be handled is 10 (according to 38.331 V15.1.0)
// Each SearchSpace is associated with one ControlResourceSet // Each SearchSpace is associated with one ControlResourceSet
NR_UE_PDCCH_SEARCHSPACE searchSpace[NR_NBR_SEARCHSPACE_ACT_BWP]; NR_UE_PDCCH_SEARCHSPACE searchSpace[NR_NBR_SEARCHSPACE_ACT_BWP];
uint32_t nb_search_space;
#endif #endif
} NR_UE_PDCCH; } NR_UE_PDCCH;
......
...@@ -41,61 +41,109 @@ extern PHY_VARS_NR_UE ***PHY_vars_UE_g; ...@@ -41,61 +41,109 @@ extern PHY_VARS_NR_UE ***PHY_vars_UE_g;
int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
if(scheduled_response != NULL){ /// module id
if(scheduled_response->dl_config != NULL){ module_id_t module_id = scheduled_response->module_id;
/// component carrier id
} uint8_t cc_id = scheduled_response->CC_id;
uint32_t i;
if(scheduled_response->ul_config != NULL){
if(scheduled_response != NULL){
} if(scheduled_response->dl_config != NULL){
fapi_nr_dl_config_request_t *dl_config = scheduled_response->dl_config;
if(scheduled_response->tx_request != NULL){
} for(i=0; i<dl_config->number_pdus; ++i){
} if(dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_DCI){
PHY_vars_UE_g[module_id][cc_id]->nb_search_space = PHY_vars_UE_g[module_id][cc_id]->nb_search_space + 1;
return 0; fapi_nr_dl_config_dci_dl_pdu_rel15_t *dci_config = &dl_config->dl_config_list[i].dci_config_pdu.dci_config_rel15;
pdcch_vars2->searchSpace[i].monitoringSymbolWithinSlot = dci_config.monitoring_symbols_within_slot;
pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel1 = dci_config.number_of_candidates[0];
pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel2 = dci_config.number_of_candidates[1];
pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel4 = dci_config.number_of_candidates[2];
pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel8 = dci_config.number_of_candidates[3];
pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel16 = dci_config.number_of_candidates[4];
pdcch_vars2->coreset[i].duration = dci_config.coreset.duration;
//pdcch_vars2->coreset[i].frequencyDomainResources;
//dci_config.coreset.rb_start;
//dci_config.coreset.rb_end;
if(dci_config.cce_reg_mapping_type == CCE_REG_MAPPING_TYPE_INTERLEAVED){
pdcch_vars2->coreset[i].cce_reg_mappingType.shiftIndex = cce_reg_interleaved_shift_index;
pdcch_vars2->coreset[i].cce_reg_mappingType.reg_bundlesize = cce_reg_interleaved_reg_bundle_size;
pdcch_vars2->coreset[i].cce_reg_mappingType.interleaversize = cce_reg_interleaved_interleaver_size;
}else{
;
}
pdcch_vars2->coreset[i].precoderGranularity = dci_config.precoder_granularity;
//pdcch_vars2->coreset[i].tciStatesPDCCH;
//pdcch_vars2->coreset[i].tciPresentInDCI;
pdcch_vars2->coreset[i].pdcchDMRSScramblingID = dci_config.pdcch_dmrs_scrambling_id;
}else{ //FAPI_NR_DL_CONFIG_TYPE_DLSCH
// dlsch config pdu
}
}
}else{
PHY_vars_UE_g[module_id][cc_id]->nb_search_space = 0;
}
if(scheduled_response->ul_config != NULL){
}else{
}
if(scheduled_response->tx_request != NULL){
}else{
}
}
return 0;
} }
int8_t nr_ue_phy_config_request(nr_phy_config_t *phy_config){ int8_t nr_ue_phy_config_request(nr_phy_config_t *phy_config){
if(phy_config != NULL){ if(phy_config != NULL){
if(phy_config->config_req.config_mask & FAPI_NR_CONFIG_REQUEST_MASK_PBCH){ if(phy_config->config_req.config_mask & FAPI_NR_CONFIG_REQUEST_MASK_PBCH){
printf("[L1][IF module][PHY CONFIG]\n"); printf("[L1][IF module][PHY CONFIG]\n");
printf("subcarrier spacing: %d\n", phy_config->config_req.pbch_config.subcarrier_spacing_common); printf("subcarrier spacing: %d\n", phy_config->config_req.pbch_config.subcarrier_spacing_common);
printf("ssb carrier offset: %d\n", phy_config->config_req.pbch_config.ssb_subcarrier_offset); printf("ssb carrier offset: %d\n", phy_config->config_req.pbch_config.ssb_subcarrier_offset);
printf("dmrs type A position: %d\n", phy_config->config_req.pbch_config.dmrs_type_a_position); printf("dmrs type A position: %d\n", phy_config->config_req.pbch_config.dmrs_type_a_position);
printf("pdcch config sib1: %d\n", phy_config->config_req.pbch_config.pdcch_config_sib1); printf("pdcch config sib1: %d\n", phy_config->config_req.pbch_config.pdcch_config_sib1);
printf("cell barred: %d\n", phy_config->config_req.pbch_config.cell_barred); printf("cell barred: %d\n", phy_config->config_req.pbch_config.cell_barred);
printf("intra frequcney reselection: %d\n", phy_config->config_req.pbch_config.intra_frequency_reselection); printf("intra frequcney reselection: %d\n", phy_config->config_req.pbch_config.intra_frequency_reselection);
printf("system frame number: %d\n", phy_config->config_req.pbch_config.system_frame_number); printf("system frame number: %d\n", phy_config->config_req.pbch_config.system_frame_number);
printf("ssb index: %d\n", phy_config->config_req.pbch_config.ssb_index); printf("ssb index: %d\n", phy_config->config_req.pbch_config.ssb_index);
printf("half frame bit: %d\n", phy_config->config_req.pbch_config.half_frame_bit); printf("half frame bit: %d\n", phy_config->config_req.pbch_config.half_frame_bit);
printf("-------------------------------\n"); printf("-------------------------------\n");
PHY_vars_UE_g[0][0]->proc.proc_rxtx[0].frame_rx = phy_config->config_req.pbch_config.system_frame_number; PHY_vars_UE_g[0][0]->proc.proc_rxtx[0].frame_rx = phy_config->config_req.pbch_config.system_frame_number;
} }
if(phy_config->config_req.config_mask & FAPI_NR_CONFIG_REQUEST_MASK_DL_BWP_COMMON){ if(phy_config->config_req.config_mask & FAPI_NR_CONFIG_REQUEST_MASK_DL_BWP_COMMON){
} }
if(phy_config->config_req.config_mask & FAPI_NR_CONFIG_REQUEST_MASK_UL_BWP_COMMON){ if(phy_config->config_req.config_mask & FAPI_NR_CONFIG_REQUEST_MASK_UL_BWP_COMMON){
} }
if(phy_config->config_req.config_mask & FAPI_NR_CONFIG_REQUEST_MASK_DL_BWP_DEDICATED){ if(phy_config->config_req.config_mask & FAPI_NR_CONFIG_REQUEST_MASK_DL_BWP_DEDICATED){
} }
if(phy_config->config_req.config_mask & FAPI_NR_CONFIG_REQUEST_MASK_UL_BWP_DEDICATED){ if(phy_config->config_req.config_mask & FAPI_NR_CONFIG_REQUEST_MASK_UL_BWP_DEDICATED){
} }
} }
return 0; return 0;
} }
...@@ -3432,6 +3432,9 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id,PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t * ...@@ -3432,6 +3432,9 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id,PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *
//emos_dump_UE.dci_cnt[nr_tti_rx] = dci_cnt; //emos_dump_UE.dci_cnt[nr_tti_rx] = dci_cnt;
#endif #endif
ue->dci_ind.number_of_dcis = dci_cnt;
ue->dl_indication.dci_ind = &ue->dci_ind; // hang on rx_ind instance
for (i=0; i<dci_cnt; i++) { for (i=0; i<dci_cnt; i++) {
/* /*
* This is the NR part * This is the NR part
...@@ -3485,7 +3488,17 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id,PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t * ...@@ -3485,7 +3488,17 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id,PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *
n_RB_DLBWP, n_RB_DLBWP,
crc_scrambled_values); crc_scrambled_values);
//ue->dci_ind.dci_list = (fapi_nr_dci_indication_pdu_t *)malloc(num_dci * sizeof(fapi_nr_dci_indication_pdu_t));
ue->dci_ind.dci_list[i].rnti = 0x0000;
ue->dci_ind.dci_list[i].dci_type = 0;
NR_DCI_INFO_EXTRACTED_t *nr_dci_info_extracted;
memcpy(&ue->dci_ind.dci_list[i].dci, nr_dci_info_extracted, sizeof(fapi_nr_dci_pdu_rel15_t) );
// TODO: check where should we send up this message.
//ue->if_inst->dl_indication(&ue->dl_indication);
/* /*
* This is the LTE part to be removed * This is the LTE part to be removed
......
...@@ -37,9 +37,9 @@ ...@@ -37,9 +37,9 @@
#include <stdlib.h> #include <stdlib.h>
#include <string.h> #include <string.h>
#define NR_BCCH_DL_SCH 3 // SI #define NR_BCCH_DL_SCH 3 // SI
#define NR_BCCH_BCH 5 // MIB #define NR_BCCH_BCH 5 // MIB
/*!\brief UE layer 2 status */ /*!\brief UE layer 2 status */
typedef enum { typedef enum {
...@@ -49,5 +49,32 @@ typedef enum { ...@@ -49,5 +49,32 @@ typedef enum {
PHY_HO_PRACH PHY_HO_PRACH
} NR_UE_L2_STATE_t; } NR_UE_L2_STATE_t;
typedef struct {
uint8_t LCID:6; // octet 1 [5:0]
uint8_t F:1; // octet 1 [6]
uint8_t R:1; // octet 1 [7]
uint8_t L:8; // octet 2 [7:0]
} __attribute__ ((__packed__)) NR_MAC_SUBHEADER_SHORT;
typedef struct {
uint8_t LCID:6; // octet 1 [5:0]
uint8_t F:1; // octet 1 [6]
uint8_t R:1; // octet 1 [7]
uint8_t L1:8; // octet 2 [7:0]
uint8_t L2:8; // octet 3 [7:0]
} __attribute__ ((__packed__)) NR_MAC_SUBHEADER_LONG;
typedef struct {
uint8_t LCID:5; // octet 1 [5:0]
uint8_t R:2; // octet 1 [7:6]
} __attribute__ ((__packed__)) NR_MAC_SUBHEADER_FIXED;
#define DL_SCH_LCID_CCCH 0x0
#define DL_SCH_LCID_R_BITRATE 0x2f
#define DL_SCH_LCID_L_DRX 0x3b
#define DL_SCH_LCID_DRX 0x3c
#define DL_SCH_LCID_TA 0x3d
#define DL_SCH_LCID_CONTENTION_RESOLUTION_ID 0x3e
#define DL_SCH_LCID_PADDING 0x3f
#endif /*__LAYER2_MAC_DEFS_H__ */ #endif /*__LAYER2_MAC_DEFS_H__ */
...@@ -81,6 +81,7 @@ typedef struct { ...@@ -81,6 +81,7 @@ typedef struct {
uint32_t type0_pdcch_ss_mux_pattern; uint32_t type0_pdcch_ss_mux_pattern;
SFN_C_TYPE type0_pdcch_ss_sfn_c; SFN_C_TYPE type0_pdcch_ss_sfn_c;
uint32_t type0_pdcch_ss_n_c; uint32_t type0_pdcch_ss_n_c;
uint32_t type0_pdcch_consecutive_slots;
/// Random access parameter /// Random access parameter
uint16_t ra_rnti; uint16_t ra_rnti;
......
...@@ -80,4 +80,4 @@ extern const float table_38213_13_12_c1[16]; ...@@ -80,4 +80,4 @@ extern const float table_38213_13_12_c1[16];
extern const int32_t table_38213_13_12_c2[16]; extern const int32_t table_38213_13_12_c2[16];
extern const float table_38213_13_12_c3[16]; extern const float table_38213_13_12_c3[16];
extern const int32_t table_38213_10_1_1_c2[3]; extern const int32_t table_38213_10_1_1_c2[5];
\ No newline at end of file \ No newline at end of file
...@@ -113,7 +113,7 @@ uint32_t ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, ...@@ -113,7 +113,7 @@ uint32_t ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP,
uint8_t eNB_id, rnti_t rnti, sub_frame_t subframe); uint8_t eNB_id, rnti_t rnti, sub_frame_t subframe);
int8_t nr_ue_decode_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_type); int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_type);
uint32_t get_ssb_frame(void); uint32_t get_ssb_frame(void);
uint32_t get_ssb_slot(uint32_t ssb_index); uint32_t get_ssb_slot(uint32_t ssb_index);
......
...@@ -88,4 +88,4 @@ const float table_38213_13_12_c1[16] = { 0, 0, 2.5f, 2.5f, 5, 5, 0, 2.5f, 5, 7 ...@@ -88,4 +88,4 @@ const float table_38213_13_12_c1[16] = { 0, 0, 2.5f, 2.5f, 5, 5, 0, 2.5f, 5, 7
const int32_t table_38213_13_12_c2[16] = { 1, 2, 1, 2, 1, 2, 2, 2, 2, 1, 2, 2, 1, 1, reserved, reserved}; // index 14-15 reserved const int32_t table_38213_13_12_c2[16] = { 1, 2, 1, 2, 1, 2, 2, 2, 2, 1, 2, 2, 1, 1, reserved, reserved}; // index 14-15 reserved
const float table_38213_13_12_c3[16] = { 1, 0.5f, 1, 0.5f, 1, 0.5f, 0.5f, 0.5f, 0.5f, 1, 0.5f, 0.5f, 1, 1, reserved, reserved}; // M, index 14-15 reserved const float table_38213_13_12_c3[16] = { 1, 0.5f, 1, 0.5f, 1, 0.5f, 0.5f, 0.5f, 0.5f, 1, 0.5f, 0.5f, 1, 1, reserved, reserved}; // M, index 14-15 reserved
const int32_t table_38213_10_1_1_c2[3] = { 4, 2, 1 }; const int32_t table_38213_10_1_1_c2[5] = { 0, 0, 4, 2, 1 };
\ No newline at end of file \ No newline at end of file
...@@ -401,9 +401,11 @@ const uint32_t num_slot_per_frame = 20; ...@@ -401,9 +401,11 @@ const uint32_t num_slot_per_frame = 20;
coreset_duration = num_symbols * number_of_search_space_per_slot; coreset_duration = num_symbols * number_of_search_space_per_slot;
mac->type0_pdcch_dci_config.number_of_candidates[2] = table_38213_10_1_1_c2[0]; // CCE aggregation level = 4 mac->type0_pdcch_dci_config.number_of_candidates[0] = table_38213_10_1_1_c2[0];
mac->type0_pdcch_dci_config.number_of_candidates[3] = table_38213_10_1_1_c2[1]; // CCE aggregation level = 8 mac->type0_pdcch_dci_config.number_of_candidates[1] = table_38213_10_1_1_c2[1];
mac->type0_pdcch_dci_config.number_of_candidates[4] = table_38213_10_1_1_c2[2]; // CCE aggregation level = 16 mac->type0_pdcch_dci_config.number_of_candidates[2] = table_38213_10_1_1_c2[2]; // CCE aggregation level = 4
mac->type0_pdcch_dci_config.number_of_candidates[3] = table_38213_10_1_1_c2[3]; // CCE aggregation level = 8
mac->type0_pdcch_dci_config.number_of_candidates[4] = table_38213_10_1_1_c2[4]; // CCE aggregation level = 16
mac->type0_pdcch_dci_config.duration = search_space_duration; mac->type0_pdcch_dci_config.duration = search_space_duration;
mac->type0_pdcch_dci_config.coreset.duration = coreset_duration; // coreset mac->type0_pdcch_dci_config.coreset.duration = coreset_duration; // coreset
mac->type0_pdcch_dci_config.monitoring_symbols_within_slot = (0x3fff << first_symbol_index) & (0x3fff >> (14-coreset_duration-first_symbol_index)) & 0x3fff; mac->type0_pdcch_dci_config.monitoring_symbols_within_slot = (0x3fff << first_symbol_index) & (0x3fff >> (14-coreset_duration-first_symbol_index)) & 0x3fff;
...@@ -462,9 +464,11 @@ NR_UE_L2_STATE_t nr_ue_scheduler( ...@@ -462,9 +464,11 @@ NR_UE_L2_STATE_t nr_ue_scheduler(
// 38.213 chapter 13 // 38.213 chapter 13
if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_0) && !(rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){ if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_0) && !(rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){
search_space_mask = search_space_mask | type0_pdcch; search_space_mask = search_space_mask | type0_pdcch;
mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.duration;
} }
if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_1) && (rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){ if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_1) && (rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){
search_space_mask = search_space_mask | type0_pdcch; search_space_mask = search_space_mask | type0_pdcch;
mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.duration;
} }
//if((mac->type0_pdcch_ss_sfn_c == SFN_C_EQ_SFN_SSB) && ( get_ssb_frame() )){ //if((mac->type0_pdcch_ss_sfn_c == SFN_C_EQ_SFN_SSB) && ( get_ssb_frame() )){
// search_space_mask = search_space_mask | type0_pdcch; // search_space_mask = search_space_mask | type0_pdcch;
...@@ -474,12 +478,14 @@ NR_UE_L2_STATE_t nr_ue_scheduler( ...@@ -474,12 +478,14 @@ NR_UE_L2_STATE_t nr_ue_scheduler(
// 38.213 Table 13-13, 13-14 // 38.213 Table 13-13, 13-14
if((rx_frame == get_ssb_frame()) && (rx_slot == mac->type0_pdcch_ss_n_c)){ if((rx_frame == get_ssb_frame()) && (rx_slot == mac->type0_pdcch_ss_n_c)){
search_space_mask = search_space_mask | type0_pdcch; search_space_mask = search_space_mask | type0_pdcch;
mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.duration;
} }
} }
if(mac->type0_pdcch_ss_mux_pattern == 3){ if(mac->type0_pdcch_ss_mux_pattern == 3){
// 38.213 Table 13-15 // 38.213 Table 13-15
if((rx_frame == get_ssb_frame()) && (rx_slot == mac->type0_pdcch_ss_n_c)){ if((rx_frame == get_ssb_frame()) && (rx_slot == mac->type0_pdcch_ss_n_c)){
search_space_mask = search_space_mask | type0_pdcch; search_space_mask = search_space_mask | type0_pdcch;
mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.duration;
} }
} }
} }
...@@ -498,13 +504,14 @@ NR_UE_L2_STATE_t nr_ue_scheduler( ...@@ -498,13 +504,14 @@ NR_UE_L2_STATE_t nr_ue_scheduler(
uint8_t format_2_3_number_of_candidates; uint8_t format_2_3_number_of_candidates;
#endif #endif
fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request; fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request;
if(search_space_mask & type0_pdcch){ if((search_space_mask & type0_pdcch) || ( mac->type0_pdcch_consecutive_slots != 0 )){
mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_consecutive_slots - 1;
dl_config->dl_config_request_body[dl_config->number_pdus].dci_pdu.dci_config_rel15 = mac->type0_pdcch_dci_config; dl_config->dl_config_list[dl_config->number_pdus].dci_pdu.dci_config_rel15 = mac->type0_pdcch_dci_config;
dl_config->dl_config_request_body[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI; dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI;
dl_config->number_pdus = dl_config->number_pdus + 1; dl_config->number_pdus = dl_config->number_pdus + 1;
dl_config->dl_config_request_body[dl_config->number_pdus].dci_pdu.dci_config_rel15.rnti = 0xaaaa; // to be set dl_config->dl_config_list[dl_config->number_pdus].dci_pdu.dci_config_rel15.rnti = 0xaaaa; // to be set
} }
if(search_space_mask & type0a_pdcch){ if(search_space_mask & type0a_pdcch){
...@@ -526,7 +533,7 @@ NR_UE_L2_STATE_t nr_ue_scheduler( ...@@ -526,7 +533,7 @@ NR_UE_L2_STATE_t nr_ue_scheduler(
return CONNECTION_OK; return CONNECTION_OK;
} }
int8_t nr_ue_decode_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_type){ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_type){
NR_UE_MAC_INST_t *mac = get_mac_inst(module_id); NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
...@@ -550,4 +557,56 @@ int8_t nr_ue_decode_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fap ...@@ -550,4 +557,56 @@ int8_t nr_ue_decode_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fap
int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe){ int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe){
return 0; return 0;
} }
\ No newline at end of file
void nr_ue_process_mac_pdu(
module_id_t module_idP,
uint8_t CC_id,
uint8_t *pduP,
uint16_t pdu_len,
uint8_t eNB_index){
uint8_t *pdu_ptr = pduP;
uint8_t sub_pdu_len;
// variable-size MAC CE(known by LCID), padding, MSG3, MAC SDU
// |0|1|2|3|4|5|6|7| bit-wise
// |R|F| LCID |
// | L |
// variable-size MAC CE(known by LCID), padding, MSG3, MAC SDU
// |0|1|2|3|4|5|6|7| bit-wise
// |R|F| LCID |
// | L |
// | L |
// fixed-size MAC CE(known by LCID), padding, MSG3
// |0|1|2|3|4|5|6|7| bit-wise
// |R|R| LCID |
// LCID: The Logical Channel ID field identifies the logical channel instance of the corresponding MAC SDU or the type of the corresponding MAC CE or padding as described in Tables 6.2.1-1 and 6.2.1-2 for the DL-SCH and UL-SCH respectively. There is one LCID field per MAC subheader. The LCID field size is 6 bits;
// L: The Length field indicates the length of the corresponding MAC SDU or variable-sized MAC CE in bytes. There is one L field per MAC subheader except for subheaders corresponding to fixed-sized MAC CEs and padding. The size of the L field is indicated by the F field;
// F: lenght of L is 8 or 16 bits wide
// R: Reserved bit, set to zero.
while (!done) {
switch(((NR_MAC_SUBHEADER_FIXED *)pdu_ptr)->LCID){
// Control element
case DL_SCH_LCID_PADDING:
done = 1;
// end of MAC PDU, there is nothing right after padding
break;
// MAC SDU
default:
printf("[MAC] get lcid: %d which not support yet\n", ((NR_MAC_SUBHEADER_FIXED *)buf_ptr)->LCID);
break;
}
pdu_ptr += sub_pdu_len;
}
}
...@@ -62,7 +62,7 @@ int8_t handle_bcch_dlsch(module_id_t module_id, int cc_id, uint8_t gNB_index, ui ...@@ -62,7 +62,7 @@ int8_t handle_bcch_dlsch(module_id_t module_id, int cc_id, uint8_t gNB_index, ui
// L2 Abstraction Layer // L2 Abstraction Layer
int8_t handle_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_type){ int8_t handle_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_type){
return nr_ue_decode_dci(module_id, cc_id, gNB_index, dci, rnti, dci_type); return nr_ue_process_dci(module_id, cc_id, gNB_index, dci, rnti, dci_type);
} }
...@@ -157,10 +157,10 @@ int8_t nr_ue_dl_indication(nr_downlink_indication_t *dl_info){ ...@@ -157,10 +157,10 @@ int8_t nr_ue_dl_indication(nr_downlink_indication_t *dl_info){
case FAPI_NR_DCI_TYPE_1_0: case FAPI_NR_DCI_TYPE_1_0:
dl_config->dl_config_request_body[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH; dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH;
// mapping into DL_CONFIG_REQ for DL-SCH // mapping into DL_CONFIG_REQ for DL-SCH
fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu = &dl_config->dl_config_request_body[dl_config->number_pdus].dlsch_pdu.dlsch_config_rel15; fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu = &dl_config->dl_config_list[dl_config->number_pdus].dlsch_pdu.dlsch_config_rel15;
dlsch_config_pdu->format_indicator = dci->dci_format; dlsch_config_pdu->format_indicator = dci->dci_format;
dlsch_config_pdu->frequency_domain_assignment = dci->frequency_domain_resouce_assignment; dlsch_config_pdu->frequency_domain_assignment = dci->frequency_domain_resouce_assignment;
dlsch_config_pdu->time_domain_assignment = dci->time_domain_resource_assignment; dlsch_config_pdu->time_domain_assignment = dci->time_domain_resource_assignment;
...@@ -174,7 +174,7 @@ int8_t nr_ue_dl_indication(nr_downlink_indication_t *dl_info){ ...@@ -174,7 +174,7 @@ int8_t nr_ue_dl_indication(nr_downlink_indication_t *dl_info){
dlsch_config_pdu->pucch_resource_indicator = dci->pucch_resource_indicator; dlsch_config_pdu->pucch_resource_indicator = dci->pucch_resource_indicator;
dlsch_config_pdu->pdsch_to_harq_feedback_timing_indicator = dci->pdsch_to_harq_feedback_timing_indicator; dlsch_config_pdu->pdsch_to_harq_feedback_timing_indicator = dci->pdsch_to_harq_feedback_timing_indicator;
dl_config->dl_config_request_body[dl_config->number_pdus].dlsch_pdu.dlsch_config_rel15.rnti = 0x0000; // TX RNTI: UE-spec dl_config->dl_config_list[dl_config->number_pdus].dlsch_pdu.dlsch_config_rel15.rnti = 0x0000; // TX RNTI: UE-spec
dl_config->number_pdus = dl_config->number_pdus + 1; dl_config->number_pdus = dl_config->number_pdus + 1;
ret_mask |= (handle_dci( ret_mask |= (handle_dci(
......
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