Commit 3ac9bd32 authored by Guy De Souza's avatar Guy De Souza

structures changes/ does not compile

parent 88b1b593
develop 1 128-ues 256_QAM_demod 375-syrtem-sdr-platform 408-reworked 408-ue-main-threads 445-LDPC-implementation-on-GPU 459-pusch-based-ta-updates 464-ru_beamforming_in_gpu 464-ru_beamforming_in_gpu-CPUsubfunction 472-add-pusch-dmrs-modes 481-ldpc-decoder-on-gpu 5g_fapi_scf LTE_TRX_on_single_port NCTU_CS_ISIP NCTU_CS_ISIP_CPU NCTU_CS_ISIP_GPU NCTU_OpinConnect_LDPC NR-PHY-MAC-IF-multi-UE NRUE_usedlschparallel NR_10MHz NR_CSI_reporting NR_DCI_01 NR_DLUL_PF NR_DLUL_PF_4UL NR_DLUL_PF_rebased NR_DL_MIMO NR_DL_sched_fixes NR_DL_scheduler NR_FAPI_beamindex_SSB_RO NR_FDD_FIX NR_FR2_RA NR_FR2_RRC_SSB NR_MAC_CE_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge NR_MAC_SSB_RO_GlobalEdge NR_MAC_SSB_RO_UE_IDCC NR_MAC_SSB_RO_merge NR_MAC_TCI_UCI_GlobalEdge NR_NGAP NR_PDCP_noS1 NR_PUCCH_MultiUE NR_RA_cleanup NR_RA_updates NR_RRCConfiguragion_FR2 NR_RRCConfiguration NR_RRCConfiguration_FR2 NR_RRCConfiguration_S1U NR_RRCConfiguration_merge_develop NR_RRCConfiguration_sync_source NR_RRCConfiguration_trx_thread NR_RRC_CP_bugfix NR_RRC_PDCP NR_RRC_PRACH_procedures NR_RRC_PRACH_procedures_todevelop NR_RRC_PUSCH NR_RRC_TA NR_RRC_X2AP_AMBR_Change_Global_edge NR_RRC_X2AP_RemoveHardcodings_GlobalEdge NR_RRC_config_simplified NR_RRC_harq NR_RRC_harq_b NR_RRC_harq_hacks NR_RRC_harq_newdcipdu NR_SA_F1AP_RFSIMULATOR NR_SA_F1AP_RFSIMULATOR2 NR_SA_F1AP_dev NR_SA_NGAP_RRC NR_SA_NGAP_RRC_wk42 NR_SA_itti_sim_wk48 NR_SA_itti_sim_wk48_hs NR_SA_itti_sim_wk48_hs1 NR_SCHED NR_SCHED_HARQ NR_SCHED_PDCCH_PUCCH_HARQ NR_SCHED_PDCCH_PUCCH_HARQ_rebased NR_SCHED_fixes NR_SRB_Config NR_TRX_on_single_port NR_TRX_on_single_port2 NR_UE_MAC_scheduler NR_UE_RA_fixes NR_UE_UL_DCI_improvements NR_UE_dlsch_bugfix NR_UE_enable_parallelization NR_UE_stability_fixes NR_UL_FAPI_programming NR_UL_scheduler NR_UL_scheduler_rebased NR_UL_scheduling NR_Wireshark NR_beam_simulation NR_beamforming_test NR_gNB_SCF_Indication NR_ipaccess_testing NR_mac_uci_functions_rework NR_msg2_phytest NR_scheduling_CSIRS NR_scheduling_request NR_scheduling_request2 NR_scheduling_request3 NR_test_S1U_RRC_PRACH_procedures NR_ue_dlsch_dmrs_cdm OpInConnect_ISIP PUSCH_TA_update RA_CI_test UE_DL_DCI_hotfix addoptions_nr_USRPdevice bch-fixes-bitmap benetel_5g_prach_fix benetel_driver_uldl_pf_merge benetel_driver_update benetel_phase_rotation benetel_phase_rotation_old bugfix-minor-remove-wrong-log bugfix-nr-bands bugfix-nr-ldpc-post-processing bugfix-nr-ldpc-size-typo bugfix-nr-pdcp-sn-size bugfix-nr-rate-matching-assertion bugfix-x2-SgNBAdditionRequest bupt-sa-merge cce_indexing_fix cce_indexing_fix2 ci-deploy-asterix ci-deploy-docker-compose ci-rd-july-improvements ci-test ci-ul-iperf-from-trf-container clean-5G-scope-round2 cleanup_softmodem_main constant_power debug_branch_init_sync develop-SA-RA develop-SnT develop-ci develop-nr develop-nr-adding-2018-09-asn1 develop-nr-fr2 develop-nr-fr2-rework develop-nr_cppcheck develop-oriecpriupdates develop-sib1 develop-sib1-local develop-sib1-lts develop-sib1-update develop-sib1-update-test1 develop-sib1-update-ue develop_inria_ci_deployment develop_inria_ci_deployment_gp develop_integration_2020_w15 develop_integration_2020_w19 develop_integration_w08 develop_stable dfts_alternatives dlsch-all-dlslots dlsch_encode_mthread dlsch_parallel docupdate_tools dongzhanyi-zte-develop dongzhanyi-zte-develop2 dreibh/apt-auth-fix dreibh/device-load-fix dreibh/device-load-fix-develop-branch dual-connectivity edrx extend_sharedlibusage extend_sharedlibusage2 fapi_for_dmrs_and_ptrs feat-mac-sock feature-4g-sched feature-nr-4g-nfapi-modifications feature-support-clang-format feature/make-s1-mme-port-configurable feature/make-s1-mme-port-configurable-with-astyle-fixes fembms-enb-ue finalize-oaicn-integration firas fix-ci-tun fix-clock-source fix-itti-segv fix-l2-sim fix-limeSDR-compile fix-softmodem-restart fix-warnings fix_NR_DLUL_PF fix_do_ra_data fix_pdsch_low_prb fix_rfsim_mimo fix_rrc_x2_ticking fixes-CE-RLC-PDU-size fixes-mac-sched-nfapi fixes-mac-sched-tun fixes-tun flexran-apps flexran-improvements flexran-repair-mme-mgmt fr2-hw-test fujitsu_lte_contribution fujitsu_lte_contribution-128 gNB-nrUE-USRP generate_push_ptrs gnb-only-test harq-hotfix hotfix-minor-remove-nr-rlc-cppcheck-error hotfix-nr-rlc-tick hotfix-ocp-executable hotfix-ue-musim-compilation hotfix_usrp_lib improve_build_nr_lte_merge improve_nr_modulation improve_ue_stability integration-develop-nr-2019w45 integration_2020_wk40 integration_2020_wk41 integration_2020_wk42_2 integration_2020_wk45 integration_2020_wk45_2 integration_2020_wk46 integration_2020_wk46_2 integration_2020_wk47 integration_2020_wk48 integration_2020_wk48_2 integration_2020_wk49 integration_2020_wk50 integration_2020_wk50_1 integration_2020_wk51 integration_2020_wk51_2 integration_2021_wk02 integration_2021_wk02_wMR988 integration_2021_wk04 integration_2021_wk05 inter-RRU-final inter-RRU-nr inter-RRU-oairu inter-rru-UE interoperability-test isip_nr itti-enhancement l2-fixes ldpc-dec-layering ldpc-decoder-codegen ldpc-decoder-codegen2 ldpc-decoder-improvements ldpc-offload ldpc_short_codeword_fixes load_gnb lte-ulsch-bugfix lte_uplink_improvement mac-fixes-wk45_2 mbms-fix-develop-nr merging-2019-w51-to-develop-nr minor-fix-doc-basic-sim mosaic5g-oai-ran mosaic5g-oai-sim nasmesh_kernel_5.8 new-gtpu new_rlc_2020 nfapi-bugfix nfapi_nr_develop ngap-dlul ngap-support ngap-w48-merge2 ngap-wf ngap-wf-1120 ngap-wf-1120-srb ngap-wf-1120-srb-gtp ngap-wf-1120-srb-gtp-hs ngap-wf-1120-srb-gtp-hs1 ngap-wf-1120-srb-gtp-hs2 ngap-wf-1120-srb-gtp-yhz ngap-wf-1203-yunsdr ngap-wf-liuyu ngap_lfq_1120 ngap_merge noCore nr-coreset-bug-fix nr-dlsch-multi-thread nr-dlsch-thread nr-dual-connectivity nr-interdigital-test nr-ip-uplink-noS1 nr-mac-pdu-wireshark nr-mac-remove-ue-list nr-multiple-ssb nr-pdcp nr-pdsch-extraction-bugfix nr-physim-update nr-rlc-am-bugfix-w44 nr-rlc-bugfix-w44 nr-ssb-measurements nr-timing-measurement nr-timing-measurement-merge nr-ue-buffer-status nr-ue-slot-based nr-uldci nrUE nrUE-hs nrUE-upper-layer nr_beamforming nr_bsr nr_ci_dlsim nr_csi_newbranch nr_dci_procedures nr_demo_wsa2019 nr_dl_dmrs_type2 nr_dl_pf nr_dl_pf2 nr_dl_ul_ptrs nr_dlsch_parallel_measurements nr_dlsim_plot nr_fapi_for_push_tmp nr_fdd_if_fix nr_fix_easycppcheck nr_flexible_NRBDL nr_improve_build_procedures nr_increase_tp nr_mib_vsa_test nr_pdcch_testing nr_pdcch_updates nr_pdsch_integration nr_polar_decoder_improvement nr_prach nr_prach_fr2 nr_pucch nr_pucch2 nr_segmentation_fixes nr_sim_fix nr_tdd_configuration nr_ue_msg3 nr_ue_tti_cleanup nr_ul_pf nr_ul_scfdma nr_vcd nrue-multi-thread nrue_msg2_reception nsa-ue nsa_remove_band_hardcodings oai-sim oai-ubuntu-docker oai-ubuntu-docker-for-lmssdr oairu oairu-dockerfile-support oc-docker-october-improvements openxg/develop pdcp-benchmark pdsch-ch-est polar8 ptrs_rrc_config pusch-mthread-scaling-fix pusch-retrans-fix-ue ra-dl-ul reduce_memory_footprint remove-ci-workaround remove_nos1_hack_pdcp remove_x2_gnb_hardcoding repair-TA revert-f5c94279 revert_memcpy rh-ci-add-ue-parallelization rh_ci_fix_autoterminate rh_ci_fr1_update rh_ci_oc rh_ci_py rh_ci_ra_fr2 rh_ci_rfsim_ra rh_ci_ue_parallel rh_doc_update_3 rh_fr1_newjenkins rh_fr1_update rh_gnb_compile_fix rh_wk50_debug rlc-v2-bugfix-status-reporting rlc-v2-tick rlc_v2_coverity_fixes rrc-enb-phy-testmode ru-parallel-beamforming runel runel-reverse-test s1-subnormal_rewrite s1_subnormal s1_subnormal-robert s1ap-bugfix-rab_setup sa-demo sa-merge-rrc-srb sa-msg4 sa-msg4-rrc sa-msg4-rrc-yihz sa-msg4-rrc-yihz-hs sa_rrc_yihz small-bugfixes-w40 small-config-change smallcleanup softmodem_cleanup split73 test-x310-perf testing_2symb_pdcch testing_with_external_txdata thread-pool tools_5Gadapt tp-ota-test trx_thread_param trx_write_thread ue-csi ue-fixes ue-fixes-ota ue-updates-runel-test ue_adjust_gain ue_beam_selection ue_dlsch-multi-threading ue_dlsch_decoding_ldpc_offload ue_nfapi_mch uhd_priority_set_cleanup ul-freq-iq-samps-to-file ul_dl_dci_same_slot ul_harq ulsch_decode_mthread ulsim_changes update-to-2019-march-june-release usrp_fix_adc_shift_and_pps_sync usrp_gpio_test wireshark-T-hack-ueid wireshark-log-scheduling-requests x2-endc-processing xiangwab xiangwan yihongzheng_srb zzs 2021.w04 2021.w02 2020.w51_2 2020.w51 2020.w50 2020.w49 2020.w48_2 2020.w48 2020.w47 2020.w46_2 2020.w46 2020.w45_2 2020.w45 2020.w44 2020.w42_2 2020.w42 2020.w41 2020.w39 2020.w38 2020.w37 2020.w36 2020.w34 2020.w33 2020.w31 2020.w30 2020.w29 2020.w28 2020.w26 2020.w25 2020.w24 2020.w23 2020.w22 2020.w19 2020.w17 2020.w16 2020.w15 2020.w11 2020.w09 2020.w06 2020.w05 2020.w04 2020.w03 osa-etsi-ws-ue osa-etsi-ws-try2 osa-etsi-ws-try1 osa-etsi-ws-gNB nr-ip-over-lte nr-ip-over-lte-v.1.5 nr-ip-over-lte-v.1.4 nr-ip-over-lte-v.1.3 nr-ip-over-lte-v.1.2 nr-ip-over-lte-v.1.1 nr-ip-over-lte-v.1.0 develop-nr-pdcch develop-nr-2020w03 develop-nr-2020w02 develop-nr-2019w51 develop-nr-2019w50 develop-nr-2019w48 develop-nr-2019w47 develop-nr-2019w45 develop-nr-2019w43 develop-nr-2019w42 develop-nr-2019w40 develop-nr-2019w28 develop-nr-2019w23 benetel_phase_rotation
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......@@ -1169,7 +1169,6 @@ int oai_nfapi_nr_dl_config_req(nfapi_nr_dl_config_request_t *dl_config_req)
int retval = nfapi_vnf_p7_dl_config_req(p7_config, dl_config_req);
dl_config_req->dl_config_request_body.number_pdcch_ofdm_symbols = 1;
dl_config_req->dl_config_request_body.number_dci = 0;
dl_config_req->dl_config_request_body.number_pdu = 0;
dl_config_req->dl_config_request_body.number_pdsch_rnti = 0;
......
......@@ -6,6 +6,17 @@
#define NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS 5
// Extension to the generic structures for single tlv values
typedef struct {
nfapi_tl_t tl;
int32_t value;
} nfapi_int32_tlv_t;
typedef struct {
nfapi_tl_t tl;
uint32_t value;
} nfapi_uint32_tlv_t;
// nFAPI enums
typedef enum {
NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE = 0,
......@@ -203,7 +214,7 @@ typedef struct {
typedef struct {
nfapi_p4_p5_message_header_t header;
uint8_t num_tlv;
uint8_t num_tlv;
nfapi_nr_subframe_config_t subframe_config;
nfapi_nr_rf_config_t rf_config;
nfapi_nr_sch_config_t sch_config;
......@@ -220,21 +231,18 @@ typedef struct {
} nfapi_nr_config_request_t;
typedef enum {
NFAPI_NR_DL_DCI_FORMAT_1_0 = 0,
NFAPI_NR_DL_DCI_FORMAT_1_0=0,
NFAPI_NR_DL_DCI_FORMAT_1_1,
NFAPI_NR_DL_DCI_FORMAT_2_0,
NFAPI_NR_DL_DCI_FORMAT_2_1,
NFAPI_NR_DL_DCI_FORMAT_2_2,
NFAPI_NR_DL_DCI_FORMAT_2_3
} nfapi_nr_dl_dci_format_e;
typedef enum {
NFAPI_NR_UL_DCI_FORMAT_0_0 = 0,
NFAPI_NR_UL_DCI_FORMAT_1_0,
} nfapi_nr_ul_dci_format_e;
NFAPI_NR_DL_DCI_FORMAT_2_3,
NFAPI_NR_UL_DCI_FORMAT_0_0,
NFAPI_NR_UL_DCI_FORMAT_1_0
} nfapi_nr_dci_format_e;
typedef enum {
NFAPI_NR_RNTI_new = 0,
NFAPI_NR_RNTI_new=0,
NFAPI_NR_RNTI_C,
NFAPI_NR_RNTI_RA,
NFAPI_NR_RNTI_P,
......@@ -247,7 +255,17 @@ typedef enum {
NFAPI_NR_RNTI_TPC_PUSCH,
NFAPI_NR_RNTI_TPC_PUCCH,
NFAPI_NR_RNTI_TPC_SRS
} nfapi_nr_rnti_type_e ;
} nfapi_nr_rnti_type_e;
typedef enum {
NFAPI_NR_USS_FORMAT_0_0_AND_1_0,
NFAPI_NR_USS_FORMAT_0_1_AND_1_1,
} nfapi_nr_uss_dci_formats_e;
typedef enum {
NFAPI_NR_SEARCH_SPACE_TYPE_COMMON=0,
NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC
} nfapi_nr_search_space_type_e;
// P7 Sub Structures
//formats 0_0 and 0_1
......@@ -348,35 +366,52 @@ uint8_t *block_numbers;
typedef struct{
nfapi_uint16_tlv_t coreset_id; ///// L1 parameter 'CORESET-ID'
nfapi_uint16_tlv_t frequency_domain_resources; ///// L1 parameter 'CORESET-freq-dom'
nfapi_uint16_tlv_t duration; ///// L1 parameter 'CORESET-time-duration'
nfapi_uint16_tlv_t cce_reg_mapping_ype; ///// L1 parameter 'CORESET-CCE-REG-mapping-type'
nfapi_uint16_tlv_t reg_bundle_size; ///// L1 parameter 'CORESET-REG-bundle-size'
nfapi_uint16_tlv_t interleaver_size; ///// L1 parameter 'CORESET-interleaver-size'
nfapi_uint16_tlv_t shift_index; ///// L1 parameter 'CORESET-shift-index'
nfapi_uint16_tlv_t precoder_granularity; ///// L1 parameter 'CORESET-precoder-granuality'
nfapi_uint16_tlv_t tci_state_id; ///// L1 parameter 'TCI-StatesPDCCH'
nfapi_uint16_tlv_t tci_present_in_dci; ///// L1 parameter 'TCI-PresentInDCI'
nfapi_uint16_tlv_t pdcch_dmrs_scrambling_id; ///// L1 parameter 'PDCCH-DMRS-Scrambling-ID'
nfapi_uint16_tlv_t coreset_id;
nfapi_uint16_tlv_t frequency_domain_resources;
nfapi_uint16_tlv_t duration;
nfapi_uint16_tlv_t cce_reg_mapping_type;
nfapi_uint16_tlv_t reg_bundle_size;
nfapi_uint16_tlv_t interleaver_size;
nfapi_uint16_tlv_t shift_index;
nfapi_uint16_tlv_t precoder_granularity;
nfapi_uint16_tlv_t tci_state_id;
nfapi_uint16_tlv_t tci_present_in_dci;
nfapi_uint16_tlv_t pdcch_dmrs_scrambling_id;
} nfapi_nr_coreset_t;
typedef struct{
nfapi_uint16_tlv_t search_space_id;
nfapi_uint16_tlv_t coreset_id;
nfapi_uint16_tlv_t monitoring_slot_periodicity_and_offset; ///// L1 parameters 'Montoring-periodicity-PDCCH-slot'
nfapi_uint16_tlv_t monitoring_symbols_within_slot; ///// L1 parameter 'Montoring-symbols-PDCCH-within-slot'
nfapi_uint16_tlv_t number_of_candidates[NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS]; ///// L1 parameter 'Aggregation-level-1/2/4/8/16'
nfapi_uint16_tlv_t Com_dci_Format2_0_nrofCand_SFI_And_aggLevel; ///// L1 parameters 'SFI-Num-PDCCH-cand' and 'SFI-Aggregation-Level'
nfapi_uint16_tlv_t Com_dci_Format2_3_monitoringPeriodicity; ///// L1 parameter 'SRS-monitoring-periodicity'
nfapi_uint16_tlv_t Com_dci_Format2_3_nrofPDCCH_Candidates; ///// L1 parameter 'SRS-Num-PDCCH-cand'
nfapi_uint16_tlv_t ue_Specific_dci_Formats;
nfapi_uint8_tlv_t search_space_id;
nfapi_uint8_tlv_t coreset_id;
nfapi_uint8_tlv_t search_space_type;
nfapi_uint8_tlv_t duration;
nfapi_uint8_tlv_t css_formats_0_0_and_1_0;
nfapi_uint8_tlv_t css_format_2_0;
nfapi_uint8_tlv_t css_format_2_1;
nfapi_uint8_tlv_t css_format_2_2;
nfapi_uint8_tlv_t css_format_2_3;
nfapi_uint8_tlv_t uss_dci_formats;
nfapi_uint8_tlv_t srs_monitoring_periodicity;
nfapi_uint8_tlv_t slot_monitoring_periodicity;
nfapi_uint8_tlv_t slot_monitoring_offset;
nfapi_uint16_tlv_t monitoring_symbols_in_slot;
nfapi_uint16_tlv_t number_of_candidates[NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS];
} nfapi_nr_search_space_t;
typedef struct {
nfapi_tl_t tl;
nfapi_nr_coreset_t coreset;
nfapi_nr_search_space_t search_space;
uint8_t n_rb;
uint8_t n_symb;
uint8_t rb_offset;
uint8_t cr_mapping_type;
uint8_t mux_pattern;
uint8_t precoder_granularity;
uint8_t config_type;
uint8_t first_slot;
uint8_t first_symbol;
uint8_t nb_ss_sets_per_slot;
uint8_t sfn_mod2;
uint8_t search_space_type;
nfapi_bf_vector_t bf_vector;
} nfapi_nr_dl_config_pdcch_parameters_rel15_t;
typedef struct {
......@@ -384,7 +419,7 @@ typedef struct {
uint16_t length;
uint16_t pdu_index;
uint16_t transmission_power;
}nfapi_nr_dl_config_bch_pdu_rel15_t;
} nfapi_nr_dl_config_bch_pdu_rel15_t;
#define NFAPI_NR_DL_CONFIG_REQUEST_BCH_PDU_REL15_TAG 0x5025
......@@ -437,9 +472,8 @@ typedef struct {
typedef struct {
nfapi_tl_t tl;
uint8_t number_pdcch_ofdm_symbols;
uint8_t number_dci;
uint16_t number_pdu;
uint8_t number_pdu;
uint8_t number_pdsch_rnti;
nfapi_nr_dl_config_request_pdu_t *dl_config_pdu_list;
} nfapi_nr_dl_config_request_body_t;
......
......@@ -169,7 +169,18 @@ uint8_t nr_generate_dci_top(NR_gNB_DCI_ALLOC_t dci_alloc,
int k,l,k_prime,dci_idx, dmrs_idx;
nr_cce_t cce;
uint8_t n_rb = pdcch_vars.coreset_params.n_rb;
uint8_t rb_offset = pdcch_vars.coreset_params.n_symb;
uint8_t n_symb = pdcch_vars.coreset_params.rb_offset;
uint8_t first_slot = pdcch_vars.first_slot;
uint8_t first_symb = pdcch_vars.ss_params.first_symbol_idx;
/// DMRS QPSK modulation
/*There is a need to shift from which index the pregenerated DMRS sequence is used
* see 38211 r15.2.0 section 7.4.1.3.2: assumption is the reference point for k refers to the DMRS sequence*/
if (pdcch_vars.coreset_params.config_type == nr_cset_config_pdcch_config)
gold_pdcch_dmrs += ((int)floor(frame_parms.ssb_start_subcarrier/NR_NB_SC_PER_RB)+rb_offset)*3/32;
for (int i=0; i<NR_MAX_PDCCH_DMRS_LENGTH>>1; i++) {
idx = ((((gold_pdcch_dmrs[(i<<1)>>5])>>((i<<1)&0x1f))&1)<<1) ^ (((gold_pdcch_dmrs[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1);
mod_dmrs[i<<1] = nr_mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1];
......@@ -197,17 +208,14 @@ uint8_t nr_generate_dci_top(NR_gNB_DCI_ALLOC_t dci_alloc,
/// Resource mapping
a = (config.rf_config.tx_antenna_ports.value == 1) ? amp : (amp*ONE_OVER_SQRT2_Q15)>>15;
uint8_t n_rb = pdcch_vars.coreset_params.n_rb;
uint8_t rb_offset = pdcch_vars.coreset_params.n_symb;
uint8_t n_symb = pdcch_vars.coreset_params.rb_offset;
uint8_t first_slot = pdcch_vars.first_slot;
uint8_t first_symb = pdcch_vars.ss_params.first_symbol_idx;
/*The coreset is initialised
* in frequency: the first subcarrier is obtained by adding the first CRB overlapping the SSB and the rb_offset
* in time: by its first slot and its first symbol*/
uint8_t cset_start_sc = frame_parms.first_carrier_offset + ((int)floor(frame_parms.ssb_start_subcarrier/NR_NB_SC_PER_RB)+rb_offset)*NR_NB_SC_PER_RB;
uint8_t cset_start_symb = first_slot*frame_parms.symbols_per_slot + first_symb;
dci_idx = 0;
dmrs_idx = 0;
for (int aa = 0; aa < config.rf_config.tx_antenna_ports.value; aa++)
{
......@@ -216,16 +224,10 @@ uint8_t nr_generate_dci_top(NR_gNB_DCI_ALLOC_t dci_alloc,
if (pdcch_vars.coreset_params.precoder_granularity == nr_cset_same_as_reg_bundle) {
dci_idx = 0;
dmrs_idx = 0;
for (int cce_idx=0; cce_idx<dci_alloc.L; cce_idx++){
cce = pdcch_vars.cce_list[cce_idx];
for (int reg_idx=0; reg_idx<NR_NB_REG_PER_CCE; reg_idx++) {
if (pdcch_vars.coreset_params.config_type == nr_cset_config_mib_sib1)
k = cset_start_sc + cce.reg_list[reg_idx].start_sc_idx;
else
k = frame_parms.first_carrier_offset; // Not clear, to review
k = cset_start_sc + cce.reg_list[reg_idx].start_sc_idx;
l = cset_start_symb + cce.reg_list[reg_idx].symb_idx;
k_prime = 0;
for (int m=0; m<NR_NB_SC_PER_RB; m++) {
......
......@@ -45,43 +45,11 @@ typedef enum {
nr_rnti_type_P_RNTI
} nr_rnti_type_e;
// PDCCH search space types css: common, uss: ue specific
typedef enum {
nr_pdcch_css_type_0=0,
nr_pdcch_css_type_0_A,
nr_pdcch_css_type_1,
nr_pdcch_css_type_2,
nr_pdcch_css_type_3,
nr_pdcch_uss_type
} nr_pdcch_ss_type_e;
typedef enum {
nr_ssb_and_cset_mux_pattern_type_1=0,
nr_ssb_and_cset_mux_pattern_type_2,
nr_ssb_and_cset_mux_pattern_type_3
} nr_ssb_and_cset_mux_pattern_type_e;
typedef enum {
nr_cce_reg_mapping_interleaved=0,
nr_cce_reg_mapping_non_interleaved
} nr_cce_reg_mapping_type_e;
typedef enum {
nr_cset_config_mib_sib1=0,
nr_cset_config_pdcch_config
} nr_coreset_config_type_e;
typedef enum {
nr_cset_same_as_reg_bundle=0,
nr_cset_all_contiguous_rbs
} nr_coreset_precoder_granularity_type_e;
typedef struct {
uint8_t param_O;
uint8_t param_M;
uint8_t nb_ss_sets_per_slot;
uint8_t first_symbol_idx;
nr_pdcch_ss_type_e ss_type;
} nr_pdcch_ss_params_t;
typedef struct {
......@@ -115,21 +83,6 @@ typedef struct {
nr_pdcch_coreset_params_t coreset_params;
} nr_pdcch_vars_t;
typedef struct {
/// Length of DCI in bits
uint8_t size;
/// Aggregation level
uint8_t L;
/// rnti type
nr_rnti_type_e rnti;
/// Format
nr_dci_format_e format;
/// type
nr_pdcch_ss_type_e ss_type;
/// DCI pdu
uint32_t dci_pdu[4];
} NR_gNB_DCI_ALLOC_t;
typedef unsigned __int128 uint128_t;
uint8_t nr_get_dci_size(nr_dci_format_e format,
......
......@@ -45,6 +45,24 @@ typedef struct {
uint8_t pbch_e[NR_POLAR_PBCH_E];
} NR_gNB_PBCH;
typedef struct {
/// Length of DCI in bits
uint8_t size;
/// Aggregation level
uint8_t L;
/// rnti type
nfapi_nr_rnti_type_e rnti;
/// Format
nfapi_nr_dci_format_e format;
/// DCI pdu
uint32_t dci_pdu[4];
} NR_gNB_DCI_ALLOC_t;
typedef struct {
uint8_t num_dci;
NR_gNB_DCI_ALLOC_t dci_alloc[32];
} NR_gNB_PDCCH;
typedef struct {
/// \brief Pointers (dynamic) to the received data in the time domain.
/// - first index: rx antenna [0..nb_antennas_rx[
......@@ -265,7 +283,7 @@ typedef struct PHY_VARS_gNB_s {
nfapi_preamble_pdu_t preamble_list[MAX_NUM_RX_PRACH_PREAMBLES];
Sched_Rsp_t Sched_INFO;
LTE_eNB_PDCCH pdcch_vars[2];
NR_gNB_PDCCH pdcch_vars[2];
LTE_eNB_PHICH phich_vars[2];
NR_gNB_COMMON common_vars;
......
......@@ -42,6 +42,8 @@
#define MAX_NUM_SUBCARRIER_SPACING 5
#define NR_MAX_NB_RB 275
#define NR_NB_SC_PER_RB 12
#define NR_NB_REG_PER_CCE 6
......@@ -58,10 +60,10 @@
#define NR_SSS_LENGTH 127
#define NR_PBCH_DMRS_LENGTH 144 // in mod symbols
#define NR_PBCH_DMRS_LENGTH_DWORD 10 // roundup(2(QPSK)*NR_PBCH_DMRS_LENGTH/32)
#define NR_PBCH_DMRS_LENGTH_DWORD 10 // ceil(2(QPSK)*NR_PBCH_DMRS_LENGTH/32)
#define NR_MAX_PDCCH_DMRS_LENGTH 100
#define NR_MAX_PDCCH_DMRS_LENGTH_DWORD 5
#define NR_MAX_PDCCH_DMRS_LENGTH ((NR_MAX_NB_RB<<1)*3) // 3 symbols *2(QPSK)
#define NR_MAX_PDCCH_DMRS_LENGTH_DWORD 52 // ceil(NR_MAX_PDCCH_DMRS_LENGTH/32)
#define NR_MAX_DCI_PAYLOAD_SIZE 64
#define NR_MAX_DCI_SIZE 200 //random values
......@@ -110,6 +112,27 @@ typedef struct NR_BWP_PARMS {
uint16_t ofdm_symbol_size;
} NR_BWP_PARMS;
typedef enum {
nr_ssb_and_cset_mux_pattern_type_1=0,
nr_ssb_and_cset_mux_pattern_type_2,
nr_ssb_and_cset_mux_pattern_type_3
} nr_ssb_and_cset_mux_pattern_type_e;
typedef enum {
nr_cce_reg_mapping_interleaved=0,
nr_cce_reg_mapping_non_interleaved
} nr_cce_reg_mapping_type_e;
typedef enum {
nr_cset_config_mib_sib1=0,
nr_cset_config_pdcch_config
} nr_coreset_config_type_e;
typedef enum {
nr_cset_same_as_reg_bundle=0,
nr_cset_all_contiguous_rbs
} nr_coreset_precoder_granularity_type_e;
typedef struct NR_DL_FRAME_PARMS {
/// frequency range
nr_frequency_range_e freq_range;
......
......@@ -53,6 +53,25 @@ void handle_nr_nfapi_bch_pdu(PHY_VARS_gNB *gNB,
// adjust transmit amplitude here based on NFAPI info
}
void handle_nfapi_nr_dci_dl_pdu(PHY_VARS_gNB *gNB,
int frame, int subframe,
gNB_rxtx_proc_t *proc,
nfapi_nr_dl_config_request_pdu_t *dl_config_pdu)
{
int idx = subframe&1;
NR_gNB_PDCCH *pdcch_vars = &gNB->pdcch_vars[idx];
nfapi_nr_dl_config_dci_dl_pdu *pdu = &dl_config_pdu->dci_dl_pdu;
LOG_D(PHY,"Frame %d, Subframe %d: DCI processing - populating pdcch_vars->dci_alloc[%d] proc:subframe_tx:%d idx:%d pdcch_vars->num_dci:%d\n",frame,subframe, pdcch_vars->num_dci, proc->subframe_tx, idx, pdcch_vars->num_dci);
// copy dci configuration into gNB structure
nr_fill_dci_and_dlsch(eNB,frame,subframe,proc,&pdcch_vars->dci_alloc[pdcch_vars->num_dci],pdu);
LOG_D(PHY,"Frame %d, Subframe %d: DCI processing - populated pdcch_vars->dci_alloc[%d] proc:subframe_tx:%d idx:%d pdcch_vars->num_dci:%d\n",proc->frame_tx,proc->subframe_tx, pdcch_vars->num_dci, proc->subframe_tx, idx, pdcch_vars->num_dci);
}
void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){
PHY_VARS_gNB *gNB;
gNB_rxtx_proc_t *proc;
......
......@@ -81,7 +81,6 @@ void clear_nr_nfapi_information(gNB_MAC_INST * gNB,
if (nfapi_mode==0 || nfapi_mode == 1) { // monolithic or PNF
DL_req[CC_idP].dl_config_request_body.number_pdcch_ofdm_symbols = 1;
DL_req[CC_idP].dl_config_request_body.number_dci = 0;
DL_req[CC_idP].dl_config_request_body.number_pdu = 0;
DL_req[CC_idP].dl_config_request_body.number_pdsch_rnti = 0;
......@@ -456,4 +455,4 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
*/
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_OUT);
}
\ No newline at end of file
}
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