Commit 72f12514 authored by Parminder Singh's avatar Parminder Singh

Enabled 4UL per frame using 4 DL DCI

- Enabled slot 1 and 2 for DLSCH
- Enabled slot 6,7,8,9,16,17,18,19 fir ULSCH
parent ff17a743
...@@ -653,7 +653,7 @@ void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) ...@@ -653,7 +653,7 @@ void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx)
for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) { for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) {
no_sig = nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid); no_sig = nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid);
if (no_sig) { if (no_sig) {
LOG_I(PHY, "PUSCH not detected in symbol %d\n",symbol); LOG_I(PHY, "PUSCH not detected for %4d.%2d in symbol %d\n",frame_rx,slot_rx,symbol);
nr_fill_indication(gNB,frame_rx, slot_rx, ULSCH_id, harq_pid, 1); nr_fill_indication(gNB,frame_rx, slot_rx, ULSCH_id, harq_pid, 1);
return; return;
} }
......
...@@ -368,9 +368,10 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, ...@@ -368,9 +368,10 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
} }
#define BIT(x) (1 << (x)) #define BIT(x) (1 << (x))
const uint64_t dlsch_in_slot_bitmap = BIT( 1) | BIT( 2) | BIT( 3) | BIT( 4) | BIT( 5) | BIT( 6) const uint64_t dlsch_in_slot_bitmap = BIT( 0) |BIT( 1) | BIT( 2) | BIT( 3) | BIT( 4)
| BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16); | BIT(10) |BIT(11) | BIT(12) | BIT(13) | BIT(14);
const uint64_t ulsch_in_slot_bitmap = BIT( 8) | BIT(18); const uint64_t ulsch_in_slot_bitmap = BIT( 6) | BIT( 7) | BIT( 8) | BIT( 9)
| BIT(16) | BIT(17) | BIT(18) | BIT(19);
memset(RC.nrmac[module_idP]->cce_list[bwp_id][0],0,MAX_NUM_CCE*sizeof(int)); // coreset0 memset(RC.nrmac[module_idP]->cce_list[bwp_id][0],0,MAX_NUM_CCE*sizeof(int)); // coreset0
memset(RC.nrmac[module_idP]->cce_list[bwp_id][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid 1 memset(RC.nrmac[module_idP]->cce_list[bwp_id][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid 1
......
...@@ -257,7 +257,7 @@ void nr_preprocessor_phytest(module_id_t module_id, ...@@ -257,7 +257,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
frame_t frame, frame_t frame,
sub_frame_t slot) sub_frame_t slot)
{ {
if (slot != 1 && slot != 3) if (slot != 1 && slot != 2 )
return; return;
NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info; NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
const int UE_id = 0; const int UE_id = 0;
...@@ -406,12 +406,13 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, ...@@ -406,12 +406,13 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id,
/* check if slot is UL, and that slot is 8 (assuming K2=6 because of UE /* check if slot is UL, and that slot is 8 (assuming K2=6 because of UE
* limitations). Note that if K2 or the TDD configuration is changed, below * limitations). Note that if K2 or the TDD configuration is changed, below
* conditions might exclude each other and never be true */ * conditions might exclude each other and never be true */
if (!(is_xlsch_in_slot(ulsch_in_slot_bitmap, sched_slot) && sched_slot == 8))
if (!(is_xlsch_in_slot(ulsch_in_slot_bitmap, sched_slot)))
return false; return false;
const int bw = NRRIV2BW(sched_ctrl->active_ubwp->bwp_Common->genericParameters.locationAndBandwidth, 275); const int bw = NRRIV2BW(sched_ctrl->active_ubwp->bwp_Common->genericParameters.locationAndBandwidth, 275);
uint16_t rbStart = 0; uint16_t rbStart = 0;
uint16_t rbSize = 50; /* due to OAI UE limitations */ uint16_t rbSize = 106; /* due to OAI UE limitations */
if (rbSize>bw) if (rbSize>bw)
rbSize = bw; rbSize = bw;
......
...@@ -317,6 +317,8 @@ void handle_nr_ul_harq(module_id_t mod_id, ...@@ -317,6 +317,8 @@ void handle_nr_ul_harq(module_id_t mod_id,
} }
NR_UE_info_t *UE_info = &RC.nrmac[mod_id]->UE_info; NR_UE_info_t *UE_info = &RC.nrmac[mod_id]->UE_info;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_ServingCellConfigCommon_t *scc = RC.nrmac[mod_id]->common_channels->ServingCellConfigCommon;
const int num_slots = nr_slots_per_frame[*scc->ssbSubcarrierSpacing];
const int8_t harq_pid = sched_ctrl->feedback_ul_harq.head; const int8_t harq_pid = sched_ctrl->feedback_ul_harq.head;
if (crc_pdu->harq_id != harq_pid && harq_pid < 0) { if (crc_pdu->harq_id != harq_pid && harq_pid < 0) {
...@@ -330,7 +332,8 @@ void handle_nr_ul_harq(module_id_t mod_id, ...@@ -330,7 +332,8 @@ void handle_nr_ul_harq(module_id_t mod_id,
DevAssert(harq_pid == crc_pdu->harq_id); DevAssert(harq_pid == crc_pdu->harq_id);
remove_front_nr_list(&sched_ctrl->feedback_ul_harq); remove_front_nr_list(&sched_ctrl->feedback_ul_harq);
NR_UE_ul_harq_t *harq = &sched_ctrl->ul_harq_processes[harq_pid]; NR_UE_ul_harq_t *harq = &sched_ctrl->ul_harq_processes[harq_pid];
DevAssert(harq->feedback_slot == slot - 1); sub_frame_t lastSlot = (slot + num_slots - 1) % num_slots;
DevAssert(harq->feedback_slot == lastSlot);
DevAssert(harq->is_waiting); DevAssert(harq->is_waiting);
harq->feedback_slot = -1; harq->feedback_slot = -1;
harq->is_waiting = false; harq->is_waiting = false;
...@@ -956,7 +959,7 @@ void nr_schedule_ulsch(module_id_t module_id, ...@@ -956,7 +959,7 @@ void nr_schedule_ulsch(module_id_t module_id,
memset(pusch_pdu, 0, sizeof(nfapi_nr_pusch_pdu_t)); memset(pusch_pdu, 0, sizeof(nfapi_nr_pusch_pdu_t));
future_ul_tti_req->n_pdus += 1; future_ul_tti_req->n_pdus += 1;
LOG_D(MAC, "%4d.%2d Scheduling UE specific PUSCH\n", frame, slot); LOG_D(MAC, "%4d.%2d Scheduling UE specific PUSCH for %4d.%2d\n", frame, slot,sched_pusch->frame,sched_pusch->slot);
pusch_pdu->pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA; pusch_pdu->pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA;
pusch_pdu->rnti = rnti; pusch_pdu->rnti = rnti;
......
...@@ -182,9 +182,9 @@ gNBs = ...@@ -182,9 +182,9 @@ gNBs =
# dl_UL_TransmissionPeriodicity # dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 6; dl_UL_TransmissionPeriodicity = 6;
nrofDownlinkSlots = 7; nrofDownlinkSlots = 5;
nrofDownlinkSymbols = 6; nrofDownlinkSymbols = 6;
nrofUplinkSlots = 2; nrofUplinkSlots = 4;
nrofUplinkSymbols = 4; nrofUplinkSymbols = 4;
ssPBCH_BlockPower = 10; ssPBCH_BlockPower = 10;
......
...@@ -182,9 +182,9 @@ gNBs = ...@@ -182,9 +182,9 @@ gNBs =
# dl_UL_TransmissionPeriodicity # dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10 # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 6; dl_UL_TransmissionPeriodicity = 6;
nrofDownlinkSlots = 7; nrofDownlinkSlots = 5;
nrofDownlinkSymbols = 6; nrofDownlinkSymbols = 6;
nrofUplinkSlots = 2; nrofUplinkSlots = 4;
nrofUplinkSymbols = 4; nrofUplinkSymbols = 4;
ssPBCH_BlockPower = 10; ssPBCH_BlockPower = 10;
......
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