Commit a373568a authored by Khodr Saaifan's avatar Khodr Saaifan Committed by Thomas Schlichter

code clean up eNB UE

parent 2058176b
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This diff is collapsed.
......@@ -37,11 +37,6 @@
#include "PHY/sse_intrin.h"
#include "T.h"
//SFN
#include "sudas_tm4.h"
#ifndef USER_MODE
#define NOCYGWIN_STATIC static
#else
......@@ -152,8 +147,6 @@ int rx_pdsch(PHY_VARS_UE *ue,
break;
case PDSCH:
//sudas_LOG_PHY(debug_sudas_LOG_PHY,"ue->DLSCH: PDSCH; \n");
//fflush(debug_sudas_LOG_PHY);
pdsch_vars = ue->pdsch_vars[ue->current_thread_id[subframe]];
dlsch = ue->dlsch[ue->current_thread_id[subframe]][eNB_id];
//printf("status TB0 = %d, status TB1 = %d \n", dlsch[0]->harq_processes[harq_pid]->status, dlsch[1]->harq_processes[harq_pid]->status);
......@@ -326,8 +319,7 @@ int rx_pdsch(PHY_VARS_UE *ue,
dlsch0_harq->mimo_mode);
}
} else if (beamforming_mode==0) { //else if nb_antennas_ports_eNB==1 && beamforming_mode == 0
//1)
nb_rb = dlsch_extract_rbs_single(common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].rxdataF,
nb_rb = dlsch_extract_rbs_single(common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].rxdataF,
common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[eNB_id],
pdsch_vars[eNB_id]->rxdataF_ext,
pdsch_vars[eNB_id]->dl_ch_estimates_ext,
......@@ -785,10 +777,7 @@ int rx_pdsch(PHY_VARS_UE *ue,
}
} else {
//sudas_LOG_PHY(debug_sudas_LOG_PHY,"ue->measurements: rx_pdsch: dlsch_detection_mrc(); \n");
//fflush(debug_sudas_LOG_PHY);
//if (dlsch0_harq->mimo_mode<LARGE_CDD)//Apply it for Alamouti only
if (dlsch0_harq->mimo_mode != TM4_NO_PRECODING)
if (dlsch0_harq->mimo_mode != TM4_NO_PRECODING)
{
dlsch_detection_mrc(frame_parms,
pdsch_vars[eNB_id]->rxdataF_comp0,
......@@ -818,9 +807,6 @@ int rx_pdsch(PHY_VARS_UE *ue,
nb_rb);
*/
} else if (dlsch0_harq->mimo_mode == ALAMOUTI) {
//sudas_LOG_PHY(debug_sudas_LOG_PHY,"ue->measurements: rx_pdsch: dlsch_alamouti(); \n");
// fflush(debug_sudas_LOG_PHY);
dlsch_alamouti(frame_parms,
pdsch_vars[eNB_id]->rxdataF_comp0,
pdsch_vars[eNB_id]->dl_ch_mag0,
......
......@@ -628,10 +628,10 @@ int allocate_REs_in_RB(PHY_VARS_eNB* phy_vars_eNB,
((int16_t *)&qpsk[0])[0] = gain_lin_QPSK;
((int16_t *)&qpsk[0])[1] = gain_lin_QPSK;
((int16_t *)&qpsk[1])[0] = -gain_lin_QPSK;
((int16_t *)&qpsk[1])[1] = gain_lin_QPSK;
((int16_t *)&qpsk[2])[0] = gain_lin_QPSK;
((int16_t *)&qpsk[2])[1] = -gain_lin_QPSK;
((int16_t *)&qpsk[3])[0] = -gain_lin_QPSK;
((int16_t *)&qpsk[1])[1] = gain_lin_QPSK;;
((int16_t *)&qpsk[2])[0] = gain_lin_QPSK;;
((int16_t *)&qpsk[2])[1] = -gain_lin_QPSK;;
((int16_t *)&qpsk[3])[0] = -gain_lin_QPSK;;
((int16_t *)&qpsk[3])[1] = -gain_lin_QPSK;
if ((dlsch0_harq != NULL) && (dlsch1_harq != NULL)) { //this is for TM3, TM4
......@@ -958,9 +958,9 @@ int allocate_REs_in_RB(PHY_VARS_eNB* phy_vars_eNB,
((int16_t *)&txdataF[1][tti_offset+2])[1] += -((int16_t *)&txdataF[0][tti_offset])[1];
}
}
/*Author: Khodr Saaifan (Fraunhofer IIs)
* RE mapping for TM4
*/
//Author: Khodr Saaifan (Fraunhofer IIs)
// RE mapping for TM4 with No precoding
else if (mimo_mode == TM4_NO_PRECODING){
*re_allocated = *re_allocated + 1;
amp = (int16_t)(((int32_t)tmp_amp*ONE_OVER_SQRT2_Q15)>>15);
......
......@@ -37,8 +37,6 @@
#include "LAYER2/MAC/extern.h"
#include "LAYER2/MAC/defs.h"
//SFN
#include "sudas_tm4.h"
#ifndef USER_MODE
#include "ARCH/CBMIMO1/DEVICE_DRIVER/extern.h"
......@@ -1432,7 +1430,9 @@ void rx_phich(PHY_VARS_UE *ue,
ulsch->harq_processes[harq_pid]->rvidx = rv_table[ulsch->harq_processes[harq_pid]->round&3];
ulsch->O_RI = 0;
ulsch->O = 0;
//sfn: TM4 reporting
//Author: Khodr Saaifan
// :Make default UCI is wideband_cqi_rank1_2A
// :enable RI
//ulsch->uci_format = HLC_subband_cqi_nopmi;
ulsch->uci_format = wideband_cqi_rank1_2A;
......@@ -1447,15 +1447,13 @@ void rx_phich(PHY_VARS_UE *ue,
}
else
{
//sfn
//sudas_LOG_PHY(debug_sudas_LOG_PHY,"ret: format HLC_subband_cqi_nopmi\n");
// fflush(debug_sudas_LOG_PHY);
// ulsch->harq_processes[harq_pid]->subframe_scheduling_flag = 1;
ulsch->harq_processes[harq_pid]->rvidx = rv_table[ulsch->harq_processes[harq_pid]->round&3];
ulsch->O_RI = 0;
ulsch->O = 0;
//sfn: TM4 reporting
//Author: Khodr Saaifan
// :Make default UCI is wideband_cqi_rank1_2A
// :enable RI
//ulsch->uci_format = HLC_subband_cqi_nopmi;
ulsch->uci_format = wideband_cqi_rank1_2A;
//LOG_I(PHY,"[HARQ-UL harqId: %d] PHICH NACK ==> subframe_scheduling_flag = %d round: %d\n", harq_pid, ulsch->harq_processes[harq_pid]->subframe_scheduling_flag,ulsch->harq_processes[harq_pid]->round);
......@@ -1618,8 +1616,9 @@ void generate_phich_top(PHY_VARS_eNB *eNB,
ulsch[UE_id]->harq_processes[harq_pid]->O_RI = 0;
ulsch[UE_id]->harq_processes[harq_pid]->Or2 = 0;
ulsch[UE_id]->harq_processes[harq_pid]->Or1 = 0;
//sfn: TM4 reporting at eNB
//Author: Khodr Saaifan
// :Make default UCI is wideband_cqi_rank1_2A
// :enable RI
ulsch[UE_id]->harq_processes[harq_pid]->uci_format = wideband_cqi_rank1_2A;
//ulsch[UE_id]->harq_processes[harq_pid]->uci_format = HLC_subband_cqi_nopmi;
......
......@@ -708,14 +708,14 @@ int dump_eNB_stats(PHY_VARS_eNB *eNB, char* buffer, int length)
eNB->UE_stats[UE_id].rank,
eNB->UE_stats[UE_id].rank? pmi2hex_2Ar2(eNB->UE_stats[UE_id].DL_pmi_single) : pmi2hex_2Ar1(eNB->UE_stats[UE_id].DL_pmi_single));
len += sprintf(&buffer[len],"eNB can schedule TM %d\n",eNB->UE_stats[UE_id].rank?4:2);
len += sprintf(&buffer[len],"eNB can schedule TM 4 PMI %d\n",eNB->UE_stats[UE_id].rank?7:0);
len += sprintf(&buffer[len],"////////////////////////******************/////////////////////////////\n");
for (i=0; i<8; i++){
len+= sprintf(&buffer[len],"DL TM %d, DL Nl %d, rb %d, TBS %d, \n",
eNB->dlsch[(uint8_t)UE_id][0]->harq_processes[i]->mimo_mode==15?4 : 2,
len+= sprintf(&buffer[len],"DL TM 4 PMI%d, DL Nl %d, rb %d, TBS %d, \n",
eNB->dlsch[(uint8_t)UE_id][0]->harq_processes[i]->mimo_mode==15?7 : 0,
eNB->dlsch[(uint8_t)UE_id][0]->harq_processes[i]->Nl,
eNB->dlsch[(uint8_t)UE_id][0]->harq_processes[i]->nb_rb,
eNB->dlsch[(uint8_t)UE_id][0]->harq_processes[i]->TBS);
......
......@@ -826,7 +826,7 @@ int32_t dlsch_qpsk_llr(LTE_DL_FRAME_PARMS *frame_parms,
uint16_t pbch_pss_sss_adj,
//int16_t **llr128p,
uint8_t beamforming_mode);
//KhodrSaaifan
//Author: Khodr Saaifan @ Fraunhofer IIS
int dlsch_qpsk_llr_tm4(LTE_DL_FRAME_PARMS *frame_parms,
int32_t **rxdataF_comp,
int16_t *dlsch_llr,
......@@ -871,7 +871,7 @@ void dlsch_16qam_llr(LTE_DL_FRAME_PARMS *frame_parms,
uint16_t pbch_pss_sss_adjust,
int16_t **llr128p,
uint8_t beamforming_mode);
//KhodrSaaifan
//Author: Khodr Saaifan @ Fraunhofer IIS
void dlsch_16qam_llr_tm4(LTE_DL_FRAME_PARMS *frame_parms,
int32_t **rxdataF_comp,
int16_t *dlsch_llr,
......@@ -935,7 +935,7 @@ void dlsch_64qam_llr(LTE_DL_FRAME_PARMS *frame_parms,
uint32_t llr_offset,
uint8_t beamforming_mode);
//KhodrSaaifan
//Author: Khodr Saaifan @ Fraunhofer IIS
void dlsch_64qam_llr_tm4(LTE_DL_FRAME_PARMS *frame_parms,
int32_t **rxdataF_comp,
int16_t *dlsch_llr,
......@@ -991,20 +991,7 @@ void dlsch_alamouti(LTE_DL_FRAME_PARMS *frame_parms,
uint8_t symbol,
uint16_t nb_rb);
/** \fn KhodrSaaifan: dlsch_postcoding_tm4(LTE_DL_FRAME_PARMS *frame_parms,
int32_t **rxdataF_comp,
int32_t **dl_ch_mag,
int32_t **dl_ch_magb,
uint8_t symbol,
uint16_t nb_rb)
\brief This function does Alamouti combining on RX and prepares LLR inputs by skipping pilots, PBCH and primary/secondary synchronization signals.
@param frame_parms Frame descriptor structure
@param rxdataF_comp Compensated channel output
@param dl_ch_mag First squared-magnitude of channel (16QAM and 64QAM) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position
@param dl_ch_magb Second squared-magnitude of channel (64QAM only) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position
@param symbol Symbol in sub-frame
@param nb_rb Number of RBs in this allocation
*/
//Author: Khodr Saaifan @ Fraunhofer IIS
void dlsch_postcoding_tm4(LTE_DL_FRAME_PARMS *frame_parms,
int **rxdataF_comp,
int **dl_ch_mag,
......
......@@ -35,13 +35,9 @@
#include "UTIL/LOG/log.h"
#include "UTIL/LOG/vcd_signal_dumper.h"
//SFN
#include "sudas_tm4.h"
#include "T.h"
//SFN
#include "sudas_tm4.h"
//uint8_t ncs_cell[20][7];
//#define DEBUG_PUCCH_TX
//#define DEBUG_PUCCH_RX
......@@ -479,7 +475,6 @@ void generate_pucch1x(int32_t **txdataF,
ref_re = (int16_t)(((int32_t)tmp_re*W_re - (int32_t)tmp_im*W_im)>>15);
ref_im = (int16_t)(((int32_t)tmp_re*W_im + (int32_t)tmp_im*W_re)>>15);
if ((l<2)||(l>=(N_UL_symb-2))) { //these are PUCCH data symbols
switch (fmt) {
case pucch_format1: //OOK 1-bit
......@@ -543,22 +538,11 @@ void generate_pucch1x(int32_t **txdataF,
nprime=nprime1;
n_oc =n_oc1;
} // ns
zptr = (int16_t *)z;
/* sudas_LOG_PHY(debug_sudas_LOG_PHY,"Allocat z[12*14] sequence matrix\n");
int n_sfn=0;
for (n_sfn=0;n_sfn<(12*14);n_sfn++)
{
sudas_LOG_PHY(debug_sudas_LOG_PHY," z[%d]_Re= %d z[%d]_Im= %d\n",n_sfn,zptr[n_sfn<<1],n_sfn,zptr[1+(n_sfn<<1)]);
}*/
rem = (((deltaPUCCH_Shift*Ncs1_div_deltaPUCCH_Shift)&7)>0) ? 1 : 0;
rem = ((((deltaPUCCH_Shift*Ncs1_div_deltaPUCCH_Shift)>>3)&7)>0) ? 1 : 0;
m = (n1_pucch < thres) ? NRB2 : (((n1_pucch-thres)/(12*c/deltaPUCCH_Shift))+NRB2+((deltaPUCCH_Shift*Ncs1_div_deltaPUCCH_Shift)>>3)+rem);
sudas_LOG_PHY(debug_sudas_LOG_PHY,"Allocat PUCCH amp %d m %d nprime0 %d nprime1 %d n_oc0 %d n_oc1 %d \n",amp,m,nprime0,nprime1,n_oc0,n_oc1);
#ifdef FHG_LOG
fflush(debug_sudas_LOG_PHY);
#endif
#ifdef DEBUG_PUCCH_TX
printf("[PHY] PUCCH: m %d\n",m);
#endif
......@@ -2059,15 +2043,10 @@ uint32_t rx_pucch(PHY_VARS_eNB *eNB,
n_oc =n_oc1;
} // ns
rem = ((((deltaPUCCH_Shift*Ncs1_div_deltaPUCCH_Shift))&7)>0) ? 1 : 0;
rem = ((((deltaPUCCH_Shift*Ncs1_div_deltaPUCCH_Shift)>>3)&7)>0) ? 1 : 0;
m = (n1_pucch < thres) ? NRB2 : (((n1_pucch-thres)/(12*c/deltaPUCCH_Shift))+NRB2+((deltaPUCCH_Shift*Ncs1_div_deltaPUCCH_Shift)>>3)+rem);
sudas_LOG_MAC(debug_sudas_LOG_MAC,"format %d DemAllocat PUCCH m %d nprime0 %d nprime1 %d n_oc0 %d n_oc1 %d\n",fmt,m,nprime0,nprime1,n_oc0,n_oc1);
#ifdef FHG_LOG
fflush(debug_sudas_LOG_MAC);
#endif
#ifdef DEBUG_PUCCH_RX
printf("[eNB] PUCCH: m %d\n",m);
#endif
......@@ -2202,25 +2181,11 @@ uint32_t rx_pucch(PHY_VARS_eNB *eNB,
}
*/
sudas_LOG_MAC(debug_sudas_LOG_MAC,"dB_fixed(stat_max) %d pucch1_thres %d sigma2_dB %d\n",dB_fixed(stat_max),pucch1_thres,sigma2_dB);
#ifdef FHG_LOG
fflush(debug_sudas_LOG_MAC);
#endif
// This is a moving average of the PUCCH1 statistics conditioned on being above or below the threshold
/*SFN:
*
sigma2_dB= eNB->measurements[0].n0_subband_power_tot_dB[0]-10; where
measurements->n0_power_tot += measurements->n0_power[aarx];
is not correct.
n0_power_tot denotes received noise variance for two antennas measured by sounding reference signal.
n0_power_tot=N_aarx*[(N_0*df)*N_FFT]*N_F*Rx_Gain*(2^15)^2 which computed in time domain
In the absence of PUCCH signal, stat_max will hold the received power of noise computed in frequency after DFT
stat_max=N_aarx*[(N_0*df)*N_FFT]*N_F*Rx_Gain*(2^15)^2
In the presence of PUCCH signal
stat_max=H_rx^2*N_FFT*(2^15)^2+N_aarx*[(N_0*df)*N_FFT]*N_F*Rx_Gain*(2^15)^2
*/
if ((dB_fixed(stat_max)-10)>sigma2_dB){//pucch1_thres
// Author: Khodr Saaifan @ Fraunhofer IIS
// : Adjust Thresh detection
if ((dB_fixed(stat_max)-5)>sigma2_dB){//pucch1_thres
*payload = 1;
*Po_PUCCH1_above = ((*Po_PUCCH1_above<<9) + (stat_max<<9)+1024)>>10;
//LOG_I(PHY,"[eNB] PUCCH fmt1: stat_max : %d, sigma2_dB %d (%d, %d), phase_max : %d\n",dB_fixed(stat_max),sigma2_dB,eNB->PHY_measurements_eNB[0].n0_power_tot_dBm,pucch1_thres,phase_max);
......@@ -2334,11 +2299,6 @@ uint32_t rx_pucch(PHY_VARS_eNB *eNB,
dB_fixed(*Po_PUCCH));
*/
// Do detection now
sudas_LOG_MAC(debug_sudas_LOG_MAC,"dB_fixed(stat_max) %d pucch1_thres %d sigma2_dB %d\n",dB_fixed(stat_max),pucch1_thres,sigma2_dB);
#ifdef FHG_LOG
fflush(debug_sudas_LOG_MAC);
#endif
if (sigma2_dB<(dB_fixed(stat_max)-pucch1_thres)) {//
......@@ -2352,11 +2312,11 @@ uint32_t rx_pucch(PHY_VARS_eNB *eNB,
chest_im=0;
cfo = (frame_parms->Ncp==0) ? &cfo_pucch_np[14*phase_max] : &cfo_pucch_ep[12*phase_max];
// channel estimate for first slot select DMRS SCs
// channel estimate for first slot
for (l=2; l<(nsymb>>1)-2; l++) {
off=(re<<1) + (24*l);
chest_re += (((rxcomp[aa][off]*(int32_t)cfo[l<<1])>>15) - ((rxcomp[aa][1+off]*(int32_t)cfo[1+(l<<1)])>>15))/chL;
chest_im += (((rxcomp[aa][off]*(int32_t)cfo[1+(l<<1)])>>15) + ((rxcomp[aa][1+off]*(int32_t)cfo[(l<<1)])>>15))/chL;
chest_im += (((rxcomp[aa][off]*(int32_t)cfo[1+(l<<1)])>>15) + ((rxcomp[aa][1+off]*(int32_t)cfo[(l<<1)])>>15))/chL;
}
#ifdef DEBUG_PUCCH_RX
......
......@@ -36,8 +36,6 @@
#include "LAYER2/MAC/defs.h"
#include "SCHED/defs.h"
#include "UTIL/LOG/vcd_signal_dumper.h"
//SFN
#include "sudas_tm4.h"
#include "assertions.h"
......@@ -268,15 +266,15 @@ int generate_ue_ulsch_params_from_rar(PHY_VARS_UE *ue,
ulsch->harq_processes[harq_pid]->status = ACTIVE;
if (cqireq==1) {
/*SFN: enable PMI reporting
* remove dependency on RI
* */
ulsch->O_RI = 1;
ulsch->O_RI = 1;
//Author: Khodr Saaifan @ Fraunhofer IIS
// : enable UCI rank 1 for 2 antennas format (Hardcoded)
ulsch->uci_format = wideband_cqi_rank1_2A;
ulsch->O = sizeof_wideband_cqi_rank1_2A_5MHz;
if (meas->rank[eNB_id] == 0) ulsch->o_RI[0] = 0;
else ulsch->o_RI[0] = 1;
if (meas->rank[eNB_id] == 0)
ulsch->o_RI[0] = 0;
else
ulsch->o_RI[0] = 1;
ulsch->uci_format = wideband_cqi_rank1_2A;
/*if (meas->rank[eNB_id] == 1){
......@@ -290,7 +288,6 @@ int generate_ue_ulsch_params_from_rar(PHY_VARS_UE *ue,
}*/
//ulsch->uci_format = HLC_subband_cqi_nopmi;
fill_CQI(ulsch,meas,eNB_id,0,ue->frame_parms.N_RB_DL,0, transmission_mode,ue->sinr_eff);
if (((proc->frame_tx % 100) == 0) || (proc->frame_tx < 10))
......
......@@ -256,12 +256,9 @@ void extract_CQI(void *o,UCI_format_t uci_format,LTE_eNB_UE_stats *stats, uint8_
switch(uci_format) {
case wideband_cqi_rank1_2A:
/*sfn: we are here
*
* */
stats->DL_cqi[0] = (((wideband_cqi_rank1_2A_5MHz *)o)->cqi1);
if (stats->DL_cqi[0] > 24)//limit CQI
if (stats->DL_cqi[0] > 24)
stats->DL_cqi[0] = 24;
stats->DL_pmi_single = ((wideband_cqi_rank1_2A_5MHz *)o)->pmi;
......@@ -287,8 +284,6 @@ void extract_CQI(void *o,UCI_format_t uci_format,LTE_eNB_UE_stats *stats, uint8_
break;
case HLC_subband_cqi_nopmi:
//sfn debug here
stats->DL_cqi[0] = (((HLC_subband_cqi_nopmi_5MHz *)o)->cqi1);
if (stats->DL_cqi[0] > 24)
......
......@@ -41,8 +41,7 @@
#include "extern.h"
#include "SIMULATION/ETH_TRANSPORT/extern.h"
#include "UTIL/LOG/vcd_signal_dumper.h"
//SFN
#include "sudas_tm4.h"
//#define DEBUG_ULSCH_CODING
//#define DEBUG_ULSCH_FREE 1
......@@ -208,7 +207,7 @@ uint32_t ulsch_encoding(uint8_t *a,
uint8_t control_only_flag,
uint8_t Nbundled)
{
// PHY statistics for RRC decisions
time_stats_t *seg_stats=&ue->ulsch_segmentation_stats;
time_stats_t *rm_stats=&ue->ulsch_rate_matching_stats;
time_stats_t *te_stats=&ue->ulsch_turbo_encoding_stats;
......@@ -264,11 +263,8 @@ uint32_t ulsch_encoding(uint8_t *a,
if (ulsch->O>0) {
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_ULSCH_ENCODING_FILL_CQI, VCD_FUNCTION_IN);
rnti = ue->pdcch_vars[ue->current_thread_id[subframe_rx]][eNB_id]->crnti;
//sfn target function : we start here CQI/PMI for tm_4 CQI1 and CQI2
fill_CQI(ulsch,meas,0,harq_pid,ue->frame_parms.N_RB_DL,rnti, tmode,ue->sinr_eff);
//sudas_LOG_PHY(debug_sudas_LOG_PHY,"[UE][UCI--->PUSCH] harq_pid %d subframe_Tx %d, CQI ON, RI ON \n",harq_pid,(subframe_rx+4)%10);
//fflush(debug_sudas_LOG_PHY);
LOG_D(PHY,"ULSCH Encoding rnti %x \n", rnti);
print_CQI(ulsch->o,ulsch->uci_format,0,ue->frame_parms.N_RB_DL);
......@@ -623,12 +619,8 @@ uint32_t ulsch_encoding(uint8_t *a,
i=0;
/*SFN: Enable ulsch->O_RI = 1 in dci_tools
*DO RI coding
*PUSCH_y: means repeat ucoded bit
* */
// Do RI coding
if (ulsch->O_RI == 1) {
// Do RI coding: PUSCH_y: means repeat ucoded bit
if (ulsch->O_RI == 1) {//Enabled ulsch->O_RI = 1 in dci_tools
switch (Q_m) {
case 2:
ulsch->q_RI[0] = ulsch->o_RI[0];
......@@ -764,11 +756,12 @@ uint32_t ulsch_encoding(uint8_t *a,
// channel multiplexing/interleaving
start_meas(m_stats);
//Author: Khodr Saaifan @ Fraunhofer IIS
// : Fix Hpp
Qprime_RI = Q_RI / Q_m;
Qprime_ACK = Q_ACK / Q_m;
Qprime_CQI = Q_CQI / Q_m;
//fix Hpp SFN
Hpp = Hprime + Qprime_RI;
Cmux = ulsch->Nsymb_pusch;
......@@ -776,9 +769,7 @@ uint32_t ulsch_encoding(uint8_t *a,
Rmux_prime = Rmux/Q_m;
// printf("Qprime_CQI = %d\n",Qprime_CQI);
// RI BITS
memset(y,LTE_NULL,Q_m*Hpp);
......@@ -805,6 +796,26 @@ uint32_t ulsch_encoding(uint8_t *a,
// CQI and Data bits
j=0;
/*
for (i=0,iprime=-Qprime_CQI;i<Hprime;i++,iprime++) {
while (y[Q_m*j] != LTE_NULL) j++;
if (i<Qprime_CQI) {
for (q=0;q<Q_m;q++) {
y[q+(Q_m*j)] = ulsch->q[q+(Q_m*i)];
//printf("cqi[%d] %d => y[%d]\n",q+(Q_m*i),ulsch->q[q+(Q_m*i)],q+(Q_m*j));
}
}
else {
for (q=0;q<Q_m;q++) {
y[q+(Q_m*j)] = ulsch->e[q+(Q_m*iprime)];
// printf("e[%d] %d => y[%d]\n",q+(Q_m*iprime),ulsch->e[q+(Q_m*iprime)],q+(Q_m*j));
}
}
j++;
}
*/
for (i=0; i<Qprime_CQI; i++) {
......
......@@ -51,8 +51,7 @@
#include "UTIL/LOG/vcd_signal_dumper.h"
//#define DEBUG_ULSCH_DECODING
//SFN
#include "sudas_tm4.h"
void free_eNB_ulsch(LTE_eNB_ULSCH_t *ulsch)
{
......@@ -1335,13 +1334,12 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,
r = Rmux_prime -1 - (i>>2);
for (q=0; q<Q_m; q++){
//SFN bug fix here
if (i==0)
//Author: Khodr Saaifan @ Fraunhofer IIR
// : OAI UE sets Qprime_RI to 1 (1 symbol)
// : However, we note that the OAI eNB configures Qprime_RI as 1 or 2 or 3
// : Thus, we limit Qprime_RI to 1 for now to decode RI correctly
if (i==0)
ulsch_harq->q_RI[(q+(Q_m*i))%len_RI] = y[q+(Q_m*((r*Cmux) + columnset[j]))];
// sudas_LOG_PHY(debug_sudas_LOG_PHY,"[SFN goo] ulsch_harq->q_RI[0] %d ulsch_harq->q_RI[1] %d len_RI %d\n",ulsch_harq->q_RI[0],ulsch_harq->q_RI[1],len_RI);
// fflush(debug_sudas_LOG_PHY);
}
ytag[(r*Cmux) + columnset[j]] = LTE_NULL;
j=(j+3)&3;
......@@ -1547,52 +1545,19 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,
}
// RI
//SFN: fix here
// rank 1
// rank 1
// Author: Khodr Saaifan @ Fraunhofer IIS
// : Fix RI detection
if ((ulsch_harq->O_RI == 1) && (Qprime_RI > 0)) {
switch (Q_m) {
case 2:
ulsch_harq->o_RI[0] =((ulsch_harq->q_RI[0] + ulsch_harq->q_RI[1]) > 0) ? 1 : 0;
// sudas_LOG_PHY(debug_sudas_LOG_PHY,"[SFN] ulsch_harq->q_RI[0] %d ulsch_harq->q_RI[1] %d Qprime_RI %d\n",ulsch_harq->q_RI[0],ulsch_harq->q_RI[1],Qprime_RI);
//sudas_LOG_PHY(debug_sudas_LOG_PHY,"[SFN] ulsch_harq->q_RI[0] %d ulsch_harq->q_RI[1] %d Qprime_RI %d\n",ulsch_harq->q_RI[0],ulsch_harq->q_RI[1],Qprime_RI);
//fflush(debug_sudas_LOG_PHY);
break;
case 4:
ulsch_harq->o_RI[0] =((ulsch_harq->q_RI[0]+ ulsch_harq->q_RI[1]) > 0) ? 1 : 0;
//sudas_LOG_PHY(debug_sudas_LOG_PHY,"[SFN] ulsch_harq->q_RI[0] %d ulsch_harq->q_RI[1] %d Qprime_RI %d\n",ulsch_harq->q_RI[0],ulsch_harq->q_RI[1],Qprime_RI);
//fflush(debug_sudas_LOG_PHY);
break;
case 6:
ulsch_harq->o_RI[0] =((ulsch_harq->q_RI[0] + ulsch_harq->q_RI[1]) > 0) ? 1 : 0;
//sudas_LOG_PHY(debug_sudas_LOG_PHY,"[SFN] ulsch_harq->q_RI[0] %d ulsch_harq->q_RI[1] %d Qprime_RI %d\n",ulsch_harq->q_RI[0],ulsch_harq->q_RI[1],Qprime_RI);
//fflush(debug_sudas_LOG_PHY);
break;
}
//sudas_LOG_PHY(debug_sudas_LOG_PHY,"[SFN]ulsch_harq->o_RI[0] %d Qprime_RI %d\n",ulsch_harq->o_RI[0],Qprime_RI);
//fflush(debug_sudas_LOG_PHY);
}
//ulsch_harq->o_RI[0] = ulsch_harq->q_RI[0]&1;//((ulsch_harq->q_RI[0] + ulsch_harq->q_RI[Q_m/2]) > 0) ? 0 : 1;
// CQI
static int ri_disply_cntr=0;
// printf("before cqi c[%d] = %p\n",0,ulsch_harq->c[0]);
ulsch_harq->cqi_crc_status = 0;
if (Q_CQI>0) {
/*ri_disply_cntr++;
if (ri_disply_cntr>10){
ri_disply_cntr=0;
//show log
LOG_I(PHY,"Qprime_RI %d [SFN CQI reports %d] O_RI %d o_RI[0]%d\n",Qprime_RI,ri_disply_cntr,ulsch_harq->O_RI,ulsch_harq->o_RI[0]);
}*/
//sudas_LOG_PHY(debug_sudas_LOG_PHY,"[SFN]ulsch_harq->O_RI %d ulsch_harq->o_RI[0]%d\n",ulsch_harq->O_RI,ulsch_harq->o_RI[0]);
// fflush(debug_sudas_LOG_PHY);
memset((void *)&dummy_w_cc[0],0,3*(ulsch_harq->Or1+8+32));
O_RCC = generate_dummy_w_cc(ulsch_harq->Or1+8,
......
......@@ -615,8 +615,8 @@ typedef enum {
TM7=12,
TM8=13,
TM9_10=14,
/*: Khodr Saaifan (Fraunhofer IIS):
*Test TM4 2 layers*/
//Author: Khodr Saaifan @ Fraunhofer IIS
// :Add TM4_NO_PRECODING to test TM4 for 2 layers
TM4_NO_PRECODING=15
} MIMO_mode_t;
......
......@@ -252,7 +252,7 @@
#define AMP_OVER_2 (AMP>>1)
/// Threshold for PUCCH Format 1 detection
#define PUCCH1_THRES 0
#define PUCCH1_THRES 4
/// Threshold for PUCCH Format 1a/1b detection
#define PUCCH1a_THRES 4
......
......@@ -57,11 +57,6 @@
#include <time.h>
//SFN
#include "sudas_tm4.h"
#if defined(ENABLE_ITTI)
# include "intertask_interface.h"
#endif
......@@ -2153,24 +2148,10 @@ void pucch_procedures(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,int UE_id,int harq
n1_pucch0,n1_pucch1,n1_pucch2,n1_pucch3,do_SR);
if ((n1_pucch0==-1) && (n1_pucch1==-1) && (do_SR==0)) { // no TX PDSCH that have to be checked and no SR for this UE_id
sudas_LOG_MAC(debug_sudas_LOG_MAC,"[eNB %d][PDSCH %x] Frame %d, subframe %d No Checking for PUCCH (%d,%d,%d,%d) SR %d\n",
eNB->Mod_id,eNB->dlsch[UE_id][0]->rnti,
frame,subframe,
n1_pucch0,n1_pucch1,n1_pucch2,n1_pucch3,do_SR);
#ifdef FHG_LOG
fflush(debug_sudas_LOG_MAC);
#endif
} else {
// otherwise we have some PUCCH detection to do
sudas_LOG_MAC(debug_sudas_LOG_MAC,"[eNB %d][PDSCH %x] Frame %d, subframe %d start Checking for PUCCH (%d,%d,%d,%d) SR %d\n",
eNB->Mod_id,eNB->dlsch[UE_id][0]->rnti,
frame,subframe,
n1_pucch0,n1_pucch1,n1_pucch2,n1_pucch3,do_SR);
#ifdef FHG_LOG
fflush(debug_sudas_LOG_MAC);
#endif
// Null out PUCCH PRBs for noise measurement
// Null out PUCCH PRBs for noise measurement
switch(fp->N_RB_UL) {
case 6:
eNB->rb_mask_ul[0] |= (0x1 | (1<<5)); //position 5
......@@ -2220,15 +2201,6 @@ void pucch_procedures(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,int UE_id,int harq
subframe,
SR_payload,
eNB->scheduling_request_config[UE_id].sr_PUCCH_ResourceIndex);
sudas_LOG_MAC(debug_sudas_LOG_MAC,"Demodulating PUCCH for SR: RNTI %x Frame %d subframe %d Checking SR is %d (SR n1pucch is %d)\n",
eNB->ulsch[UE_id]->rnti,
frame,
subframe,
SR_payload,
eNB->scheduling_request_config[UE_id].sr_PUCCH_ResourceIndex);
#ifdef FHG_LOG
fflush(debug_sudas_LOG_MAC);
#endif
}
#ifdef PHY_ABSTRACTION
else {
......@@ -2244,18 +2216,13 @@ void pucch_procedures(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,int UE_id,int harq
#endif
}// do_SR==1
if ((n1_pucch0==-1) && (n1_pucch1==-1))
{ // just check for SR
}
else if (fp->frame_type==FDD) { // FDD
if ((n1_pucch0==-1) && (n1_pucch1==-1)) { // just check for SR
} else if (fp->frame_type==FDD) { // FDD
// if SR was detected, use the n1_pucch from SR, else use n1_pucch0
// n1_pucch0 = (SR_payload==1) ? eNB->scheduling_request_config[UE_id].sr_PUCCH_ResourceIndex:n1_pucch0;
// n1_pucch0 = (SR_payload==1) ? eNB->scheduling_request_config[UE_id].sr_PUCCH_ResourceIndex:n1_pucch0;
LOG_D(PHY,"Demodulating PUCCH for ACK/NAK: n1_pucch0 %d (%d), SR_payload %d\n",n1_pucch0,eNB->scheduling_request_config[UE_id].sr_PUCCH_ResourceIndex,SR_payload);
sudas_LOG_MAC(debug_sudas_LOG_MAC,"Demodulating PUCCH for ACK/NAK: n1_pucch0 %d (%d), SR_payload %d\n",n1_pucch0,eNB->scheduling_request_config[UE_id].sr_PUCCH_ResourceIndex,SR_payload);
#ifdef FHG_LOG
fflush(debug_sudas_LOG_MAC);
#endif
if (eNB->abstraction_flag == 0) {
metric0 = rx_pucch(eNB,
pucch_format1a,
......@@ -2267,10 +2234,6 @@ void pucch_procedures(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,int UE_id,int harq
frame,
subframe,
PUCCH1a_THRES);
sudas_LOG_MAC(debug_sudas_LOG_MAC,"Demodulating metric0 %d metric0_SR %d ack %d do_SR %d\n",metric0,metric0_SR,pucch_payload0[0],do_SR);
#ifdef FHG_LOG
fflush(debug_sudas_LOG_MAC);
#endif
}
#ifdef PHY_ABSTRACTION
else {
......@@ -2282,16 +2245,16 @@ void pucch_procedures(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,int UE_id,int harq
pucch_payload0);
}
#endif
//Author : Khodr Saaifan @Fraunhofer
// : Need to test the SR and ACK/NACK feedbacks
/* cancel SR detection if reception on n1_pucch0 is better than on SR PUCCH resource index */
//if (do_SR && (metric0 > metric0_SR)) SR_payload = 0;
if (do_SR && (metric0 > metric0_SR)) SR_payload = 0;
/*
if (do_SR && (metric0 <= metric0_SR)) {
// when transmitting ACK/NACK on SR PUCCH resource index, SR payload is always 1
// SR_payload = 1;
sudas_LOG_MAC(debug_sudas_LOG_MAC,"Demodulating pucch_format1a shortneed %d\n",do_srs);
fflush(debug_sudas_LOG_MAC);
SR_payload = 1;
if (eNB->abstraction_flag == 0) {
metric0=rx_pucch(eNB,
......@@ -2305,8 +2268,6 @@ void pucch_procedures(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,int UE_id,int harq
subframe,
PUCCH1a_THRES);
}
sudas_LOG_MAC(debug_sudas_LOG_MAC,"Demodulating pucch_format1a ACK/NACK %d\n",pucch_payload0[0]);
fflush(debug_sudas_LOG_MAC);
#ifdef PHY_ABSTRACTION
else {
metric0 = rx_pucch_emul(eNB,
......@@ -2326,7 +2287,7 @@ void pucch_procedures(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,int UE_id,int harq
frame,subframe,
pucch_payload0[0],metric0);
#endif
*/
process_HARQ_feedback(UE_id,eNB,proc,
0,// pusch_flag
pucch_payload0,
......
......@@ -54,8 +54,7 @@
#include "LAYER2/MAC/extern.h"
#include "LAYER2/MAC/defs.h"
#include "UTIL/LOG/log.h"
//SFN
#include "sudas_tm4.h"
#ifdef EMOS
fifo_dump_emos_UE emos_dump_UE;
#endif
......@@ -412,10 +411,8 @@ uint8_t is_cqi_TXOp(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id)
{
int subframe = proc->subframe_tx;
int frame = proc->frame_tx;
CQI_REPORTPERIODIC *cqirep = &ue->cqi_report_config[eNB_id].CQI_ReportPeriodic;
//sudas_LOG_PHY(debug_sudas_LOG_PHY,"[UE][UCI--->PUSCH] CQI_ReportPeriodic cqirep->Npd %d cqirep->N_OFFSET_CQI %d \n",cqirep->Npd,cqirep->N_OFFSET_CQI);
//fflush(debug_sudas_LOG_PHY);
//LOG_I(PHY,"[UE %d][CRNTI %x] AbsSubFrame %d.%d Checking for CQI TXOp (cqi_ConfigIndex %d) isCQIOp %d\n",
// ue->Mod_id,ue->pdcch_vars[eNB_id]->crnti,frame,subframe,
// cqirep->cqi_PMI_ConfigIndex,
......@@ -1530,8 +1527,6 @@ void ue_prach_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uin
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_OUT);
}
// UL UE Procedure for Shared Channel
void ue_ulsch_uespec_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t abstraction_flag) {
int harq_pid;
......@@ -1539,14 +1534,14 @@ void ue_ulsch_uespec_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB
int subframe_tx=proc->subframe_tx;
int Mod_id = ue->Mod_id;
int CC_id = ue->CC_id;
uint8_t Msg3_flag=0;//schedule RRC request
uint16_t first_rb, nb_rb;//indicate the first RB in the virtual RB array
uint8_t Msg3_flag=0;
uint16_t first_rb, nb_rb;
unsigned int input_buffer_length;
int i;
int aa;
int tx_amp;
uint8_t ulsch_input_buffer[5477] __attribute__ ((aligned(32)));//32 bytes aligned for SIMD operation
uint8_t access_mode;//indicate PUSCH or PUCCH
uint8_t ulsch_input_buffer[5477] __attribute__ ((aligned(32)));
uint8_t access_mode;
uint8_t Nbundled=0;
uint8_t NbundledCw1=0;
uint8_t ack_status_cw0=0;
......@@ -1596,9 +1591,9 @@ void ue_ulsch_uespec_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB
Msg3_flag=0;
}
}
// Check and test if the schedulig ifo are valid for PUSCH channel
// it uses isBad to test the validation of the parms first_rb, nb_rb, and RV index
if (ue->ulsch[eNB_id]->harq_processes[harq_pid]->subframe_scheduling_flag == 1) {
uint8_t isBad = 0;
if (ue->frame_parms.N_RB_UL <= ue->ulsch[eNB_id]->harq_processes[harq_pid]->first_rb) {
LOG_D(PHY,"Invalid PUSCH first_RB=%d for N_RB_UL=%d\n",
......@@ -1640,7 +1635,6 @@ void ue_ulsch_uespec_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB
ue->ulsch[eNB_id]->harq_processes[harq_pid]->subframe_scheduling_flag = 0;
}
}
if (ue->ulsch[eNB_id]->harq_processes[harq_pid]->subframe_scheduling_flag == 1) {
ue->generate_ul_signal[eNB_id] = 1;
......@@ -1648,14 +1642,13 @@ void ue_ulsch_uespec_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB
// deactivate service request
// ue->ulsch[eNB_id]->harq_processes[harq_pid]->subframe_scheduling_flag = 0;
LOG_D(PHY,"Generating PUSCH (Abssubframe: %d.%d): harq-Id: %d, round: %d, MaxReTrans: %d \n",frame_tx,subframe_tx,harq_pid,ue->ulsch[eNB_id]->harq_processes[harq_pid]->round,ue->ulsch[eNB_id]->Mlimit);
// Control HARQ process round=0,...,Mlimit - 1, where Mlimit = 4
if (ue->ulsch[eNB_id]->harq_processes[harq_pid]->round >= (ue->ulsch[eNB_id]->Mlimit - 1))
{
LOG_D(PHY,"PUSCH MAX Retransmission achieved ==> send last pusch\n");
ue->ulsch[eNB_id]->harq_processes[harq_pid]->subframe_scheduling_flag = 0;
ue->ulsch[eNB_id]->harq_processes[harq_pid]->round = 0;
}
// Get ack status for cw0 for antenna 0 for PDSCH
ack_status_cw0 = reset_ack(&ue->frame_parms,
ue->dlsch[ue->current_thread_id[proc->subframe_rx]][eNB_id][0]->harq_ack,
subframe_tx,
......@@ -1663,7 +1656,6 @@ void ue_ulsch_uespec_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB
ue->ulsch[eNB_id]->o_ACK,
&Nbundled,
0);
// Reset ack status for cw1 for antenna 1 for PDSCH ()
ack_status_cw1 = reset_ack(&ue->frame_parms,
ue->dlsch[ue->current_thread_id[proc->subframe_rx]][eNB_id][1]->harq_ack,
subframe_tx,
......@@ -1689,13 +1681,8 @@ void ue_ulsch_uespec_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB
// compute CQI/RI resources
compute_cqi_ri_resources(ue, ue->ulsch[eNB_id], eNB_id, ue->ulsch[eNB_id]->rnti, P_RNTI, CBA_RNTI, cqi_status, ri_status);
sudas_LOG_PHY(debug_sudas_LOG_PHY,"Generating PUSCH (frame_tx %d subframe_tx %d): o_ACK %d ack_status_cw0 %d\n",frame_tx,subframe_tx,ue->ulsch[eNB_id]->o_ACK[0],ack_status_cw0);
#ifdef FHG_LOG
fflush(debug_sudas_LOG_PHY);
#endif
if (ack_status_cw0 > 0) {
// check if we received a PDSCH at subframe_tx - 4
// ==> send ACK/NACK on PUSCH
if (ue->frame_parms.frame_type == FDD)
......@@ -2174,7 +2161,8 @@ void ue_pucch_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uin
SR_payload = 1;
}
}
//Author: Khodr Saaifan @Fraunhofer
// : Get ack for cw0 then reset the request
ack_status_cw0 = reset_ack(&ue->frame_parms,
ue->dlsch[ue->current_thread_id[proc->subframe_rx]][eNB_id][0]->harq_ack,
subframe_tx,
......@@ -2182,7 +2170,8 @@ void ue_pucch_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uin
pucch_ack_payload,
&N_kbundled,
0);
//Author: Khodr Saaifan @Fraunhofer
// : Get ack for cw1 then reset the request
ack_status_cw1 = reset_ack(&ue->frame_parms,
ue->dlsch[ue->current_thread_id[proc->subframe_rx]][eNB_id][1]->harq_ack,
subframe_tx,
......@@ -2237,12 +2226,6 @@ void ue_pucch_procedures(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,uin
// Generate PUCCH signal
ue->generate_ul_signal[eNB_id] = 1;
sudas_LOG_PHY(debug_sudas_LOG_PHY,"PUCCH Format:: %d SR %d ACK_status %d CQI_status %d RI_status %d \n",format, SR_payload,ack_status_cw0,cqi_status,ri_status);
#ifdef FHG_LOG
fflush(debug_sudas_LOG_PHY);
#endif
switch (format) {
case pucch_format1:
case pucch_format1a:
......@@ -2342,10 +2325,7 @@ sudas_LOG_PHY(debug_sudas_LOG_PHY,"PUCCH Format:: %d SR %d ACK_status %d CQI_sta
pucch_payload,
tx_amp,
subframe_tx);
sudas_LOG_PHY(debug_sudas_LOG_PHY,"PUCCH Format %d pucch_resource %d isShortenPucch %d \n",format, pucch_resource,isShortenPucch);
#ifdef FHG_LOG
fflush(debug_sudas_LOG_PHY);
#endif
} else {
#ifdef PHY_ABSTRACTION
LOG_D(PHY,"Calling generate_pucch_emul ... (ACK %d %d, SR %d)\n",pucch_ack_payload[0],pucch_ack_payload[1],SR_payload);
......@@ -2478,10 +2458,6 @@ void phy_procedures_UE_TX(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,ui
}
if (ue->UE_mode[eNB_id] == PUSCH) {
sudas_LOG_PHY(debug_sudas_LOG_PHY,"****** start TX-Chain Check if PUCCH is active for AbsSubframe %d.%d ******\n", frame_tx, subframe_tx);
#ifdef FHG_LOG
fflush(debug_sudas_LOG_PHY);
#endif
// check if we need to use PUCCH 1a/1b
ue_pucch_procedures(ue,proc,eNB_id,abstraction_flag);
// check if we need to use SRS
......@@ -4008,17 +3984,6 @@ void ue_dlsch_procedures(PHY_VARS_UE *ue,
pdsch==PDSCH?1:0,
dlsch0->harq_processes[harq_pid]->TBS>256?1:0);
if (pdsch==PDSCH) {
sudas_LOG_PHY(debug_sudas_LOG_PHY,"ret %d HARQinfo status %d round %d harq_pid %d ack %d \n", ret,dlsch0->harq_processes[harq_pid]->status,
dlsch0->harq_processes[harq_pid]->round,
dlsch0->harq_ack[subframe_rx].harq_id,
dlsch0->harq_ack[subframe_rx].ack);
#ifdef FHG_LOG
fflush(debug_sudas_LOG_PHY);
#endif
}
#if UE_TIMING_TRACE
stop_meas(&ue->dlsch_decoding_stats[ue->current_thread_id[subframe_rx]]);
#if DISABLE_LOG_X
......@@ -5364,6 +5329,8 @@ int phy_procedures_UE_RX(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,
ue_pbch_procedures(eNB_id,ue,proc,abstraction_flag);
}
// do procedures for C-RNTI
LOG_D(PHY," ------ --> PDSCH ChannelComp/LLR slot 0: AbsSubframe %d.%d ------ \n", frame_rx%1024, subframe_rx);
if (ue->dlsch[ue->current_thread_id[subframe_rx]][eNB_id][0]->active == 1) {
......@@ -5385,10 +5352,6 @@ int phy_procedures_UE_RX(PHY_VARS_UE *ue,UE_rxtx_proc_t *proc,uint8_t eNB_id,
#if UE_TIMING_TRACE
stop_meas(&ue->pdsch_procedures_stat[ue->current_thread_id[subframe_rx]]);
start_meas(&ue->dlsch_procedures_stat[ue->current_thread_id[subframe_rx]]);
#endif
sudas_LOG_PHY(debug_sudas_LOG_PHY," ------ --> PDSCH ue_dlsch_procedures AbsSubframe %d.%d ------ \n", frame_rx%1024, subframe_rx);
#ifdef FHG_LOG
fflush(debug_sudas_LOG_PHY);
#endif
ue_dlsch_procedures(ue,
proc,
......
......@@ -21,7 +21,8 @@
#define FHG_TM4_LOG_CQI
//#define FHG_LOG
#define FHG_LOG_TM4
//#define FHG_LOG_TM4
......@@ -37,7 +38,6 @@ extern FILE *debug_sudas_LOG_MAC;
#ifdef FHG_LOG
#define sudas_LOG_PHY(c,...) fprintf(c,__VA_ARGS__)
#define sudas_LOG_MAC(c,...) fprintf(c,__VA_ARGS__)
#else
......
......@@ -652,8 +652,7 @@ typedef struct {
/// Number of Allocated RBs for DL after scheduling (prior to frequency allocation)
uint16_t nb_rb[8]; // num_max_harq
//TM of allocated RBs
uint16_t Trans_Mode[8][50]; // num_max_harq
/// Number of Allocated RBs for UL after scheduling (prior to frequency allocation)
uint16_t nb_rb_ul[8]; // num_max_harq
......
This diff is collapsed.
......@@ -178,16 +178,14 @@ void assign_rbs_required (module_id_t Mod_id,
rnti_t rnti;
uint16_t TBS = 0;
int16_t N_layer=1;
LTE_eNB_UE_stats *eNB_UE_stats[MAX_NUM_CCs];
int UE_id,n,i,j,CC_id,pCCid,tmp;
UE_list_t *UE_list = &eNB_mac_inst[Mod_id].UE_list;
// UE_TEMPLATE *UE_template;
LTE_DL_FRAME_PARMS *frame_parms[MAX_NUM_CCs];
//sfn for TM4 testing
//Fraunhofer IIS: for TM4 Feedback
eNB_MAC_INST *eNB = &eNB_mac_inst[Mod_id];
int16_t N_layer=1;
// clear rb allocations across all CC_ids
for (UE_id = 0; UE_id < NUMBER_OF_UE_MAX; UE_id++) {
if (UE_list->active[UE_id] != TRUE) continue;
......@@ -247,13 +245,10 @@ void assign_rbs_required (module_id_t Mod_id,
frame_parms[CC_id] = mac_xface->get_lte_frame_parms(Mod_id,CC_id);
eNB_UE_stats[CC_id] = mac_xface->get_eNB_UE_stats(Mod_id,CC_id,rnti);
//Author: KSaaifan @ Fraunhofer IIS
// : We introduce Nl to calculate nb_rbs_req
// :
/*sfn:
* TM4
*sudas_LOG_MAC(debug_sudas_LOG_MAC,"TM %d, DL_cqi %d, rank %d;\n",PHY_vars_eNB_g[Mod_id][CC_id]->transmission_mode[UE_id],eNB_UE_stats[CC_id]->DL_cqi[0],eNB_UE_stats[CC_id]->rank);
* fflush(debug_sudas_LOG_MAC);
*sudas_LOG_MAC(debug_sudas_LOG_MAC,"TM
* */
switch(mac_xface->get_transmission_mode(Mod_id,CC_id,rnti)){
case 1:
case 2:
......@@ -261,7 +256,8 @@ void assign_rbs_required (module_id_t Mod_id,
N_layer=1;
break;
case 4:
N_layer=2;
if (eNB_UE_stats[CC_id]->rank==0) N_layer=1;
else N_layer=2;
break;
default:
N_layer=1;
......@@ -284,7 +280,10 @@ void assign_rbs_required (module_id_t Mod_id,
nb_rbs_required[CC_id][UE_id] += min_rb_unit[CC_id];
if (nb_rbs_required[CC_id][UE_id] > eNB->eNB_stats[CC_id].available_prbs) {//sfn: replace frame_parms[CC_id]->N_RB_DL
nb_rbs_required[CC_id][UE_id] = min_rb_unit[CC_id]*(eNB->eNB_stats[CC_id].available_prbs/min_rb_unit[CC_id]);
if(eNB->eNB_stats[CC_id].available_prbs==25)
nb_rbs_required[CC_id][UE_id] = eNB->eNB_stats[CC_id].available_prbs;
else
nb_rbs_required[CC_id][UE_id] = min_rb_unit[CC_id]*(eNB->eNB_stats[CC_id].available_prbs/min_rb_unit[CC_id]);
TBS = mac_xface->get_TBS_DL(eNB_UE_stats[CC_id]->dlsch_mcs1,N_layer*nb_rbs_required[CC_id][UE_id]);
break;
}
......@@ -292,7 +291,6 @@ void assign_rbs_required (module_id_t Mod_id,
TBS = mac_xface->get_TBS_DL(eNB_UE_stats[CC_id]->dlsch_mcs1,N_layer*nb_rbs_required[CC_id][UE_id]);
} // end of while
LOG_D(MAC,"[eNB %d] Frame %d: UE %d on CC %d: RB unit %d, nb_required RB %d (TBS %d, mcs %d)\n",
Mod_id, frameP,UE_id, CC_id, min_rb_unit[CC_id], nb_rbs_required[CC_id][UE_id], TBS, eNB_UE_stats[CC_id]->dlsch_mcs1);
}
......@@ -606,35 +604,6 @@ void dlsch_scheduler_pre_processor (module_id_t Mod_id,
rballoc_sub,
MIMO_mode_indicator);
//
ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
harq_pid = ue_sched_ctl->harq_pid[CC_id];
round = ue_sched_ctl->round[CC_id];
rnti = UE_RNTI(Mod_id,i);
eNB_UE_stats[CC_id] = mac_xface->get_eNB_UE_stats(Mod_id,CC_id,rnti);
PHY_vars_eNB_g[Mod_id][CC_id]->UE_stats[UE_id].rank = eNB_UE_stats[CC_id]->rank;
if (round==0)
{
/* SFN: Enable Format2 scheduling
* select TM according to rank
*
*/
if (eNB_UE_stats[CC_id]->rank)
{
PHY_vars_eNB_g[Mod_id][CC_id]->transmission_mode[UE_id]=4;
UE_list->UE_template[CC_id][UE_id].Trans_Mode[harq_pid][CC_id]=4;
}
else
{
PHY_vars_eNB_g[Mod_id][CC_id]->transmission_mode[UE_id]=2;
UE_list->UE_template[CC_id][UE_id].Trans_Mode[harq_pid][CC_id]=2;
}
}
else//Retransmission
{
PHY_vars_eNB_g[Mod_id][CC_id]->transmission_mode[UE_id]=UE_list->UE_template[CC_id][UE_id].Trans_Mode[harq_pid][CC_id];;
}
}
}
......
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