Commit bc04d720 authored by francescomani's avatar francescomani

some improvements from review

parent 842a4bbf
......@@ -1159,7 +1159,7 @@ int pnf_phy_ul_dci_req(gNB_L1_rxtx_proc_t *proc, nfapi_pnf_p7_config_t *pnf_p7,
if (req->numPdus > 0) {
for (int i=0; i<req->numPdus; i++) {
if (req->ul_dci_pdu_list[i].PDUType == 0) // only possible value 0: PDCCH PDU
if (req->ul_dci_pdu_list[i].PDUType == NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE) // only possible value 0: PDCCH PDU
msgTx->ul_pdcch_pdu[i] = req->ul_dci_pdu_list[i];
else
LOG_E(PHY,"[PNF] UL_DCI_REQ sfn_slot:%d PDU[%d] - unknown pdu type:%d\n", NFAPI_SFNSLOT2DEC(req->SFN, req->Slot), req->numPdus-1, req->ul_dci_pdu_list[req->numPdus-1].PDUType);
......@@ -1243,8 +1243,7 @@ int pnf_phy_dl_tti_req(gNB_L1_rxtx_proc_t *proc, nfapi_pnf_p7_config_t *pnf_p7,
processingData_L1tx_t *msgTx = (processingData_L1tx_t *)NotifiedFifoData(res);
if (dl_tti_pdu_list[i].PDUType == NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE) {
// we trust the scheduler sends only one PDCCH PDU per slot
msgTx->pdcch_pdu[i] = dl_tti_pdu_list[i].pdcch_pdu; // fills the last received PDCCH PDU
msgTx->pdcch_pdu[i] = dl_tti_pdu_list[i].pdcch_pdu; // copies all the received PDCCH PDUs
}
else if (dl_tti_pdu_list[i].PDUType == NFAPI_NR_DL_TTI_SSB_PDU_TYPE) {
//NFAPI_TRACE(NFAPI_TRACE_INFO, "%s() PDU:%d BCH: pdu_index:%u pdu_length:%d sdu_length:%d BCH_SDU:%x,%x,%x\n", __FUNCTION__, i, pdu_index, bch_pdu->bch_pdu_rel8.length, tx_request_pdu[sfn][sf][pdu_index]->segments[0].segment_length, sdu[0], sdu[1], sdu[2]);
......
......@@ -641,14 +641,16 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
bwpd = (void*)CellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP;
genericParameters = &scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters;
}
else
AssertFatal(1==0,"Either initial BWP or active BWP should always be present\n");
sched_ctrl->search_space = get_searchspace(scc, bwpd, target_ss);
sched_ctrl->coreset = get_coreset(Mod_idP, scc, bwpd, sched_ctrl->search_space, target_ss);
UE_info->UE_sched_ctrl[UE_id].sched_pdcch = set_pdcch_structure(RC.nrmac[Mod_idP],
sched_ctrl->search_space,
sched_ctrl->coreset,
scc,
genericParameters,
NULL);
sched_ctrl->sched_pdcch = set_pdcch_structure(RC.nrmac[Mod_idP],
sched_ctrl->search_space,
sched_ctrl->coreset,
scc,
genericParameters,
NULL);
sched_ctrl->maxL = 2;
}
}
......
......@@ -830,14 +830,15 @@ void pf_dl(module_id_t module_id,
if (ps->time_domain_allocation != tda)
nr_set_pdsch_semi_static(scc, UE_info->CellGroup[UE_id], sched_ctrl->active_bwp, bwpd, tda, f, ps);
const uint16_t slbitmap = SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols);
// Freq-demain allocation
while (rbStart < bwpSize &&
!(rballoc_mask[rbStart]&SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols)))
!(rballoc_mask[rbStart]&slbitmap))
rbStart++;
uint16_t max_rbSize = 1;
while (rbStart + max_rbSize < bwpSize &&
(rballoc_mask[rbStart + max_rbSize]&SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols)))
(rballoc_mask[rbStart + max_rbSize]&slbitmap))
max_rbSize++;
sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, ps->mcsTableIdx);
......@@ -861,7 +862,7 @@ void pf_dl(module_id_t module_id,
/* transmissions: directly allocate */
n_rb_sched -= sched_pdsch->rbSize;
for (int rb = 0; rb < sched_pdsch->rbSize; rb++)
rballoc_mask[rb + sched_pdsch->rbStart] -= SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols);
rballoc_mask[rb + sched_pdsch->rbStart] -= slbitmap;
}
}
......@@ -896,6 +897,7 @@ void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth,
MAX_BWP_SIZE);
const uint16_t slbitmap = SL_to_bitmap(startSymbolIndex, nrOfSymbols);
uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map;
uint16_t rballoc_mask[bwpSize];
int n_rb_sched = 0;
......@@ -904,8 +906,8 @@ void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
// if any RB in vrb_map is blocked (1), the current RBG will be 0
rballoc_mask[i] = (~vrb_map[i+BWPStart])&0x3fff; //bitwise not and 14 symbols
// if all the pdsch symbols are free
if((rballoc_mask[i]&SL_to_bitmap(startSymbolIndex, nrOfSymbols)) ==
SL_to_bitmap(startSymbolIndex, nrOfSymbols))
if((rballoc_mask[i]&slbitmap) ==
slbitmap)
n_rb_sched++;
}
......
......@@ -298,12 +298,12 @@ void nr_preprocessor_phytest(module_id_t module_id,
while (true) {
/* advance to first free RB */
while (rbStart < bwpSize &&
(vrb_map[rbStart + BWPStart]&(((1<<ps->nrOfSymbols)-1)<<ps->startSymbolIndex)))
(vrb_map[rbStart + BWPStart]&SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols)))
rbStart++;
rbSize = 1;
/* iterate until we are at target_dl_bw or no available RBs */
while (rbStart + rbSize < bwpSize &&
!(vrb_map[rbStart + rbSize + BWPStart]&(((1<<ps->nrOfSymbols)-1)<<ps->startSymbolIndex)) &&
!(vrb_map[rbStart + rbSize + BWPStart]&SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols)) &&
rbSize < target_dl_bw)
rbSize++;
/* found target_dl_bw? */
......
......@@ -293,6 +293,19 @@ NR_sched_pdcch_t *set_pdcch_structure(gNB_MAC_INST *gNB_mac,
}
int cce_to_reg_interleaving(const int R, int k, int n_shift, const int C, int L, const int N_regs) {
int f; // interleaving function
if(R==0)
f = k;
else {
int c = k/R;
int r = k%R;
f = (r*C + c + n_shift)%(N_regs/L);
}
return f;
}
uint8_t find_pdcch_candidate(gNB_MAC_INST *mac,
int cc_id,
int aggregation,
......@@ -310,34 +323,26 @@ uint8_t find_pdcch_candidate(gNB_MAC_INST *mac,
return -1;
}
int N_rb = pdcch->n_rb; // nb of rbs of coreset per symbol
int N_symb = coreset->duration; // nb of coreset symbols
int N_regs = N_rb*N_symb; // nb of REGs per coreset
int N_cces = N_regs / NR_NB_REG_PER_CCE; // nb of cces in coreset
int L = pdcch->RegBundleSize;
int R = pdcch->InterleaverSize;
int n_shift = pdcch->ShiftIndex;
int C = R>0 ? N_regs/(L*R) : 0;
int B_rb = L/N_symb; // nb of RBs occupied by each REG bundle
const int N_rb = pdcch->n_rb; // nb of rbs of coreset per symbol
const int N_symb = coreset->duration; // nb of coreset symbols
const int N_regs = N_rb*N_symb; // nb of REGs per coreset
const int N_cces = N_regs / NR_NB_REG_PER_CCE; // nb of cces in coreset
const int R = pdcch->InterleaverSize;
const int L = pdcch->RegBundleSize;
const int C = R>0 ? N_regs/(L*R) : 0;
const int B_rb = L/N_symb; // nb of RBs occupied by each REG bundle
int first_cce;
bool taken = false; // flag if the resource for a given candidate are taken
// loop over all the available candidates
// this implements TS 38.211 Sec. 7.3.2.2
for(int m=next_cand; m<nr_of_candidates; m++) { // loop over candidates
first_cce = aggregation * (( Y + CEILIDIV((m*N_cces),(aggregation*nr_of_candidates)) + N_ci ) % CEILIDIV(N_cces,aggregation));
for (int j=first_cce; (j<first_cce+aggregation) && !taken; j++) { // loop over CCEs
for (int k=6*j/L; (k<(6*j/L+6/L)) && !taken; k++) { // loop over REG bundles
int f; // interleaving function
if(R==0)
f = k;
else {
int c = k/R;
int r = k%R;
f = (r*C + c + n_shift)%(N_regs/L);
}
int f = cce_to_reg_interleaving(R, k, pdcch->ShiftIndex, C, L, N_regs);
for(int rb=0; rb<B_rb; rb++) { // loop over the RBs of the bundle
if(vrb_map[pdcch->BWPStart + f*B_rb + rb]&(((1<<N_symb)-1)<<pdcch->StartSymbolIndex)) {
if(vrb_map[pdcch->BWPStart + f*B_rb + rb]&SL_to_bitmap(pdcch->StartSymbolIndex,N_symb)) {
taken = true;
break;
}
......
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