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常顺宇
OpenXG-RAN
Commits
461990a1
Commit
461990a1
authored
4 years ago
by
Francesco Mani
Browse files
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changes in pucch2 indication
parent
ae0c02b2
dev
1
256_QAM_demod
512-dataplane-bug-in-l2nfapi_nos1
FR2_NSA
Fix_SA_SIB1
NR-PHY-MAC-IF-multi-UE
NRPRACH_highSpeed_saankhya
NRUE_usedlschparallel
NR_10MHz
NR_2port_CSIRS
NR_CSIRS_tomerge
NR_CSI_reporting
NR_DLUL_PF
NR_DLUL_PF_4UL
NR_DLUL_PF_rebased
NR_DL_MIMO
NR_DL_sched_fixes
NR_F1C_F1U_extensions
NR_FAPI_beamindex_SSB_RO
NR_FAPI_beamindex_SSB_RO_SEMPROJ
NR_FDD_FIX
NR_FR2_RA
NR_FR2_RRC_SSB
NR_FR2_initsync_fixes
NR_MAC_Multi_Rach_GlobalEdge
NR_MAC_Multi_Rach_GlobalEdge-old
NR_MAC_SSB
NR_MAC_SSB_RO_UE_IDCC
NR_MAC_TCI_UCI_GlobalEdge
NR_MCS_BLER
NR_PUCCH_MultiUE
NR_RA_cleanup
NR_RRCConfiguration_FR2
NR_SA_F1AP_5GRECORDS
NR_SA_F1AP_5GRECORDS-USIM
NR_SA_F1AP_5GRECORDS-wf-0623
NR_SA_F1AP_5GRECORDS_lts
NR_SA_F1AP_RFSIMULATOR
NR_SA_F1AP_RFSIMULATOR2
NR_SA_F1AP_RFSIMULATOR2_SRB
NR_SA_F1AP_RFSIMULATOR3
NR_SA_F1AP_RFSIMULATOR3_tmp
NR_SA_F1AP_RFSIMULATOR3_wf
NR_SA_F1AP_RFSIMULATOR_w5GCN
NR_SA_F1AP_dev
NR_SA_NGAP_RRC_wk42
NR_SA_itti_sim_wk48
NR_SA_itti_sim_wk48_hs
NR_SA_itti_sim_wk48_hs1
NR_SA_w5GCN_new_gtpu
NR_SCHED_HARQ
NR_SCHED_PDCCH_PUCCH_HARQ
NR_SCHED_PDCCH_PUCCH_HARQ_rebased
NR_SCHED_fixes
NR_SRB_Config
NR_UE_CONFIG_REQ_FIXES
NR_UE_PUCCH_bugfixes
NR_UE_SA
NR_UE_dlsch_bugfix
NR_UE_enable_parallelization
NR_UE_rework_test
NR_UE_reworking_UCI_procedures
NR_UE_stability_fixes
NR_UL_SCFDMA_100MHz
NR_UL_scheduler
NR_UL_scheduler_rebased
NR_Wireshark
NR_beam_simulation
NR_cleanup_PUCCH_resources
NR_gNB_initial_MIB_fix
NR_mac_uci_functions_rework
NR_multiplexing_HARQ_CSI_PUCCH
NR_phytest_bugfixes
NR_reworking_UL_antennaports
NR_scheduling_CSIRS
NR_scheduling_request
NR_scheduling_request2
NR_scheduling_request3
PBCHNRTCFIX
RFquality
Saankhya_NRPRACH_HighSpeed
Test_SA_5GREC
add-dmrs-test
add-ru-docker-image
avxllr
bandwidth-testing
bch-fixes-bitmap
benetel_config_file_fix
benetel_dpdk20
benetel_driver_uldl_pf_merge
benetel_driver_update
benetel_fixes
benetel_phase_rotation
bsr-fix
bugfix-free-ra-process
bugfix-nr-ldpc-post-processing
bugfix-nr-ldpc-size-typo
bugfix-nr-pdcp-sn-size
bugfix-nr-rate-matching-assertion
bugfix-nr-t-reordering
bugfix-x2-SgNBAdditionRequest
bugfix_gnb_rt_stats_html
bupt-sa-merge
ci-deploy-asterix
ci-deploy-docker-compose
ci-fix-module-ul-iperf
ci-new-docker-pipeline
ci-reduce-nb-vms
ci-test
ci-ul-iperf-from-trf-container
ci_benetel_longrun_limits
ci_benetel_test
ci_fix_iperf_for_module
ci_hotfix_module_ue_ip_address
ci_improve_module_ctl
ci_nsa_benetel
ci_nsa_fixes
ci_nsa_pipes_improve
ci_nsa_test_integration_2021_wk19
ci_nsa_traces
ci_nsa_uplink
ci_phytest
ci_quectel_support
ci_sa_rfsim_test
ci_solve_ul_for_module
ci_test_5GREC
ci_test_nsa_fix_quectel_nic
ci_test_nsa_on_develop
ci_test_ra_fr2
ci_testinfra_as_code
ci_vm_resource_fix
cleanup_softmodem_main
constant_power
debug-UL-5GRECORDS
debug_UL_signal
detached-w16-test
develop
develop-CBRA-v3
develop-CCE
develop-NR_SA_F1AP_5GRECORDS
develop-NR_SA_F1AP_5GRECORDS-abs
develop-NR_SA_F1AP_5GRECORDS-hs
develop-NR_SA_F1AP_5GRECORDS-hs1
develop-NR_SA_F1AP_5GRECORDS-lts
develop-NR_SA_F1AP_5GRECORDS-lts-wf
develop-NR_SA_F1AP_5GRECORDS-v3
develop-NR_SA_F1AP_5GRECORDS_100M
develop-NR_SA_F1AP_5GRECORDS_LDPC_FPGA
develop-NR_SA_F1AP_5GRECORDS_lfq_0607
develop-SA-CBRA
develop-SA-CBRA-CUDU
develop-SA-CBRA-Msg5
develop-SA-CBRA-lts
develop-SA-CBRA-ulsch-lts
develop-SA-RA
develop-SnT
develop-aw2sori
develop-oriecpriupdates
develop-sib1
develop-sib1-local
develop-sib1-lts
develop-sib1-update
develop-sib1-update-test1
develop-sib1-update-ue
develop-wf-du
develop_stable
disable_CSI_measrep
dlsch_parallel
docker-improvements-2021-april
docker-no-cache-option
dongzhanyi-zte-develop1
dongzhanyi-zte-develop2
enhance-rfsim
episys-merge
episys/nsa_baseline
episys/nsa_development
feature/make-s1-mme-port-configurable
feature/make-s1-mme-port-configurable-with-astyle-fixes
fedora-gen-kernel-fix
fft_bench_hotfix
fix-check
fix-ci-tun
fix-compile
fix-itti-segv
fix-nr-pdcp-timer
fix-nr-rlc-range-nack
fix-physim-deploy
fix-quectel
fix-realtime
fix-retransmission-rbg
fix-x2-without-gnb
fix_NR_DLUL_PF
fix_NR_DLUL_PF_benchmark
fix_coreset_dmrs_idx
fix_do_ra_data
fix_nr_ulsim
fix_pdsch_low_prb
fix_rb_corruption
fix_reestablishment
fixes-CE-RLC-PDU-size
fixgtpu
flexran-repair-mme-mgmt
flexran-rtc-repo-is-public
fujitsu_lte_contribution
git-dashboard
gnb-freerun-txru
gnb-n300-fixes
gnb-only-test
gnb-realtime-hotfix
gnb-realtime-quickfix
gnb-threadpool
hack-bch-no-sched-sf-0
hack-exit-gnb-when-no-enb-nsa
harq-hotfix
hotfix-minor-remove-nr-rlc-cppcheck-error
hotfix-nr-rlc-tick
integ-w13-test-rt-issue
integration_2020_wk15
integration_2020_wk45
integration_2020_wk45_2
integration_2020_wk46
integration_2020_wk46_2
integration_2020_wk47
integration_2020_wk48
integration_2020_wk48_2
integration_2020_wk49
integration_2020_wk50
integration_2020_wk50_1
integration_2020_wk51
integration_2020_wk51_2
integration_2021_wk02
integration_2021_wk02_wMR988
integration_2021_wk04
integration_2021_wk05
integration_2021_wk06
integration_2021_wk06_MR978
integration_2021_wk06_b
integration_2021_wk06_c
integration_2021_wk08
integration_2021_wk08_2
integration_2021_wk08_MR963
integration_2021_wk09
integration_2021_wk09_b
integration_2021_wk10
integration_2021_wk10_b
integration_2021_wk11
integration_2021_wk12
integration_2021_wk12_b
integration_2021_wk13_a
integration_2021_wk13_b
integration_2021_wk13_b_fix_tdas
integration_2021_wk13_b_fixed
integration_2021_wk13_c
integration_2021_wk14_a
integration_2021_wk15_a
integration_2021_wk16
integration_2021_wk17_a
integration_2021_wk17_b
integration_2021_wk18_a
integration_2021_wk18_b
integration_2021_wk19
integration_2021_wk20_a
integration_2021_wk22
integration_2021_wk23
integration_2021_wk27
integration_w5GC_CBRA_test
inter-RRU-final
itti-enhancement
ldpc_offload_t1
ldpc_short_codeword_fixes
lte-ulsch-bugfix
lte_uplink_improvement
mac-fixes-wk45_2
migrate-cpp-check-container
migrate-vm-pipeline-to-bionic
minor-fix-doc-basic-sim
mosaic5g-oai-ran
mosaic5g-oai-sim
msg4_phy_0303_lfq
multiple_ssb_sib1_bugfix
nasmesh_kernel_5.8
new-gtpu
nfapi_nr_arch_mod
nfapi_nr_develop
nfapi_nr_develop_new
ngap-dlul
ngap-wf
ngap-wf-1120
ngap-wf-1120-srb
ngap-wf-1120-srb-gtp
ngap-wf-1120-srb-gtp-hs
ngap-wf-1120-srb-gtp-hs1
ngap-wf-1120-srb-gtp-hs2
ngap-wf-1120-srb-gtp-yhz
ngap-wf-1203-yunsdr
ngap-wf-liuyu
ngap_lfq_1120
ngap_merge
noCore
nr-bsr-fix
nr-dl-mimo-2layer
nr-dmrs-fixes
nr-pdcp-benchmarking
nr-pdcp-improvements
nr-pdcp-nea2-security
nr-pdcp-nia2-integrity
nr-pdcp-small-bugfixes
nr-pdcp-srb-integrity
nr-ra-fix
nr-rlc-am-bugfix-w44
nr-stats-print
nrPBCHTCFix
nrPbchTcFix
nrUE
nrUE-hs
nrUE-upper-layer
nr_bsr
nr_dl_dmrs_type2
nr_dl_pf
nr_dl_pf2
nr_dl_ul_ptrs
nr_fdd_if_fix
nr_improve_chanest
nr_power_measurement_fixes
nr_prach_fr2
nr_ue_pdcp_fix
nr_ue_tti_cleanup
nr_ul_pf
nr_ul_scfdma
oai-sim
oairu
oairu-dockerfile-support
oc-docker-october-improvements
openxg/develop
phy-asan-fixes
physim-build-deploy
physim-deploy-handle-error-cases
prb_based_dl_channel_estimation
ptrs_rrc_config
pusch-mthread-scaling-fix
pusch-retrans-fix-ue
ra-dl-ul
recursive-cmake
remove_nos1_hack_pdcp
remove_x2_gnb_hardcoding
repair-TA
rh-ci-add-ue-parallelization
rh_ci_add_runtime_stats
rh_ci_add_uldlharq_stats
rh_ci_fix_autoterminate
rh_ci_fr1_update
rh_ci_gsheet_rt_monitoring
rh_ci_nsa2jenkins
rh_ci_nsa_test_n310
rh_ci_phy_test_improve
rh_ci_ra_fr2
rh_ci_test_benetel
rh_ci_test_nsa
rh_ci_test_nsa_wk16
rh_ci_test_nsa_wk17_b
rh_ci_test_nsa_wk17b
rh_ci_test_rfsim_sa
rh_ci_ue_parallel
rh_fr1_newjenkins
rh_fr1_update
rh_gnb_compile_fix
rh_wk50_debug
rlc-v2-bugfix-status-reporting
rlc-v2-tick
rohan_ulsim2RxFix
rrc-enb-phy-testmode
s1-subnormal_rewrite
s1_subnormal
s1_subnormal-robert
s1ap-bugfix-rab_setup
sa-demo
sa-demo-hs
sa-merge-rrc-srb
sa-msg4
sa-msg4-rrc
sa-msg4-rrc-yihz
sa-msg4-rrc-yihz-hs
sa_rrc_yihz
sanitize-address
sanitize-v1
sanitize-v1-tmp
sarma_pvnp_oai
scs_60_iisc
sim-channels
small-config-change
small_nr_bugfixes
t-gnb-tracer
test-5GREC
test-nsa-benetel
test-panos
test_nsa_gtpu_fix
test_rt-fix_phy-test
ue-dci-false-detection
ue-fixes
ue-pdsch-pusch-parallel
ue-race-fix
ue_beam_selection
ul-freq-iq-samps-to-file
usrp_stop_cleanly
usrp_x400
wf-sa-rrc
wf_testc
wireshark-T-hack-ueid
wireshark-log-scheduling-requests
wk11-with-phytest
x2_handle_sctp_shutdown
xiangwab
xiangwan
xw2
yihongzheng_srb
2021.wk14_a
2021.wk13_d
2021.wk13_c
2021.w27
2021.w26
2021.w25
2021.w24
2021.w23
2021.w22
2021.w20
2021.w19
2021.w18_b
2021.w18_a
2021.w17_b
2021.w16
2021.w15
2021.w14
2021.w13_a
2021.w12
2021.w11
2021.w10
2021.w09
2021.w08
2021.w06
2021.w05
2021.w04
2021.w02
2020.w51_2
2020.w51
2020.w50
2020.w49
2020.w48_2
2020.w48
2020.w47
2020.w46_2
2020.w46
2020.w45_2
2020.w45
2020.w44
benetel_phase_rotation
benetel_gnb_rel_2.0
benetel_gnb_rel_1.0
benetel_enb_rel_2.0
benetel_enb_rel_1.0
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1 changed file
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17 additions
and
10 deletions
+17
-10
openair1/PHY/NR_TRANSPORT/pucch_rx.c
openair1/PHY/NR_TRANSPORT/pucch_rx.c
+17
-10
No files found.
openair1/PHY/NR_TRANSPORT/pucch_rx.c
View file @
461990a1
...
...
@@ -394,7 +394,7 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB,
// first bit of bitmap for sr presence and second bit for acknack presence
uci_pdu
->
pduBitmap
=
pucch_pdu
->
sr_flag
|
((
pucch_pdu
->
bit_len_harq
>
0
)
<<
1
);
uci_pdu
->
pucch_format
=
0
;
// format 0
uci_pdu
->
ul_cqi
=
cqi
;
// currently not valid
uci_pdu
->
ul_cqi
=
cqi
;
uci_pdu
->
timing_advance
=
0xffff
;
// currently not valid
uci_pdu
->
rssi
=
1280
-
(
10
*
dB_fixed
(
32767
*
32767
)
-
dB_fixed_times10
(
signal_energy
(
&
rxdataF
[
0
][
pucch_pdu
->
start_symbol_index
*
frame_parms
->
ofdm_symbol_size
+
re_offset
],
12
)));
if
(
pucch_pdu
->
bit_len_harq
==
0
)
{
...
...
@@ -1494,7 +1494,7 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB,
}
}
// cw loop
corr_dB
=
dB_fixed64
((
uint64_t
)
corr
);
LOG_
D
(
PHY
,
"cw_ML %d, metric %d dB
\n
"
,
cw_ML
,
corr_dB
);
LOG_
I
(
PHY
,
"cw_ML %d, metric %d dB
\n
"
,
cw_ML
,
corr_dB
);
decodedPayload
[
0
]
=
(
uint64_t
)
cw_ML
;
}
else
{
// polar coded case
...
...
@@ -1629,21 +1629,29 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB,
corr_dB
=
dB_fixed64
(
corr
);
LOG_D
(
PHY
,
"metric %d dB
\n
"
,
corr_dB
);
}
re_offset
=
(
12
*
pucch_pdu
->
prb_start
)
+
(
12
*
pucch_pdu
->
bwp_start
)
+
frame_parms
->
first_carrier_offset
;
// estimate CQI for MAC (from antenna port 0 only)
int
SNRtimes10
=
dB_fixed_times10
(
signal_energy
(
&
rxdataF
[
0
][(
l2
*
frame_parms
->
ofdm_symbol_size
)
+
re_offset
],
12
*
pucch_pdu
->
prb_size
))
-
(
10
*
gNB
->
measurements
.
n0_power_tot_dB
);
int
cqi
;
if
(
SNRtimes10
<
-
640
)
cqi
=
0
;
else
if
(
SNRtimes10
>
635
)
cqi
=
255
;
else
cqi
=
(
640
+
SNRtimes10
)
/
5
;
uci_pdu
->
harq
.
harq_bit_len
=
pucch_pdu
->
bit_len_harq
;
uci_pdu
->
pduBitmap
=
0
;
uci_pdu
->
rnti
=
pucch_pdu
->
rnti
;
uci_pdu
->
handle
=
pucch_pdu
->
handle
;
uci_pdu
->
pucch_format
=
0
;
uci_pdu
->
ul_cqi
=
corr_dB
;
// need to fill these field!
uci_pdu
->
timing_advance
=
31
;
uci_pdu
->
rssi
=
0
;
uci_pdu
->
ul_cqi
=
cqi
;
uci_pdu
->
timing_advance
=
0xffff
;
// currently not valid
uci_pdu
->
rssi
=
1280
-
(
10
*
dB_fixed
(
32767
*
32767
)
-
dB_fixed_times10
(
signal_energy
(
&
rxdataF
[
0
][(
l2
*
frame_parms
->
ofdm_symbol_size
)
+
re_offset
],
12
*
pucch_pdu
->
prb_size
)));
if
(
pucch_pdu
->
bit_len_harq
>
0
)
{
int
harq_bytes
=
pucch_pdu
->
bit_len_harq
>>
3
;
if
((
pucch_pdu
->
bit_len_harq
&
7
)
>
0
)
harq_bytes
++
;
uci_pdu
->
pduBitmap
|=
1
;
uci_pdu
->
harq
.
harq_payload
=
(
uint8_t
*
)
malloc
(
harq_bytes
);
uci_pdu
->
harq
.
harq_crc
=
decoderState
>
0
?
1
:
0
;
uci_pdu
->
harq
.
harq_crc
=
decoderState
;
int
i
=
0
;
for
(;
i
<
harq_bytes
-
1
;
i
++
)
{
uci_pdu
->
harq
.
harq_payload
[
i
]
=
decodedPayload
[
0
]
&
255
;
...
...
@@ -1666,19 +1674,18 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB,
int
csi_part1_bytes
=
pucch_pdu
->
bit_len_csi_part1
>>
3
;
if
((
pucch_pdu
->
bit_len_csi_part1
&
7
)
>
0
)
csi_part1_bytes
++
;
uci_pdu
->
csi_part1
.
csi_part1_payload
=
(
uint8_t
*
)
malloc
(
csi_part1_bytes
);
uci_pdu
->
csi_part1
.
csi_part1_crc
=
decoderState
>
0
?
1
:
0
;
uci_pdu
->
csi_part1
.
csi_part1_crc
=
decoderState
;
int
i
=
0
;
for
(;
i
<
csi_part1_bytes
-
1
;
i
++
)
{
uci_pdu
->
csi_part1
.
csi_part1_payload
[
i
]
=
decodedPayload
[
0
]
&
255
;
decodedPayload
[
0
]
>>=
8
;
}
uci_pdu
->
csi_part1
.
csi_part1_payload
[
i
]
=
decodedPayload
[
0
]
&
((
1
<<
(
pucch_pdu
->
bit_len_csi_part1
&
7
))
-
1
);
decodedPayload
[
0
]
>>=
pucch_pdu
->
bit_len_csi_part1
;
decodedPayload
[
0
]
>>=
pucch_pdu
->
bit_len_csi_part1
;
}
if
(
pucch_pdu
->
bit_len_csi_part2
>
0
)
{
uci_pdu
->
pduBitmap
|=
8
;
}
}
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