Commit 8d3fa4dc authored by Robert Schmidt's avatar Robert Schmidt

Simplify dlsch_scheduler_pre_processor_reset()

The original reset() function used in fairRR has been moved to
eNB_scheduler_fairRR.c
parent ff766786
dev 1 128-ues 256_QAM_demod 512-dataplane-bug-in-l2nfapi_nos1 FR2_NSA Fix_SA_SIB1 LTE_TRX_on_single_port NCTU_OpinConnect_LDPC NR-PHY-MAC-IF-multi-UE NRPRACH_highSpeed_saankhya NRUE_usedlschparallel NR_10MHz NR_2port_CSIRS NR_CSIRS_tomerge NR_CSI_reporting NR_DCI_01 NR_DLUL_PF NR_DLUL_PF_4UL NR_DLUL_PF_rebased NR_DL_MIMO NR_DL_sched_fixes NR_DL_scheduler NR_F1C_F1U_extensions NR_FAPI_beamindex_SSB_RO NR_FAPI_beamindex_SSB_RO_SEMPROJ NR_FDD_FIX NR_FR2_RA NR_FR2_RRC_SSB NR_FR2_initsync_fixes NR_MAC_CE_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge-old NR_MAC_SSB NR_MAC_SSB_RO_GlobalEdge NR_MAC_SSB_RO_UE_IDCC NR_MAC_SSB_RO_merge NR_MAC_TCI_UCI_GlobalEdge NR_MCS_BLER NR_NGAP NR_PUCCH_MultiUE NR_RA_cleanup NR_RA_updates NR_RRCConfiguration_FR2 NR_RRC_PDCP NR_RRC_PRACH_procedures NR_RRC_X2AP_AMBR_Change_Global_edge NR_RRC_X2AP_RemoveHardcodings_GlobalEdge NR_RRC_config_simplified NR_RRC_harq_b NR_SA_F1AP_5GRECORDS NR_SA_F1AP_5GRECORDS-USIM NR_SA_F1AP_5GRECORDS-wf-0623 NR_SA_F1AP_5GRECORDS_lts NR_SA_F1AP_RFSIMULATOR NR_SA_F1AP_RFSIMULATOR2 NR_SA_F1AP_RFSIMULATOR2_SRB NR_SA_F1AP_RFSIMULATOR3 NR_SA_F1AP_RFSIMULATOR3_tmp NR_SA_F1AP_RFSIMULATOR3_wf NR_SA_F1AP_RFSIMULATOR_w5GCN NR_SA_F1AP_dev NR_SA_NGAP_RRC NR_SA_NGAP_RRC_wk42 NR_SA_itti_sim_wk48 NR_SA_itti_sim_wk48_hs NR_SA_itti_sim_wk48_hs1 NR_SA_w5GCN_new_gtpu NR_SCHED_HARQ NR_SCHED_PDCCH_PUCCH_HARQ NR_SCHED_PDCCH_PUCCH_HARQ_rebased NR_SCHED_fixes NR_SRB_Config NR_TRX_on_single_port2 NR_UE_CONFIG_REQ_FIXES NR_UE_MAC_scheduler NR_UE_PUCCH_bugfixes NR_UE_RA_fixes NR_UE_SA NR_UE_UL_DCI_improvements NR_UE_dlsch_bugfix NR_UE_enable_parallelization NR_UE_rework_test NR_UE_reworking_UCI_procedures NR_UE_stability_fixes NR_UL_FAPI_programming NR_UL_SCFDMA_100MHz NR_UL_scheduler NR_UL_scheduler_rebased NR_UL_scheduling NR_Wireshark NR_beam_simulation NR_cleanup_PUCCH_resources NR_gNB_initial_MIB_fix NR_ipaccess_testing NR_mac_uci_functions_rework NR_msg2_phytest NR_multiplexing_HARQ_CSI_PUCCH NR_phytest_bugfixes NR_reworking_UL_antennaports NR_scheduling_CSIRS NR_scheduling_request NR_scheduling_request2 NR_scheduling_request3 NR_ue_dlsch_dmrs_cdm PBCHNRTCFIX PUSCH_TA_update RA_CI_test RFquality Saankhya_NRPRACH_HighSpeed Test_SA_5GREC UE_DL_DCI_hotfix add-dmrs-test add-ru-docker-image avxllr bandwidth-testing bch-fixes-bitmap benetel_5g_prach_fix benetel_config_file_fix benetel_dpdk20 benetel_driver_uldl_pf_merge benetel_driver_update benetel_fixes benetel_phase_rotation benetel_phase_rotation_old bsr-fix bugfix-free-ra-process bugfix-minor-remove-wrong-log bugfix-nr-bands bugfix-nr-ldpc-post-processing bugfix-nr-ldpc-size-typo bugfix-nr-pdcp-sn-size bugfix-nr-rate-matching-assertion bugfix-nr-t-reordering bugfix-x2-SgNBAdditionRequest bugfix_gnb_rt_stats_html bupt-sa-merge cce_indexing_fix cce_indexing_fix2 ci-deploy-asterix ci-deploy-docker-compose ci-fix-module-ul-iperf ci-new-docker-pipeline ci-rd-july-improvements ci-reduce-nb-vms ci-test ci-ul-iperf-from-trf-container ci_benetel_longrun_limits ci_benetel_test ci_fix_iperf_for_module ci_hotfix_module_ue_ip_address ci_improve_module_ctl ci_nsa_benetel ci_nsa_fixes ci_nsa_pipes_improve ci_nsa_test_integration_2021_wk19 ci_nsa_traces ci_nsa_uplink ci_phytest ci_quectel_support ci_sa_rfsim_test ci_solve_ul_for_module ci_test_5GREC ci_test_nsa_fix_quectel_nic ci_test_nsa_on_develop ci_test_ra_fr2 ci_testinfra_as_code ci_vm_resource_fix clean-5G-scope-round2 cleanup_softmodem_main constant_power debug-UL-5GRECORDS debug_UL_signal detached-w16-test develop develop-CBRA-v3 develop-CCE develop-NR_SA_F1AP_5GRECORDS develop-NR_SA_F1AP_5GRECORDS-abs develop-NR_SA_F1AP_5GRECORDS-hs develop-NR_SA_F1AP_5GRECORDS-hs1 develop-NR_SA_F1AP_5GRECORDS-lts develop-NR_SA_F1AP_5GRECORDS-lts-wf develop-NR_SA_F1AP_5GRECORDS-v3 develop-NR_SA_F1AP_5GRECORDS_100M develop-NR_SA_F1AP_5GRECORDS_LDPC_FPGA develop-NR_SA_F1AP_5GRECORDS_lfq_0607 develop-SA-CBRA develop-SA-CBRA-CUDU develop-SA-CBRA-Msg5 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integration_2020_wk47 integration_2020_wk48 integration_2020_wk48_2 integration_2020_wk49 integration_2020_wk50 integration_2020_wk50_1 integration_2020_wk51 integration_2020_wk51_2 integration_2021_wk02 integration_2021_wk02_wMR988 integration_2021_wk04 integration_2021_wk05 integration_2021_wk06 integration_2021_wk06_MR978 integration_2021_wk06_b integration_2021_wk06_c integration_2021_wk08 integration_2021_wk08_2 integration_2021_wk08_MR963 integration_2021_wk09 integration_2021_wk09_b integration_2021_wk10 integration_2021_wk10_b integration_2021_wk11 integration_2021_wk12 integration_2021_wk12_b integration_2021_wk13_a integration_2021_wk13_b integration_2021_wk13_b_fix_tdas integration_2021_wk13_b_fixed integration_2021_wk13_c integration_2021_wk14_a integration_2021_wk15_a integration_2021_wk16 integration_2021_wk17_a integration_2021_wk17_b integration_2021_wk18_a integration_2021_wk18_b integration_2021_wk19 integration_2021_wk20_a integration_2021_wk22 integration_2021_wk23 integration_2021_wk27 integration_w5GC_CBRA_test inter-RRU-final inter-RRU-oairu inter-rru-UE itti-enhancement ldpc-decoder-codegen ldpc-decoder-codegen2 ldpc-offload ldpc_offload_t1 ldpc_short_codeword_fixes load_gnb lte-ulsch-bugfix lte_uplink_improvement mac-fixes-wk45_2 migrate-cpp-check-container migrate-vm-pipeline-to-bionic minor-fix-doc-basic-sim mosaic5g-oai-ran mosaic5g-oai-sim msg4_phy_0303_lfq multiple_ssb_sib1_bugfix nasmesh_kernel_5.8 new-gtpu new_rlc_2020 nfapi-bugfix nfapi_nr_arch_mod nfapi_nr_develop nfapi_nr_develop_new ngap-dlul ngap-support ngap-w48-merge2 ngap-wf ngap-wf-1120 ngap-wf-1120-srb ngap-wf-1120-srb-gtp ngap-wf-1120-srb-gtp-hs ngap-wf-1120-srb-gtp-hs1 ngap-wf-1120-srb-gtp-hs2 ngap-wf-1120-srb-gtp-yhz ngap-wf-1203-yunsdr ngap-wf-liuyu ngap_lfq_1120 ngap_merge noCore nr-bsr-fix nr-dl-mimo-2layer nr-dmrs-fixes nr-mac-pdu-wireshark nr-mac-remove-ue-list nr-pdcp-benchmarking nr-pdcp-improvements nr-pdcp-nea2-security nr-pdcp-nia2-integrity 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ue-race-fix ue_beam_selection ue_nfapi_mch ul-freq-iq-samps-to-file ul_dl_dci_same_slot ul_harq ulsch_decode_mthread ulsim_changes usrp_fix_adc_shift_and_pps_sync usrp_stop_cleanly usrp_x400 wf-sa-rrc wf_testc wireshark-T-hack-ueid wireshark-log-scheduling-requests wk11-with-phytest x2-endc-processing x2_handle_sctp_shutdown xiangwab xiangwan xw2 yihongzheng_srb zzs 2021.wk14_a 2021.wk13_d 2021.wk13_c 2021.w27 2021.w26 2021.w25 2021.w24 2021.w23 2021.w22 2021.w20 2021.w19 2021.w18_b 2021.w18_a 2021.w17_b 2021.w16 2021.w15 2021.w14 2021.w13_a 2021.w12 2021.w11 2021.w10 2021.w09 2021.w08 2021.w06 2021.w05 2021.w04 2021.w02 2020.w51_2 2020.w51 2020.w50 2020.w49 2020.w48_2 2020.w48 2020.w47 2020.w46_2 2020.w46 2020.w45_2 2020.w45 2020.w44 2020.w42_2 2020.w42 2020.w41 2020.w39 2020.w38 2020.w37 2020.w36 2020.w34 2020.w33 2020.w31 2020.w30 2020.w29 2020.w28 2020.w26 2020.w25 2020.w24 2020.w23 2020.w22 2020.w19 2020.w17 2020.w16 2020.w15 benetel_phase_rotation benetel_gnb_rel_2.0 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...@@ -558,6 +558,174 @@ void dlsch_scheduler_pre_ue_select_fairRR( ...@@ -558,6 +558,174 @@ void dlsch_scheduler_pre_ue_select_fairRR(
return; return;
} }
void dlsch_scheduler_pre_processor_reset_fairRR(
module_id_t module_idP,
frame_t frameP,
sub_frame_t subframeP,
int min_rb_unit[NFAPI_CC_MAX],
uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB],
uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX],
uint8_t MIMO_mode_indicator[NFAPI_CC_MAX][N_RBG_MAX]) {
int UE_id;
uint8_t CC_id;
int i, j;
UE_list_t *UE_list;
UE_sched_ctrl_t *ue_sched_ctl;
int N_RB_DL, RBGsize, RBGsize_last;
int N_RBG[NFAPI_CC_MAX];
rnti_t rnti;
uint8_t *vrb_map;
COMMON_channels_t *cc;
//
for (CC_id = 0; CC_id < RC.nb_mac_CC[module_idP]; CC_id++) {
// initialize harq_pid and round
cc = &RC.mac[module_idP]->common_channels[CC_id];
N_RBG[CC_id] = to_rbg(cc->mib->message.dl_Bandwidth);
min_rb_unit[CC_id] = get_min_rb_unit(module_idP, CC_id);
for (UE_id = 0; UE_id < MAX_MOBILES_PER_ENB; ++UE_id) {
UE_list = &RC.mac[module_idP]->UE_list;
ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
rnti = UE_RNTI(module_idP, UE_id);
if (rnti == NOT_A_RNTI)
continue;
if (UE_list->active[UE_id] != TRUE)
continue;
LOG_D(MAC, "Running preprocessor for UE %d (%x)\n", UE_id, rnti);
// initialize harq_pid and round
if (ue_sched_ctl->ta_timer)
ue_sched_ctl->ta_timer--;
/*
eNB_UE_stats *eNB_UE_stats;
if (eNB_UE_stats == NULL)
return;
mac_xface->get_ue_active_harq_pid(module_idP,CC_id,rnti,
frameP,subframeP,
&ue_sched_ctl->harq_pid[CC_id],
&ue_sched_ctl->round[CC_id],
openair_harq_DL);
if (ue_sched_ctl->ta_timer == 0) {
// WE SHOULD PROTECT the eNB_UE_stats with a mutex here ...
ue_sched_ctl->ta_timer = 20; // wait 20 subframes before taking TA measurement from PHY
switch (N_RB_DL) {
case 6:
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update;
break;
case 15:
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/2;
break;
case 25:
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/4;
break;
case 50:
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/8;
break;
case 75:
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/12;
break;
case 100:
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/16;
break;
}
// clear the update in case PHY does not have a new measurement after timer expiry
eNB_UE_stats->timing_advance_update = 0;
}
else {
ue_sched_ctl->ta_timer--;
ue_sched_ctl->ta_update =0; // don't trigger a timing advance command
}
if (UE_id==0) {
VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_UE0_TIMING_ADVANCE,ue_sched_ctl->ta_update);
}
*/
nb_rbs_required[CC_id][UE_id] = 0;
ue_sched_ctl->pre_nb_available_rbs[CC_id] = 0;
ue_sched_ctl->dl_pow_off[CC_id] = 2;
for (i = 0; i < N_RBG[CC_id]; i++) {
ue_sched_ctl->rballoc_sub_UE[CC_id][i] = 0;
}
}
N_RB_DL = to_prb(RC.mac[module_idP]->common_channels[CC_id].mib->message.dl_Bandwidth);
switch (N_RB_DL) {
case 6:
RBGsize = 1;
RBGsize_last = 1;
break;
case 15:
RBGsize = 2;
RBGsize_last = 1;
break;
case 25:
RBGsize = 2;
RBGsize_last = 1;
break;
case 50:
RBGsize = 3;
RBGsize_last = 2;
break;
case 75:
RBGsize = 4;
RBGsize_last = 3;
break;
case 100:
RBGsize = 4;
RBGsize_last = 4;
break;
default:
AssertFatal(1 == 0, "unsupported RBs (%d)\n", N_RB_DL);
}
vrb_map = RC.mac[module_idP]->common_channels[CC_id].vrb_map;
// Initialize Subbands according to VRB map
for (i = 0; i < N_RBG[CC_id]; i++) {
int rb_size = i == N_RBG[CC_id] - 1 ? RBGsize_last : RBGsize;
// for SI-RNTI,RA-RNTI and P-RNTI allocations
for (j = 0; j < rb_size; j++) {
if (vrb_map[j + (i*RBGsize)] != 0) {
rballoc_sub[CC_id][i] = 1;
LOG_D(MAC, "Frame %d, subframe %d : vrb %d allocated\n", frameP, subframeP, j + (i*RBGsize));
break;
}
}
//LOG_D(MAC, "Frame %d Subframe %d CC_id %d RBG %i : rb_alloc %d\n",
//frameP, subframeP, CC_id, i, rballoc_sub[CC_id][i]);
MIMO_mode_indicator[CC_id][i] = 2;
}
}
}
// This function assigns pre-available RBS to each UE in specified sub-bands before scheduling is done // This function assigns pre-available RBS to each UE in specified sub-bands before scheduling is done
...@@ -612,14 +780,14 @@ void dlsch_scheduler_pre_processor_fairRR (module_id_t Mod_id, ...@@ -612,14 +780,14 @@ void dlsch_scheduler_pre_processor_fairRR (module_id_t Mod_id,
UE_id = i; UE_id = i;
// Initialize scheduling information for all active UEs // Initialize scheduling information for all active UEs
dlsch_scheduler_pre_processor_reset(Mod_id, dlsch_scheduler_pre_processor_reset_fairRR(
0, Mod_id,
frameP, frameP,
subframeP, subframeP,
min_rb_unit, min_rb_unit,
(uint16_t (*)[MAX_MOBILES_PER_ENB])nb_rbs_required, (uint16_t(*)[MAX_MOBILES_PER_ENB])nb_rbs_required,
rballoc_sub, rballoc_sub,
MIMO_mode_indicator); MIMO_mode_indicator);
} }
} }
......
...@@ -85,6 +85,15 @@ void dlsch_scheduler_pre_ue_select_fairRR( ...@@ -85,6 +85,15 @@ void dlsch_scheduler_pre_ue_select_fairRR(
uint16_t nb_rbs_required[MAX_NUM_CCs][MAX_MOBILES_PER_ENB], uint16_t nb_rbs_required[MAX_NUM_CCs][MAX_MOBILES_PER_ENB],
DLSCH_UE_SELECT dlsch_ue_select[MAX_NUM_CCs]); DLSCH_UE_SELECT dlsch_ue_select[MAX_NUM_CCs]);
void dlsch_scheduler_pre_processor_reset_fairRR(
module_id_t module_idP,
frame_t frameP,
sub_frame_t subframeP,
int min_rb_unit[NFAPI_CC_MAX],
uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB],
uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX],
uint8_t MIMO_mode_indicator[NFAPI_CC_MAX][N_RBG_MAX]);
void dlsch_scheduler_pre_processor_fairRR (module_id_t Mod_id, void dlsch_scheduler_pre_processor_fairRR (module_id_t Mod_id,
frame_t frameP, frame_t frameP,
sub_frame_t subframeP, sub_frame_t subframeP,
......
...@@ -237,13 +237,8 @@ void dlsch_scheduler_pre_processor(module_id_t module_idP, ...@@ -237,13 +237,8 @@ void dlsch_scheduler_pre_processor(module_id_t module_idP,
sub_frame_t subframe); sub_frame_t subframe);
void dlsch_scheduler_pre_processor_reset(module_id_t module_idP, void dlsch_scheduler_pre_processor_reset(module_id_t module_idP,
int slice_idx, int CC_id,
frame_t frameP, uint8_t rballoc_sub[N_RBG_MAX]);
sub_frame_t subframeP,
int min_rb_unit[NFAPI_CC_MAX],
uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB],
uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX],
uint8_t MIMO_mode_indicator[NFAPI_CC_MAX][N_RBG_MAX]);
void dlsch_scheduler_pre_processor_partitioning(module_id_t Mod_id, void dlsch_scheduler_pre_processor_partitioning(module_id_t Mod_id,
int slice_idx, int slice_idx,
......
...@@ -886,6 +886,8 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, ...@@ -886,6 +886,8 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
uint16_t i, j; uint16_t i, j;
int slice_idx = 0; int slice_idx = 0;
int min_rb_unit[NFAPI_CC_MAX]; int min_rb_unit[NFAPI_CC_MAX];
min_rb_unit[CC_id] = get_min_rb_unit(Mod_id, CC_id);
// TODO: remove NFAPI_CC_MAX, here for compatibility for the moment
uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX]; uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX];
memset(rballoc_sub, 0, sizeof(rballoc_sub)); memset(rballoc_sub, 0, sizeof(rballoc_sub));
...@@ -894,21 +896,18 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, ...@@ -894,21 +896,18 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
uint16_t (*nb_rbs_required)[MAX_MOBILES_PER_ENB] = sli->pre_processor_results[slice_idx].nb_rbs_required; uint16_t (*nb_rbs_required)[MAX_MOBILES_PER_ENB] = sli->pre_processor_results[slice_idx].nb_rbs_required;
uint16_t (*nb_rbs_accounted)[MAX_MOBILES_PER_ENB] = sli->pre_processor_results[slice_idx].nb_rbs_accounted; uint16_t (*nb_rbs_accounted)[MAX_MOBILES_PER_ENB] = sli->pre_processor_results[slice_idx].nb_rbs_accounted;
uint16_t (*nb_rbs_remaining)[MAX_MOBILES_PER_ENB] = sli->pre_processor_results[slice_idx].nb_rbs_remaining; uint16_t (*nb_rbs_remaining)[MAX_MOBILES_PER_ENB] = sli->pre_processor_results[slice_idx].nb_rbs_remaining;
uint8_t (*MIMO_mode_indicator)[N_RBG_MAX] = sli->pre_processor_results[slice_idx].MIMO_mode_indicator; // TODO remove this
uint8_t MIMO_mode_indicator[NFAPI_CC_MAX][N_RBG_MAX];
memset(MIMO_mode_indicator, 0, sizeof(MIMO_mode_indicator));
UE_list_t *UE_list = &eNB->UE_list; UE_list_t *UE_list = &eNB->UE_list;
UE_sched_ctrl_t *ue_sched_ctl; UE_sched_ctrl_t *ue_sched_ctl;
// int rrc_status = RRC_IDLE;
// Initialize scheduling information for all active UEs // Initialize scheduling information for all active UEs
memset(&sli->pre_processor_results[slice_idx], 0, sizeof(sli->pre_processor_results[slice_idx])); memset(&sli->pre_processor_results[slice_idx], 0, sizeof(sli->pre_processor_results[slice_idx]));
// FIXME: After the memset above, some of the resets in reset() are redundant
dlsch_scheduler_pre_processor_reset(Mod_id, dlsch_scheduler_pre_processor_reset(Mod_id,
slice_idx, CC_id,
frameP, rballoc_sub[CC_id]);
subframeP,
min_rb_unit,
nb_rbs_required,
rballoc_sub,
MIMO_mode_indicator);
// STATUS // STATUS
// Store the DLSCH buffer for each logical channel // Store the DLSCH buffer for each logical channel
store_dlsch_buffer(Mod_id, store_dlsch_buffer(Mod_id,
...@@ -999,173 +998,41 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, ...@@ -999,173 +998,41 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
void void
dlsch_scheduler_pre_processor_reset(module_id_t module_idP, dlsch_scheduler_pre_processor_reset(module_id_t module_idP,
int slice_idx, int CC_id,
frame_t frameP, uint8_t rballoc_sub[N_RBG_MAX]) {
sub_frame_t subframeP, UE_list_t *UE_list = &RC.mac[module_idP]->UE_list;
int min_rb_unit[NFAPI_CC_MAX],
uint16_t nb_rbs_required[NFAPI_CC_MAX][MAX_MOBILES_PER_ENB],
uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX],
uint8_t MIMO_mode_indicator[NFAPI_CC_MAX][N_RBG_MAX]) {
int UE_id;
uint8_t CC_id;
int i, j;
UE_list_t *UE_list;
UE_sched_ctrl_t *ue_sched_ctl;
int N_RB_DL, RBGsize, RBGsize_last;
int N_RBG[NFAPI_CC_MAX];
rnti_t rnti;
uint8_t *vrb_map;
COMMON_channels_t *cc;
//
for (CC_id = 0; CC_id < RC.nb_mac_CC[module_idP]; CC_id++) {
// initialize harq_pid and round
cc = &RC.mac[module_idP]->common_channels[CC_id];
N_RBG[CC_id] = to_rbg(cc->mib->message.dl_Bandwidth);
min_rb_unit[CC_id] = get_min_rb_unit(module_idP, CC_id);
for (UE_id = 0; UE_id < MAX_MOBILES_PER_ENB; ++UE_id) {
UE_list = &RC.mac[module_idP]->UE_list;
ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
rnti = UE_RNTI(module_idP, UE_id);
if (rnti == NOT_A_RNTI)
continue;
if (UE_list->active[UE_id] != TRUE)
continue;
if (!ue_dl_slice_membership(module_idP, UE_id, slice_idx))
continue;
LOG_D(MAC, "Running preprocessor for UE %d (%x)\n", UE_id, rnti);
// initialize harq_pid and round
if (ue_sched_ctl->ta_timer)
ue_sched_ctl->ta_timer--;
/*
eNB_UE_stats *eNB_UE_stats;
if (eNB_UE_stats == NULL)
return;
mac_xface->get_ue_active_harq_pid(module_idP,CC_id,rnti,
frameP,subframeP,
&ue_sched_ctl->harq_pid[CC_id],
&ue_sched_ctl->round[CC_id],
openair_harq_DL);
if (ue_sched_ctl->ta_timer == 0) {
// WE SHOULD PROTECT the eNB_UE_stats with a mutex here ...
ue_sched_ctl->ta_timer = 20; // wait 20 subframes before taking TA measurement from PHY
switch (N_RB_DL) {
case 6:
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update;
break;
case 15:
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/2;
break;
case 25:
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/4;
break;
case 50:
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/8;
break;
case 75:
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/12;
break;
case 100:
ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/16;
break;
}
// clear the update in case PHY does not have a new measurement after timer expiry
eNB_UE_stats->timing_advance_update = 0;
}
else {
ue_sched_ctl->ta_timer--;
ue_sched_ctl->ta_update =0; // don't trigger a timing advance command
}
if (UE_id==0) {
VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_UE0_TIMING_ADVANCE,ue_sched_ctl->ta_update);
}
*/
nb_rbs_required[CC_id][UE_id] = 0;
ue_sched_ctl->pre_nb_available_rbs[CC_id] = 0;
ue_sched_ctl->dl_pow_off[CC_id] = 2;
for (i = 0; i < N_RBG[CC_id]; i++) {
ue_sched_ctl->rballoc_sub_UE[CC_id][i] = 0;
}
}
N_RB_DL = to_prb(RC.mac[module_idP]->common_channels[CC_id].mib->message.dl_Bandwidth);
switch (N_RB_DL) {
case 6:
RBGsize = 1;
RBGsize_last = 1;
break;
case 15: for (int UE_id = 0; UE_id < MAX_MOBILES_PER_ENB; ++UE_id) {
RBGsize = 2; UE_sched_ctrl_t *ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
RBGsize_last = 1; const rnti_t rnti = UE_RNTI(module_idP, UE_id);
break;
case 25: if (rnti == NOT_A_RNTI)
RBGsize = 2; continue;
RBGsize_last = 1;
break;
case 50: if (UE_list->active[UE_id] != TRUE)
RBGsize = 3; continue;
RBGsize_last = 2;
break;
case 75: // initialize harq_pid and round
RBGsize = 4; if (ue_sched_ctl->ta_timer)
RBGsize_last = 3; ue_sched_ctl->ta_timer--;
break;
case 100: ue_sched_ctl->pre_nb_available_rbs[CC_id] = 0;
RBGsize = 4; ue_sched_ctl->dl_pow_off[CC_id] = 2;
RBGsize_last = 4;
break;
default: for (int i = 0; i < sizeof(ue_sched_ctl->rballoc_sub_UE[CC_id])/sizeof(unsigned char); i++) {
AssertFatal(1 == 0, "unsupported RBs (%d)\n", N_RB_DL); ue_sched_ctl->rballoc_sub_UE[CC_id][i] = 0;
} }
}
vrb_map = RC.mac[module_idP]->common_channels[CC_id].vrb_map; const int N_RB_DL = to_prb(RC.mac[module_idP]->common_channels[CC_id].mib->message.dl_Bandwidth);
const int RBGsize = get_min_rb_unit(module_idP, CC_id);
// Initialize Subbands according to VRB map const uint8_t *vrb_map = RC.mac[module_idP]->common_channels[CC_id].vrb_map;
for (i = 0; i < N_RBG[CC_id]; i++) {
int rb_size = i == N_RBG[CC_id] - 1 ? RBGsize_last : RBGsize;
// for SI-RNTI,RA-RNTI and P-RNTI allocations // Check for SI-RNTI, RA-RNTI or P-RNTI allocations in VRB map and
for (j = 0; j < rb_size; j++) { // initialize subbands accordly
if (vrb_map[j + (i*RBGsize)] != 0) { for (int i = 0; i < N_RB_DL; i++) {
rballoc_sub[CC_id][i] = 1; if (vrb_map[i] != 0)
LOG_D(MAC, "Frame %d, subframe %d : vrb %d allocated\n", frameP, subframeP, j + (i*RBGsize)); rballoc_sub[i/RBGsize] = 1;
break;
}
}
//LOG_D(MAC, "Frame %d Subframe %d CC_id %d RBG %i : rb_alloc %d\n",
//frameP, subframeP, CC_id, i, rballoc_sub[CC_id][i]);
MIMO_mode_indicator[CC_id][i] = 2;
}
} }
} }
......
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