Commit 3d10b9fc authored by francescomani's avatar francescomani

symbol-wise vrb map occupation for dl

parent 99250c95
...@@ -1144,13 +1144,19 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra ...@@ -1144,13 +1144,19 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
BWPSize = type0_PDCCH_CSS_config->num_rbs; BWPSize = type0_PDCCH_CSS_config->num_rbs;
} }
// Calculate number of symbols
int startSymbolIndex, nrOfSymbols;
const int startSymbolAndLength = pdsch_TimeDomainAllocationList->list.array[time_domain_assignment]->startSymbolAndLength;
SLIV2SL(startSymbolAndLength, &startSymbolIndex, &nrOfSymbols);
AssertFatal(startSymbolIndex >= 0, "StartSymbolIndex is negative\n");
coreset = get_coreset(module_idP, scc, bwp, ss, NR_SearchSpace__searchSpaceType_PR_common); coreset = get_coreset(module_idP, scc, bwp, ss, NR_SearchSpace__searchSpaceType_PR_common);
AssertFatal(coreset!=NULL,"Coreset cannot be null for RA-Msg2\n"); AssertFatal(coreset!=NULL,"Coreset cannot be null for RA-Msg2\n");
uint16_t *vrb_map = cc[CC_id].vrb_map; uint16_t *vrb_map = cc[CC_id].vrb_map;
for (int i = 0; (i < rbSize) && (rbStart <= (BWPSize - rbSize)); i++) { for (int i = 0; (i < rbSize) && (rbStart <= (BWPSize - rbSize)); i++) {
if (vrb_map[BWPStart + rbStart + i]) { if (vrb_map[BWPStart + rbStart + i]&(((1<<nrOfSymbols)-1)<<startSymbolIndex)) {
rbStart += i; rbStart += i;
i = 0; i = 0;
} }
...@@ -1182,12 +1188,6 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra ...@@ -1182,12 +1188,6 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
return; return;
} }
// Calculate number of symbols
int startSymbolIndex, nrOfSymbols;
const int startSymbolAndLength = pdsch_TimeDomainAllocationList->list.array[time_domain_assignment]->startSymbolAndLength;
SLIV2SL(startSymbolAndLength, &startSymbolIndex, &nrOfSymbols);
AssertFatal(startSymbolIndex >= 0, "StartSymbolIndex is negative\n");
LOG_D(NR_MAC,"Msg2 startSymbolIndex.nrOfSymbols %d.%d\n",startSymbolIndex,nrOfSymbols); LOG_D(NR_MAC,"Msg2 startSymbolIndex.nrOfSymbols %d.%d\n",startSymbolIndex,nrOfSymbols);
int mappingtype = pdsch_TimeDomainAllocationList->list.array[time_domain_assignment]->mappingType; int mappingtype = pdsch_TimeDomainAllocationList->list.array[time_domain_assignment]->mappingType;
...@@ -1362,9 +1362,9 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra ...@@ -1362,9 +1362,9 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
nr_mac->TX_req[CC_id].Number_of_PDUs++; nr_mac->TX_req[CC_id].Number_of_PDUs++;
nr_mac->TX_req[CC_id].Slot = slotP; nr_mac->TX_req[CC_id].Slot = slotP;
// Mark the corresponding RBs as used // Mark the corresponding symbols RBs as used
for (int rb = 0; rb < rbSize; rb++) { for (int rb = 0; rb < rbSize; rb++) {
vrb_map[BWPStart + rb + rbStart] = 1; vrb_map[BWPStart + rb + rbStart] = ((1<<nrOfSymbols)-1)<<startSymbolIndex;
} }
ra->state = WAIT_Msg3; ra->state = WAIT_Msg3;
...@@ -1547,7 +1547,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra ...@@ -1547,7 +1547,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
int i = 0; int i = 0;
while ((i < rbSize) && (rbStart + rbSize <= BWPSize)) { while ((i < rbSize) && (rbStart + rbSize <= BWPSize)) {
if (vrb_map[BWPStart + rbStart + i]) { if (vrb_map[BWPStart + rbStart + i]&(((1<<nrOfSymbols)-1)<<startSymbolIndex)) {
rbStart += i+1; rbStart += i+1;
i = 0; i = 0;
} else { } else {
...@@ -1721,9 +1721,9 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra ...@@ -1721,9 +1721,9 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
nr_mac->TX_req[CC_id].Number_of_PDUs++; nr_mac->TX_req[CC_id].Number_of_PDUs++;
nr_mac->TX_req[CC_id].Slot = slotP; nr_mac->TX_req[CC_id].Slot = slotP;
// Mark the corresponding RBs as used // Mark the corresponding symbols and RBs as used
for (int rb = 0; rb < pdsch_pdu_rel15->rbSize; rb++) { for (int rb = 0; rb < pdsch_pdu_rel15->rbSize; rb++) {
vrb_map[BWPStart + rb + pdsch_pdu_rel15->rbStart] = 1; vrb_map[BWPStart + rb + pdsch_pdu_rel15->rbStart] = ((1<<nrOfSymbols)-1)<<startSymbolIndex;
} }
LOG_D(NR_MAC,"BWPSize: %i\n", pdcch_pdu_rel15->BWPSize); LOG_D(NR_MAC,"BWPSize: %i\n", pdcch_pdu_rel15->BWPSize);
......
...@@ -384,7 +384,7 @@ uint32_t schedule_control_sib1(module_id_t module_id, ...@@ -384,7 +384,7 @@ uint32_t schedule_control_sib1(module_id_t module_id,
int rbSize = 0; int rbSize = 0;
uint32_t TBS = 0; uint32_t TBS = 0;
do { do {
if(rbSize < bwpSize && !vrb_map[rbStart + rbSize]) if(rbSize < bwpSize && !(vrb_map[rbStart + rbSize]&(((1<<nrOfSymbols)-1)<<startSymbolIndex)))
rbSize++; rbSize++;
else{ else{
if (gNB_mac->sched_ctrlCommon->sched_pdsch.mcs<10) if (gNB_mac->sched_ctrlCommon->sched_pdsch.mcs<10)
...@@ -411,10 +411,9 @@ uint32_t schedule_control_sib1(module_id_t module_id, ...@@ -411,10 +411,9 @@ uint32_t schedule_control_sib1(module_id_t module_id,
LOG_D(MAC,"dmrs_length %d\n",dmrs_length); LOG_D(MAC,"dmrs_length %d\n",dmrs_length);
LOG_D(MAC,"N_PRB_DMRS = %d\n",N_PRB_DMRS); LOG_D(MAC,"N_PRB_DMRS = %d\n",N_PRB_DMRS);
LOG_D(MAC,"mappingtype = %d\n", mappingtype); LOG_D(MAC,"mappingtype = %d\n", mappingtype);
// Mark the corresponding RBs as used // Mark the corresponding RBs as used
for (int rb = 0; rb < gNB_mac->sched_ctrlCommon->sched_pdsch.rbSize; rb++) { for (int rb = 0; rb < gNB_mac->sched_ctrlCommon->sched_pdsch.rbSize; rb++) {
vrb_map[rb + rbStart] = 1; vrb_map[rb + rbStart] = ((1<<nrOfSymbols)-1)<<startSymbolIndex;
} }
return TBS; return TBS;
} }
......
...@@ -531,7 +531,7 @@ void nr_store_dlsch_buffer(module_id_t module_id, ...@@ -531,7 +531,7 @@ void nr_store_dlsch_buffer(module_id_t module_id,
bool allocate_dl_retransmission(module_id_t module_id, bool allocate_dl_retransmission(module_id_t module_id,
frame_t frame, frame_t frame,
sub_frame_t slot, sub_frame_t slot,
uint8_t *rballoc_mask, uint16_t *rballoc_mask,
int *n_rb_sched, int *n_rb_sched,
int UE_id, int UE_id,
int current_harq_pid) { int current_harq_pid) {
...@@ -561,13 +561,16 @@ bool allocate_dl_retransmission(module_id_t module_id, ...@@ -561,13 +561,16 @@ bool allocate_dl_retransmission(module_id_t module_id,
while (rbSize < retInfo->rbSize) { while (rbSize < retInfo->rbSize) {
rbStart += rbSize; /* last iteration rbSize was not enough, skip it */ rbStart += rbSize; /* last iteration rbSize was not enough, skip it */
rbSize = 0; rbSize = 0;
while (rbStart < bwpSize && !rballoc_mask[rbStart]) while (rbStart < bwpSize &&
!(rballoc_mask[rbStart]&(((1<<ps->nrOfSymbols)-1)<<ps->startSymbolIndex)))
rbStart++; rbStart++;
if (rbStart >= bwpSize) { if (rbStart >= bwpSize) {
LOG_D(NR_MAC, "cannot allocate retransmission for UE %d/RNTI %04x: no resources\n", UE_id, UE_info->rnti[UE_id]); LOG_D(NR_MAC, "cannot allocate retransmission for UE %d/RNTI %04x: no resources\n", UE_id, UE_info->rnti[UE_id]);
return false; return false;
} }
while (rbStart + rbSize < bwpSize && rballoc_mask[rbStart + rbSize] && rbSize < retInfo->rbSize) while (rbStart + rbSize < bwpSize &&
(rballoc_mask[rbStart + rbSize]&(((1<<ps->nrOfSymbols)-1)<<ps->startSymbolIndex)) &&
rbSize < retInfo->rbSize)
rbSize++; rbSize++;
} }
/* check whether we need to switch the TDA allocation since the last /* check whether we need to switch the TDA allocation since the last
...@@ -577,13 +580,15 @@ bool allocate_dl_retransmission(module_id_t module_id, ...@@ -577,13 +580,15 @@ bool allocate_dl_retransmission(module_id_t module_id,
} else { } else {
/* the retransmission will use a different time domain allocation, check /* the retransmission will use a different time domain allocation, check
* that we have enough resources */ * that we have enough resources */
while (rbStart < bwpSize && !rballoc_mask[rbStart])
rbStart++;
while (rbStart + rbSize < bwpSize && rballoc_mask[rbStart + rbSize])
rbSize++;
NR_pdsch_semi_static_t temp_ps; NR_pdsch_semi_static_t temp_ps;
temp_ps.nrOfLayers = 1; temp_ps.nrOfLayers = 1;
nr_set_pdsch_semi_static(scc, cg, sched_ctrl->active_bwp, bwpd, tda, f, &temp_ps); nr_set_pdsch_semi_static(scc, cg, sched_ctrl->active_bwp, bwpd, tda, f, &temp_ps);
while (rbStart < bwpSize &&
!(rballoc_mask[rbStart]&(((1<<ps->nrOfSymbols)-1)<<ps->startSymbolIndex)))
rbStart++;
while (rbStart + rbSize < bwpSize &&
(rballoc_mask[rbStart + rbSize]&(((1<<ps->nrOfSymbols)-1)<<ps->startSymbolIndex)))
rbSize++;
uint32_t new_tbs; uint32_t new_tbs;
uint16_t new_rbSize; uint16_t new_rbSize;
bool success = nr_find_nb_rb(retInfo->Qm, bool success = nr_find_nb_rb(retInfo->Qm,
...@@ -642,7 +647,7 @@ bool allocate_dl_retransmission(module_id_t module_id, ...@@ -642,7 +647,7 @@ bool allocate_dl_retransmission(module_id_t module_id,
/* retransmissions: directly allocate */ /* retransmissions: directly allocate */
*n_rb_sched -= sched_ctrl->sched_pdsch.rbSize; *n_rb_sched -= sched_ctrl->sched_pdsch.rbSize;
for (int rb = 0; rb < sched_ctrl->sched_pdsch.rbSize; rb++) for (int rb = 0; rb < sched_ctrl->sched_pdsch.rbSize; rb++)
rballoc_mask[rb + sched_ctrl->sched_pdsch.rbStart] = 0; rballoc_mask[rb + sched_ctrl->sched_pdsch.rbStart] -= (((1<<ps->nrOfSymbols)-1)<<ps->startSymbolIndex);
return true; return true;
} }
...@@ -655,7 +660,7 @@ void pf_dl(module_id_t module_id, ...@@ -655,7 +660,7 @@ void pf_dl(module_id_t module_id,
NR_list_t *UE_list, NR_list_t *UE_list,
int max_num_ue, int max_num_ue,
int n_rb_sched, int n_rb_sched,
uint8_t *rballoc_mask) { uint16_t *rballoc_mask) {
gNB_MAC_INST *mac = RC.nrmac[module_id]; gNB_MAC_INST *mac = RC.nrmac[module_id];
NR_UE_info_t *UE_info = &mac->UE_info; NR_UE_info_t *UE_info = &mac->UE_info;
...@@ -769,13 +774,6 @@ void pf_dl(module_id_t module_id, ...@@ -769,13 +774,6 @@ void pf_dl(module_id_t module_id,
return; return;
} }
// Freq-demain allocation
while (rbStart < bwpSize && !rballoc_mask[rbStart]) rbStart++;
uint16_t max_rbSize = 1;
while (rbStart + max_rbSize < bwpSize && rballoc_mask[rbStart + max_rbSize])
max_rbSize++;
/* MCS has been set above */ /* MCS has been set above */
const int tda = RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0][slot]; const int tda = RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0][slot];
...@@ -785,6 +783,17 @@ void pf_dl(module_id_t module_id, ...@@ -785,6 +783,17 @@ void pf_dl(module_id_t module_id,
const long f = (sched_ctrl->active_bwp || bwpd) ? sched_ctrl->search_space->searchSpaceType->choice.ue_Specific->dci_Formats : 0; const long f = (sched_ctrl->active_bwp || bwpd) ? sched_ctrl->search_space->searchSpaceType->choice.ue_Specific->dci_Formats : 0;
if (ps->time_domain_allocation != tda) if (ps->time_domain_allocation != tda)
nr_set_pdsch_semi_static(scc, UE_info->CellGroup[UE_id], sched_ctrl->active_bwp, bwpd, tda, f, ps); nr_set_pdsch_semi_static(scc, UE_info->CellGroup[UE_id], sched_ctrl->active_bwp, bwpd, tda, f, ps);
// Freq-demain allocation
while (rbStart < bwpSize &&
!(rballoc_mask[rbStart]&(((1<<ps->nrOfSymbols)-1)<<ps->startSymbolIndex)))
rbStart++;
uint16_t max_rbSize = 1;
while (rbStart + max_rbSize < bwpSize &&
(rballoc_mask[rbStart + max_rbSize]&(((1<<ps->nrOfSymbols)-1)<<ps->startSymbolIndex)))
max_rbSize++;
sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, ps->mcsTableIdx); sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, ps->mcsTableIdx);
sched_pdsch->R = nr_get_code_rate_dl(sched_pdsch->mcs, ps->mcsTableIdx); sched_pdsch->R = nr_get_code_rate_dl(sched_pdsch->mcs, ps->mcsTableIdx);
sched_pdsch->pucch_allocation = alloc; sched_pdsch->pucch_allocation = alloc;
...@@ -806,7 +815,7 @@ void pf_dl(module_id_t module_id, ...@@ -806,7 +815,7 @@ void pf_dl(module_id_t module_id,
/* transmissions: directly allocate */ /* transmissions: directly allocate */
n_rb_sched -= sched_pdsch->rbSize; n_rb_sched -= sched_pdsch->rbSize;
for (int rb = 0; rb < sched_pdsch->rbSize; rb++) for (int rb = 0; rb < sched_pdsch->rbSize; rb++)
rballoc_mask[rb + sched_pdsch->rbStart] = 0; rballoc_mask[rb + sched_pdsch->rbStart] -= (((1<<ps->nrOfSymbols)-1)<<ps->startSymbolIndex);
} }
} }
...@@ -819,9 +828,18 @@ void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t ...@@ -819,9 +828,18 @@ void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
NR_ServingCellConfigCommon_t *scc = RC.nrmac[module_id]->common_channels[0].ServingCellConfigCommon; NR_ServingCellConfigCommon_t *scc = RC.nrmac[module_id]->common_channels[0].ServingCellConfigCommon;
const int CC_id = 0; const int CC_id = 0;
/* Get bwpSize from the first UE */ /* Get bwpSize and TDAfrom the first UE */
/* This is temporary and it assumes all UEs have the same BWP and TDA*/
int UE_id = UE_info->list.head; int UE_id = UE_info->list.head;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
const int tda = RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0][slot];
int startSymbolIndex, nrOfSymbols;
const struct NR_PDSCH_TimeDomainResourceAllocationList *tdaList = sched_ctrl->active_bwp ?
sched_ctrl->active_bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList :
scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList;
AssertFatal(tda < tdaList->list.count, "time_domain_allocation %d>=%d\n", tda, tdaList->list.count);
const int startSymbolAndLength = tdaList->list.array[tda]->startSymbolAndLength;
SLIV2SL(startSymbolAndLength, &startSymbolIndex, &nrOfSymbols);
const uint16_t bwpSize = NRRIV2BW(sched_ctrl->active_bwp ? const uint16_t bwpSize = NRRIV2BW(sched_ctrl->active_bwp ?
sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth: sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth:
...@@ -833,13 +851,16 @@ void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t ...@@ -833,13 +851,16 @@ void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
MAX_BWP_SIZE); MAX_BWP_SIZE);
uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map; uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map;
uint8_t rballoc_mask[bwpSize]; uint16_t rballoc_mask[bwpSize];
int n_rb_sched = 0; int n_rb_sched = 0;
for (int i = 0; i < bwpSize; i++) { for (int i = 0; i < bwpSize; i++) {
// calculate mask: init with "NOT" vrb_map: // calculate mask: init with "NOT" vrb_map:
// if any RB in vrb_map is blocked (1), the current RBG will be 0 // if any RB in vrb_map is blocked (1), the current RBG will be 0
rballoc_mask[i] = !vrb_map[i+BWPStart]; rballoc_mask[i] = (~vrb_map[i+BWPStart])&0x3fff; //bitwise not and 14 symbols
n_rb_sched += rballoc_mask[i]; // if all the pdsch symbols are free
if((rballoc_mask[i]&(((1<<nrOfSymbols)-1)<<startSymbolIndex)) ==
((1<<nrOfSymbols)-1)<<startSymbolIndex)
n_rb_sched++;
} }
/* Retrieve amount of data to send for this UE */ /* Retrieve amount of data to send for this UE */
......
...@@ -278,6 +278,14 @@ void nr_preprocessor_phytest(module_id_t module_id, ...@@ -278,6 +278,14 @@ void nr_preprocessor_phytest(module_id_t module_id,
__func__, __func__,
UE_id); UE_id);
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id]; NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
const int tda = sched_ctrl->active_bwp ? RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp->bwp_Id][slot] : 1;
const long f = sched_ctrl->active_bwp ? sched_ctrl->search_space->searchSpaceType->choice.ue_Specific->dci_Formats : 0;
NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
ps->nrOfLayers = target_dl_Nl;
if (ps->time_domain_allocation != tda)
nr_set_pdsch_semi_static(
scc, UE_info->CellGroup[UE_id], sched_ctrl->active_bwp, NULL, tda, f, ps);
/* find largest unallocated chunk */ /* find largest unallocated chunk */
const int bwpSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE); const int bwpSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
const int BWPStart = NRRIV2PRBOFFSET(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE); const int BWPStart = NRRIV2PRBOFFSET(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
...@@ -289,11 +297,14 @@ void nr_preprocessor_phytest(module_id_t module_id, ...@@ -289,11 +297,14 @@ void nr_preprocessor_phytest(module_id_t module_id,
/* loop ensures that we allocate exactly target_dl_bw, or return */ /* loop ensures that we allocate exactly target_dl_bw, or return */
while (true) { while (true) {
/* advance to first free RB */ /* advance to first free RB */
while (rbStart < bwpSize && vrb_map[rbStart + BWPStart]) while (rbStart < bwpSize &&
(vrb_map[rbStart + BWPStart]&(((1<<ps->nrOfSymbols)-1)<<ps->startSymbolIndex)))
rbStart++; rbStart++;
rbSize = 1; rbSize = 1;
/* iterate until we are at target_dl_bw or no available RBs */ /* iterate until we are at target_dl_bw or no available RBs */
while (rbStart + rbSize < bwpSize && !vrb_map[rbStart + rbSize + BWPStart] && rbSize < target_dl_bw) while (rbStart + rbSize < bwpSize &&
!(vrb_map[rbStart + rbSize + BWPStart]&(((1<<ps->nrOfSymbols)-1)<<ps->startSymbolIndex)) &&
rbSize < target_dl_bw)
rbSize++; rbSize++;
/* found target_dl_bw? */ /* found target_dl_bw? */
if (rbSize == target_dl_bw) if (rbSize == target_dl_bw)
...@@ -369,16 +380,9 @@ void nr_preprocessor_phytest(module_id_t module_id, ...@@ -369,16 +380,9 @@ void nr_preprocessor_phytest(module_id_t module_id,
// rnti, frame, slot); // rnti, frame, slot);
NR_sched_pdsch_t *sched_pdsch = &sched_ctrl->sched_pdsch; NR_sched_pdsch_t *sched_pdsch = &sched_ctrl->sched_pdsch;
NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
sched_pdsch->pucch_allocation = alloc; sched_pdsch->pucch_allocation = alloc;
sched_pdsch->rbStart = rbStart; sched_pdsch->rbStart = rbStart;
sched_pdsch->rbSize = rbSize; sched_pdsch->rbSize = rbSize;
const int tda = sched_ctrl->active_bwp ? RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp->bwp_Id][slot] : 1;
const long f = sched_ctrl->active_bwp ? sched_ctrl->search_space->searchSpaceType->choice.ue_Specific->dci_Formats : 0;
ps->nrOfLayers = target_dl_Nl;
if (ps->time_domain_allocation != tda)
nr_set_pdsch_semi_static(
scc, UE_info->CellGroup[UE_id], sched_ctrl->active_bwp, NULL, tda, f, ps);
sched_pdsch->mcs = target_dl_mcs; sched_pdsch->mcs = target_dl_mcs;
sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, ps->mcsTableIdx); sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, ps->mcsTableIdx);
...@@ -398,7 +402,7 @@ void nr_preprocessor_phytest(module_id_t module_id, ...@@ -398,7 +402,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
/* mark the corresponding RBs as used */ /* mark the corresponding RBs as used */
for (int rb = 0; rb < sched_pdsch->rbSize; rb++) for (int rb = 0; rb < sched_pdsch->rbSize; rb++)
vrb_map[rb + sched_pdsch->rbStart + BWPStart] = 1; vrb_map[rb + sched_pdsch->rbStart + BWPStart] = ((1<<ps->nrOfSymbols)-1)<<ps->startSymbolIndex;
if ((frame&127) == 0) LOG_D(MAC,"phytest: %d.%d DL mcs %d, DL rbStart %d, DL rbSize %d\n", frame, slot, sched_pdsch->mcs, rbStart,rbSize); if ((frame&127) == 0) LOG_D(MAC,"phytest: %d.%d DL mcs %d, DL rbStart %d, DL rbSize %d\n", frame, slot, sched_pdsch->mcs, rbStart,rbSize);
} }
......
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