uint8_tcarrier_ind;// 1 CARRIER_IND: 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213]
uint8_tsul_ind_0_1;// 2 SUL_IND_0_1:
uint8_tslot_format_ind;// 3 SLOT_FORMAT_IND: size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213]
uint8_tpre_emption_ind;// 4 PRE_EMPTION_IND: size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits
uint8_tblock_number;// 5 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3
uint8_ttime_dom_resource_assignment;// 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
// where I the number of entries in the higher layer parameter pusch-AllocationList
uint8_tvrb_to_prb_mapping;// 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
uint8_tprb_bundling_size_ind;// 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214]
uint8_trate_matching_ind;// 15 RATE_MATCHING_IND: 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set
uint8_tzp_csi_rs_trigger;// 16 ZP_CSI_RS_TRIGGER:
uint8_tfreq_hopping_flag;// 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
uint8_tdai;// 28 DAI: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
// 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI
// 0 otherwise
uint8_tfirst_dai;// 29 FIRST_DAI: (1 or 2 bits) 1 bit for semi-static HARQ-ACK
uint8_tsecond_dai;// 30 SECOND_DAI: (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks
uint8_ttci;// 39 TCI: 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits
uint8_tsrs_request;// 40 SRS_REQUEST:
uint8_ttpc_cmd;// 41 TPC_CMD:
uint8_tcsi_request;// 42 CSI_REQUEST:
uint8_tcbgti;// 43 CBGTI: 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH
uint8_tcbgfi;// 44 CBGFI: 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator
uint8_tptrs_dmrs;// 45 PTRS_DMRS:
uint8_tbeta_offset_ind;// 46 BETA_OFFSET_IND:
uint8_tdmrs_seq_ini;// 47 DMRS_SEQ_INI: 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding
// is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise
uint8_tul_sch_ind;// 48 UL_SCH_IND: value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH
uint16_tpadding_nr_dci;// 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
// and if the number of information bits in the DCI format 0_0 prior to padding
// is less than the payload size of the DCI format 1_0 monitored in common search space
// zeros shall be appended to the DCI format 0_0
// until the payload size equals that of the DCI format 1_0
uint8_tcarrier_ind;// 1 CARRIER_IND: 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213]
uint8_tsul_ind_0_1;// 2 SUL_IND_0_1:
uint8_tslot_format_ind;// 3 SLOT_FORMAT_IND: size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213]
uint8_tpre_emption_ind;// 4 PRE_EMPTION_IND: size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits
uint8_tblock_number;// 5 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3
uint8_ttime_dom_resource_assignment;// 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
// where I the number of entries in the higher layer parameter pusch-AllocationList
uint8_tvrb_to_prb_mapping;// 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
uint8_tprb_bundling_size_ind;// 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214]
uint8_trate_matching_ind;// 15 RATE_MATCHING_IND: 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set
uint8_tzp_csi_rs_trigger;// 16 ZP_CSI_RS_TRIGGER:
uint8_tfreq_hopping_flag;// 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
uint8_tdai;// 28 DAI: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
// 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI
// 0 otherwise
uint8_tfirst_dai;// 29 FIRST_DAI: (1 or 2 bits) 1 bit for semi-static HARQ-ACK
uint8_tsecond_dai;// 30 SECOND_DAI: (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks
uint8_ttci;// 39 TCI: 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits
uint8_tsrs_request;// 40 SRS_REQUEST:
uint8_ttpc_cmd;// 41 TPC_CMD:
uint8_tcsi_request;// 42 CSI_REQUEST:
uint8_tcbgti;// 43 CBGTI: 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH
uint8_tcbgfi;// 44 CBGFI: 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator
uint8_tptrs_dmrs;// 45 PTRS_DMRS:
uint8_tbeta_offset_ind;// 46 BETA_OFFSET_IND:
uint8_tdmrs_seq_ini;// 47 DMRS_SEQ_INI: 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding
// is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise
uint8_tul_sch_ind;// 48 UL_SCH_IND: value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH
uint16_tpadding_nr_dci;// 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
// and if the number of information bits in the DCI format 0_0 prior to padding
// is less than the payload size of the DCI format 1_0 monitored in common search space
// zeros shall be appended to the DCI format 0_0
// until the payload size equals that of the DCI format 1_0
uint8_tsul_ind_0_0;// 50 SUL_IND_0_0:
uint8_tra_preamble_index;// 51 RA_PREAMBLE_INDEX:
uint8_tsul_ind_1_0;// 52 SUL_IND_1_0:
uint8_tss_pbch_index;// 53 SS_PBCH_INDEX
uint8_tprach_mask_index;// 54 PRACH_MASK_INDEX
uint8_treserved_nr_dci;// 55 RESERVED_NR_DCI
}nr_dci_pdu_rel15_t;
// The PRACH Config period is a series of selected slots in one or multiple frames