Commit 9b54d47f authored by francescomani's avatar francescomani

adapt VRB maps to multiple beams in a period

parent ac94f9c4
...@@ -152,6 +152,7 @@ void nr_dlsim_preprocessor(module_id_t module_id, ...@@ -152,6 +152,7 @@ void nr_dlsim_preprocessor(module_id_t module_id,
/* CC_id = */ 0, /* CC_id = */ 0,
sched_ctrl->aggregation_level, sched_ctrl->aggregation_level,
nr_of_candidates, nr_of_candidates,
0,
&sched_ctrl->sched_pdcch, &sched_ctrl->sched_pdcch,
sched_ctrl->coreset, sched_ctrl->coreset,
Y); Y);
......
...@@ -604,11 +604,16 @@ void nr_mac_config_scc(gNB_MAC_INST *nrmac, NR_ServingCellConfigCommon_t *scc, c ...@@ -604,11 +604,16 @@ void nr_mac_config_scc(gNB_MAC_INST *nrmac, NR_ServingCellConfigCommon_t *scc, c
const int NTN_gNB_Koffset = get_NTN_Koffset(scc); const int NTN_gNB_Koffset = get_NTN_Koffset(scc);
const int n = nr_slots_per_frame[*scc->ssbSubcarrierSpacing]; const int n = nr_slots_per_frame[*scc->ssbSubcarrierSpacing];
const int size = n << (int)ceil(log2((NTN_gNB_Koffset + 13) / n + 1)); // 13 is upper limit for max_fb_time const int size = n << (int)ceil(log2((NTN_gNB_Koffset + 13) / n + 1)); // 13 is upper limit for max_fb_time
nrmac->vrb_map_UL_size = size; nrmac->vrb_map_UL_size = size;
nrmac->common_channels[0].vrb_map_UL = calloc(size * MAX_BWP_SIZE, sizeof(uint16_t));
AssertFatal(nrmac->common_channels[0].vrb_map_UL, int num_beams = 1;
"could not allocate memory for RC.nrmac[]->common_channels[0].vrb_map_UL\n"); if(nrmac->beam_info.beam_allocation)
num_beams = nrmac->beam_info.beams_per_period;
for (int i = 0; i < num_beams; i++) {
nrmac->common_channels[0].vrb_map_UL[i] = calloc(size * MAX_BWP_SIZE, sizeof(uint16_t));
AssertFatal(nrmac->common_channels[0].vrb_map_UL[i],
"could not allocate memory for RC.nrmac[]->common_channels[0].vrb_map_UL[%d]\n", i);
}
nrmac->UL_tti_req_ahead_size = size; nrmac->UL_tti_req_ahead_size = size;
nrmac->UL_tti_req_ahead[0] = calloc(size, sizeof(nfapi_nr_ul_tti_request_t)); nrmac->UL_tti_req_ahead[0] = calloc(size, sizeof(nfapi_nr_ul_tti_request_t));
......
...@@ -246,17 +246,20 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, frame_t frame, sub_frame_ ...@@ -246,17 +246,20 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, frame_t frame, sub_frame_
} }
for (int CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { for (int CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
//mbsfn_status[CC_id] = 0; int num_beams = 1;
if(gNB->beam_info.beam_allocation)
num_beams = gNB->beam_info.beams_per_period;
// clear vrb_maps // clear vrb_maps
memset(cc[CC_id].vrb_map, 0, sizeof(uint16_t) * MAX_BWP_SIZE); for (int i = 0; i < num_beams; i++)
memset(cc[CC_id].vrb_map[i], 0, sizeof(uint16_t) * MAX_BWP_SIZE);
// clear last scheduled slot's content (only)! // clear last scheduled slot's content (only)!
const int num_slots = nr_slots_per_frame[*scc->ssbSubcarrierSpacing]; const int num_slots = nr_slots_per_frame[*scc->ssbSubcarrierSpacing];
const int size = gNB->vrb_map_UL_size; const int size = gNB->vrb_map_UL_size;
const int prev_slot = frame * num_slots + slot + size - 1; const int prev_slot = frame * num_slots + slot + size - 1;
uint16_t *vrb_map_UL = cc[CC_id].vrb_map_UL; for (int i = 0; i < num_beams; i++) {
memcpy(&vrb_map_UL[prev_slot % size * MAX_BWP_SIZE], &gNB->ulprbbl, sizeof(uint16_t) * MAX_BWP_SIZE); uint16_t *vrb_map_UL = cc[CC_id].vrb_map_UL[i];
memcpy(&vrb_map_UL[prev_slot % size * MAX_BWP_SIZE], &gNB->ulprbbl, sizeof(uint16_t) * MAX_BWP_SIZE);
}
clear_nr_nfapi_information(gNB, CC_id, frame, slot, &sched_info->DL_req, &sched_info->TX_req, &sched_info->UL_dci_req); clear_nr_nfapi_information(gNB, CC_id, frame, slot, &sched_info->DL_req, &sched_info->TX_req, &sched_info->UL_dci_req);
} }
......
...@@ -90,13 +90,18 @@ static void schedule_ssb(frame_t frame, ...@@ -90,13 +90,18 @@ static void schedule_ssb(frame_t frame,
LOG_D(MAC,"Scheduling ssb %d at frame %d and slot %d\n",i_ssb,frame,slot); LOG_D(MAC,"Scheduling ssb %d at frame %d and slot %d\n",i_ssb,frame,slot);
} }
static void fill_ssb_vrb_map(NR_COMMON_channels_t *cc, int rbStart, int ssb_subcarrier_offset, uint16_t symStart, int CC_id) static void fill_ssb_vrb_map(NR_COMMON_channels_t *cc,
int rbStart,
int ssb_subcarrier_offset,
uint16_t symStart,
int CC_id,
int beam)
{ {
AssertFatal(*cc->ServingCellConfigCommon->ssbSubcarrierSpacing != AssertFatal(*cc->ServingCellConfigCommon->ssbSubcarrierSpacing !=
NR_SubcarrierSpacing_kHz240, NR_SubcarrierSpacing_kHz240,
"240kHZ subcarrier won't work with current VRB map because a single SSB might be across 2 slots\n"); "240kHZ subcarrier won't work with current VRB map because a single SSB might be across 2 slots\n");
uint16_t *vrb_map = cc[CC_id].vrb_map; uint16_t *vrb_map = cc[CC_id].vrb_map[beam];
const int extra_prb = ssb_subcarrier_offset > 0; const int extra_prb = ssb_subcarrier_offset > 0;
for (int rb = 0; rb < 20 + extra_prb; rb++) for (int rb = 0; rb < 20 + extra_prb; rb++)
vrb_map[rbStart + rb] = SL_to_bitmap(symStart % NR_SYMBOLS_PER_SLOT, 4); vrb_map[rbStart + rb] = SL_to_bitmap(symStart % NR_SYMBOLS_PER_SLOT, 4);
...@@ -178,11 +183,11 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP, ...@@ -178,11 +183,11 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP,
ssb_start_symbol = get_ssb_start_symbol(band, scs, i_ssb); ssb_start_symbol = get_ssb_start_symbol(band, scs, i_ssb);
// if start symbol is in current slot, schedule current SSB, fill VRB map and call get_type0_PDCCH_CSS_config_parameters // if start symbol is in current slot, schedule current SSB, fill VRB map and call get_type0_PDCCH_CSS_config_parameters
if ((ssb_start_symbol / 14) == rel_slot){ if ((ssb_start_symbol / 14) == rel_slot){
bool ret = beam_allocation_procedure(&gNB->beam_info, frameP, slotP, i_ssb, n_slots_frame); int beam = beam_allocation_procedure(&gNB->beam_info, frameP, slotP, i_ssb, n_slots_frame);
AssertFatal(ret, "Cannot allocate SSB %d in any available beam\n", i_ssb); AssertFatal(beam >= 0, "Cannot allocate SSB %d in any available beam\n", i_ssb);
const int prb_offset = offset_pointa >> scs; const int prb_offset = offset_pointa >> scs;
schedule_ssb(frameP, slotP, scc, dl_req, i_ssb, ssbSubcarrierOffset, offset_pointa, mib_pdu); schedule_ssb(frameP, slotP, scc, dl_req, i_ssb, ssbSubcarrierOffset, offset_pointa, mib_pdu);
fill_ssb_vrb_map(cc, prb_offset, ssbSubcarrierOffset, ssb_start_symbol, CC_id); fill_ssb_vrb_map(cc, prb_offset, ssbSubcarrierOffset, ssb_start_symbol, CC_id, beam);
if (get_softmodem_params()->sa == 1) { if (get_softmodem_params()->sa == 1) {
get_type0_PDCCH_CSS_config_parameters(&gNB->type0_PDCCH_CSS_config[i_ssb], get_type0_PDCCH_CSS_config_parameters(&gNB->type0_PDCCH_CSS_config[i_ssb],
frameP, frameP,
...@@ -209,11 +214,11 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP, ...@@ -209,11 +214,11 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP,
ssb_start_symbol = get_ssb_start_symbol(band, scs, i_ssb); ssb_start_symbol = get_ssb_start_symbol(band, scs, i_ssb);
// if start symbol is in current slot, schedule current SSB, fill VRB map and call get_type0_PDCCH_CSS_config_parameters // if start symbol is in current slot, schedule current SSB, fill VRB map and call get_type0_PDCCH_CSS_config_parameters
if ((ssb_start_symbol / 14) == rel_slot){ if ((ssb_start_symbol / 14) == rel_slot){
bool ret = beam_allocation_procedure(&gNB->beam_info, frameP, slotP, i_ssb, n_slots_frame); int beam = beam_allocation_procedure(&gNB->beam_info, frameP, slotP, i_ssb, n_slots_frame);
AssertFatal(ret, "Cannot allocate SSB %d in any available beam\n", i_ssb); AssertFatal(beam >= 0, "Cannot allocate SSB %d in any available beam\n", i_ssb);
const int prb_offset = offset_pointa >> scs; const int prb_offset = offset_pointa >> scs;
schedule_ssb(frameP, slotP, scc, dl_req, i_ssb, ssbSubcarrierOffset, offset_pointa, mib_pdu); schedule_ssb(frameP, slotP, scc, dl_req, i_ssb, ssbSubcarrierOffset, offset_pointa, mib_pdu);
fill_ssb_vrb_map(cc, prb_offset, ssbSubcarrierOffset, ssb_start_symbol, CC_id); fill_ssb_vrb_map(cc, prb_offset, ssbSubcarrierOffset, ssb_start_symbol, CC_id, beam);
if (get_softmodem_params()->sa == 1) { if (get_softmodem_params()->sa == 1) {
get_type0_PDCCH_CSS_config_parameters(&gNB->type0_PDCCH_CSS_config[i_ssb], get_type0_PDCCH_CSS_config_parameters(&gNB->type0_PDCCH_CSS_config[i_ssb],
frameP, frameP,
...@@ -240,11 +245,11 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP, ...@@ -240,11 +245,11 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP,
ssb_start_symbol = get_ssb_start_symbol(band, scs, i_ssb); ssb_start_symbol = get_ssb_start_symbol(band, scs, i_ssb);
// if start symbol is in current slot, schedule current SSB, fill VRB map and call get_type0_PDCCH_CSS_config_parameters // if start symbol is in current slot, schedule current SSB, fill VRB map and call get_type0_PDCCH_CSS_config_parameters
if ((ssb_start_symbol / 14) == rel_slot){ if ((ssb_start_symbol / 14) == rel_slot){
bool ret = beam_allocation_procedure(&gNB->beam_info, frameP, slotP, i_ssb, n_slots_frame); int beam = beam_allocation_procedure(&gNB->beam_info, frameP, slotP, i_ssb, n_slots_frame);
AssertFatal(ret, "Cannot allocate SSB %d in any available beam\n", i_ssb); AssertFatal(beam >= 0, "Cannot allocate SSB %d in any available beam\n", i_ssb);
const int prb_offset = offset_pointa >> (scs-2); // reference 60kHz const int prb_offset = offset_pointa >> (scs-2); // reference 60kHz
schedule_ssb(frameP, slotP, scc, dl_req, i_ssb, ssbSubcarrierOffset, offset_pointa, mib_pdu); schedule_ssb(frameP, slotP, scc, dl_req, i_ssb, ssbSubcarrierOffset, offset_pointa, mib_pdu);
fill_ssb_vrb_map(cc, prb_offset, ssbSubcarrierOffset >> (scs - 2), ssb_start_symbol, CC_id); fill_ssb_vrb_map(cc, prb_offset, ssbSubcarrierOffset >> (scs - 2), ssb_start_symbol, CC_id, beam);
if (get_softmodem_params()->sa == 1) { if (get_softmodem_params()->sa == 1) {
get_type0_PDCCH_CSS_config_parameters(&gNB->type0_PDCCH_CSS_config[i_ssb], get_type0_PDCCH_CSS_config_parameters(&gNB->type0_PDCCH_CSS_config[i_ssb],
frameP, frameP,
...@@ -279,12 +284,13 @@ static uint32_t schedule_control_sib1(module_id_t module_id, ...@@ -279,12 +284,13 @@ static uint32_t schedule_control_sib1(module_id_t module_id,
NR_pdsch_dmrs_t *dmrs_parms, NR_pdsch_dmrs_t *dmrs_parms,
NR_tda_info_t *tda_info, NR_tda_info_t *tda_info,
uint8_t candidate_idx, uint8_t candidate_idx,
int beam,
uint16_t num_total_bytes) uint16_t num_total_bytes)
{ {
gNB_MAC_INST *gNB_mac = RC.nrmac[module_id]; gNB_MAC_INST *gNB_mac = RC.nrmac[module_id];
NR_COMMON_channels_t *cc = &gNB_mac->common_channels[CC_id]; NR_COMMON_channels_t *cc = &gNB_mac->common_channels[CC_id];
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
uint16_t *vrb_map = cc->vrb_map; uint16_t *vrb_map = cc->vrb_map[beam];
if (gNB_mac->sched_ctrlCommon == NULL){ if (gNB_mac->sched_ctrlCommon == NULL){
LOG_D(NR_MAC,"schedule_control_common: Filling nr_mac->sched_ctrlCommon\n"); LOG_D(NR_MAC,"schedule_control_common: Filling nr_mac->sched_ctrlCommon\n");
...@@ -323,6 +329,7 @@ static uint32_t schedule_control_sib1(module_id_t module_id, ...@@ -323,6 +329,7 @@ static uint32_t schedule_control_sib1(module_id_t module_id,
CC_id, CC_id,
gNB_mac->sched_ctrlCommon->aggregation_level, gNB_mac->sched_ctrlCommon->aggregation_level,
nr_of_candidates, nr_of_candidates,
beam,
&gNB_mac->sched_ctrlCommon->sched_pdcch, &gNB_mac->sched_ctrlCommon->sched_pdcch,
gNB_mac->sched_ctrlCommon->coreset, gNB_mac->sched_ctrlCommon->coreset,
0); 0);
...@@ -384,7 +391,8 @@ static uint32_t schedule_control_sib1(module_id_t module_id, ...@@ -384,7 +391,8 @@ static uint32_t schedule_control_sib1(module_id_t module_id,
CC_id, CC_id,
&gNB_mac->sched_ctrlCommon->sched_pdcch, &gNB_mac->sched_ctrlCommon->sched_pdcch,
gNB_mac->sched_ctrlCommon->cce_index, gNB_mac->sched_ctrlCommon->cce_index,
gNB_mac->sched_ctrlCommon->aggregation_level); gNB_mac->sched_ctrlCommon->aggregation_level,
beam);
for (int rb = 0; rb < pdsch->rbSize; rb++) { for (int rb = 0; rb < pdsch->rbSize; rb++) {
vrb_map[rb + rbStart] |= SL_to_bitmap(tda_info->startSymbolIndex, tda_info->nrOfSymbols); vrb_map[rb + rbStart] |= SL_to_bitmap(tda_info->startSymbolIndex, tda_info->nrOfSymbols);
} }
...@@ -578,8 +586,8 @@ void schedule_nr_sib1(module_id_t module_idP, ...@@ -578,8 +586,8 @@ void schedule_nr_sib1(module_id_t module_idP,
(type0_PDCCH_CSS_config->active == true)) { (type0_PDCCH_CSS_config->active == true)) {
const int n_slots_frame = nr_slots_per_frame[*scc->ssbSubcarrierSpacing]; const int n_slots_frame = nr_slots_per_frame[*scc->ssbSubcarrierSpacing];
bool ret = beam_allocation_procedure(&gNB_mac->beam_info, frameP, slotP, i, n_slots_frame); int beam = beam_allocation_procedure(&gNB_mac->beam_info, frameP, slotP, i, n_slots_frame);
AssertFatal(ret, "Cannot allocate SIB1 corresponding to SSB %d in any available beam\n", i); AssertFatal(beam >= 0, "Cannot allocate SIB1 corresponding to SSB %d in any available beam\n", i);
LOG_D(NR_MAC,"(%d.%d) SIB1 transmission: ssb_index %d\n", frameP, slotP, type0_PDCCH_CSS_config->ssb_index); LOG_D(NR_MAC,"(%d.%d) SIB1 transmission: ssb_index %d\n", frameP, slotP, type0_PDCCH_CSS_config->ssb_index);
default_table_type_t table_type = get_default_table_type(type0_PDCCH_CSS_config->type0_pdcch_ss_mux_pattern); default_table_type_t table_type = get_default_table_type(type0_PDCCH_CSS_config->type0_pdcch_ss_mux_pattern);
...@@ -602,6 +610,7 @@ void schedule_nr_sib1(module_id_t module_idP, ...@@ -602,6 +610,7 @@ void schedule_nr_sib1(module_id_t module_idP,
&dmrs_parms, &dmrs_parms,
&tda_info, &tda_info,
candidate_idx, candidate_idx,
beam,
cc->sib1_bcch_length); cc->sib1_bcch_length);
nfapi_nr_dl_tti_request_body_t *dl_req = &DL_req->dl_tti_request_body; nfapi_nr_dl_tti_request_body_t *dl_req = &DL_req->dl_tti_request_body;
......
...@@ -535,10 +535,14 @@ static bool allocate_dl_retransmission(module_id_t module_id, ...@@ -535,10 +535,14 @@ static bool allocate_dl_retransmission(module_id_t module_id,
retInfo->tda_info = temp_tda; retInfo->tda_info = temp_tda;
} }
// TODO properly set the beam index (currently only done for RA)
int beam = 0;
/* Find a free CCE */ /* Find a free CCE */
int CCEIndex = get_cce_index(nr_mac, int CCEIndex = get_cce_index(nr_mac,
CC_id, slot, UE->rnti, CC_id, slot, UE->rnti,
&sched_ctrl->aggregation_level, &sched_ctrl->aggregation_level,
beam,
sched_ctrl->search_space, sched_ctrl->search_space,
sched_ctrl->coreset, sched_ctrl->coreset,
&sched_ctrl->sched_pdcch, &sched_ctrl->sched_pdcch,
...@@ -555,7 +559,6 @@ static bool allocate_dl_retransmission(module_id_t module_id, ...@@ -555,7 +559,6 @@ static bool allocate_dl_retransmission(module_id_t module_id,
* allocation after CCE alloc fail would be more complex) */ * allocation after CCE alloc fail would be more complex) */
int r_pucch = nr_get_pucch_resource(sched_ctrl->coreset, ul_bwp->pucch_Config, CCEIndex); int r_pucch = nr_get_pucch_resource(sched_ctrl->coreset, ul_bwp->pucch_Config, CCEIndex);
// TODO properly set the beam index (currently only done for RA)
const int alloc = nr_acknack_scheduling(nr_mac, UE, frame, slot, 0, r_pucch, 0); const int alloc = nr_acknack_scheduling(nr_mac, UE, frame, slot, 0, r_pucch, 0);
if (alloc<0) { if (alloc<0) {
LOG_D(NR_MAC, "[UE %04x][%4d.%2d] could not find PUCCH for DL DCI retransmission\n", LOG_D(NR_MAC, "[UE %04x][%4d.%2d] could not find PUCCH for DL DCI retransmission\n",
...@@ -570,7 +573,8 @@ static bool allocate_dl_retransmission(module_id_t module_id, ...@@ -570,7 +573,8 @@ static bool allocate_dl_retransmission(module_id_t module_id,
/* CC_id = */ 0, /* CC_id = */ 0,
&sched_ctrl->sched_pdcch, &sched_ctrl->sched_pdcch,
CCEIndex, CCEIndex,
sched_ctrl->aggregation_level); sched_ctrl->aggregation_level,
beam);
/* just reuse from previous scheduling opportunity, set new start RB */ /* just reuse from previous scheduling opportunity, set new start RB */
sched_ctrl->sched_pdsch = *retInfo; sched_ctrl->sched_pdsch = *retInfo;
sched_ctrl->sched_pdsch.rbStart = rbStart; sched_ctrl->sched_pdsch.rbStart = rbStart;
...@@ -724,9 +728,13 @@ static void pf_dl(module_id_t module_id, ...@@ -724,9 +728,13 @@ static void pf_dl(module_id_t module_id,
continue; continue;
} }
// TODO properly set the beam index (currently only done for RA)
int beam = 0;
int CCEIndex = get_cce_index(mac, int CCEIndex = get_cce_index(mac,
CC_id, slot, iterator->UE->rnti, CC_id, slot, iterator->UE->rnti,
&sched_ctrl->aggregation_level, &sched_ctrl->aggregation_level,
beam,
sched_ctrl->search_space, sched_ctrl->search_space,
sched_ctrl->coreset, sched_ctrl->coreset,
&sched_ctrl->sched_pdcch, &sched_ctrl->sched_pdcch,
...@@ -744,7 +752,6 @@ static void pf_dl(module_id_t module_id, ...@@ -744,7 +752,6 @@ static void pf_dl(module_id_t module_id,
* allocation after CCE alloc fail would be more complex) */ * allocation after CCE alloc fail would be more complex) */
int r_pucch = nr_get_pucch_resource(sched_ctrl->coreset, ul_bwp->pucch_Config, CCEIndex); int r_pucch = nr_get_pucch_resource(sched_ctrl->coreset, ul_bwp->pucch_Config, CCEIndex);
// TODO properly set the beam index (currently only done for RA)
const int alloc = nr_acknack_scheduling(mac, iterator->UE, frame, slot, 0, r_pucch, 0); const int alloc = nr_acknack_scheduling(mac, iterator->UE, frame, slot, 0, r_pucch, 0);
if (alloc<0) { if (alloc<0) {
...@@ -761,7 +768,8 @@ static void pf_dl(module_id_t module_id, ...@@ -761,7 +768,8 @@ static void pf_dl(module_id_t module_id,
/* CC_id = */ 0, /* CC_id = */ 0,
&sched_ctrl->sched_pdcch, &sched_ctrl->sched_pdcch,
CCEIndex, CCEIndex,
sched_ctrl->aggregation_level); sched_ctrl->aggregation_level,
beam);
/* MCS has been set above */ /* MCS has been set above */
NR_sched_pdsch_t *sched_pdsch = &sched_ctrl->sched_pdsch; NR_sched_pdsch_t *sched_pdsch = &sched_ctrl->sched_pdsch;
...@@ -861,7 +869,8 @@ static void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_ ...@@ -861,7 +869,8 @@ static void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_
const uint16_t BWPStart = current_BWP->BWPStart; const uint16_t BWPStart = current_BWP->BWPStart;
const uint16_t slbitmap = SL_to_bitmap(startSymbolIndex, nrOfSymbols); const uint16_t slbitmap = SL_to_bitmap(startSymbolIndex, nrOfSymbols);
uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map; // TODO improve handling of beam in vrb_map (for now just using 0)
uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map[0];
uint16_t rballoc_mask[bwpSize]; uint16_t rballoc_mask[bwpSize];
int n_rb_sched = 0; int n_rb_sched = 0;
......
...@@ -83,11 +83,14 @@ void nr_preprocessor_phytest(module_id_t module_id, ...@@ -83,11 +83,14 @@ void nr_preprocessor_phytest(module_id_t module_id,
const int bwpSize = dl_bwp->BWPSize; const int bwpSize = dl_bwp->BWPSize;
const int BWPStart = dl_bwp->BWPStart; const int BWPStart = dl_bwp->BWPStart;
// TODO implement beam procedures for phy-test mode
int beam = 0;
int rbStart = 0; int rbStart = 0;
int rbSize = 0; int rbSize = 0;
if (target_dl_bw>bwpSize) if (target_dl_bw>bwpSize)
target_dl_bw = bwpSize; target_dl_bw = bwpSize;
uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map; uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map[beam];
/* loop ensures that we allocate exactly target_dl_bw, or return */ /* loop ensures that we allocate exactly target_dl_bw, or return */
while (true) { while (true) {
/* advance to first free RB */ /* advance to first free RB */
...@@ -131,6 +134,7 @@ void nr_preprocessor_phytest(module_id_t module_id, ...@@ -131,6 +134,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
int CCEIndex = get_cce_index(RC.nrmac[module_id], int CCEIndex = get_cce_index(RC.nrmac[module_id],
CC_id, slot, UE->rnti, CC_id, slot, UE->rnti,
&sched_ctrl->aggregation_level, &sched_ctrl->aggregation_level,
beam,
sched_ctrl->search_space, sched_ctrl->search_space,
sched_ctrl->coreset, sched_ctrl->coreset,
&sched_ctrl->sched_pdcch, &sched_ctrl->sched_pdcch,
...@@ -158,7 +162,8 @@ void nr_preprocessor_phytest(module_id_t module_id, ...@@ -158,7 +162,8 @@ void nr_preprocessor_phytest(module_id_t module_id,
CC_id, CC_id,
&sched_ctrl->sched_pdcch, &sched_ctrl->sched_pdcch,
CCEIndex, CCEIndex,
sched_ctrl->aggregation_level); sched_ctrl->aggregation_level,
beam);
//AssertFatal(alloc, //AssertFatal(alloc,
// "could not find uplink slot for PUCCH (RNTI %04x@%d.%d)!\n", // "could not find uplink slot for PUCCH (RNTI %04x@%d.%d)!\n",
...@@ -273,8 +278,11 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_ ...@@ -273,8 +278,11 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
tda); tda);
sched_ctrl->sched_pusch.tda_info = tda_info; sched_ctrl->sched_pusch.tda_info = tda_info;
// TODO implement beam procedures for phy-test mode
int beam = 0;
const int buffer_index = ul_buffer_index(sched_frame, sched_slot, mu, nr_mac->vrb_map_UL_size); const int buffer_index = ul_buffer_index(sched_frame, sched_slot, mu, nr_mac->vrb_map_UL_size);
uint16_t *vrb_map_UL = &nr_mac->common_channels[CC_id].vrb_map_UL[buffer_index * MAX_BWP_SIZE]; uint16_t *vrb_map_UL = &nr_mac->common_channels[CC_id].vrb_map_UL[beam][buffer_index * MAX_BWP_SIZE];
for (int i = rbStart; i < rbStart + rbSize; ++i) { for (int i = rbStart; i < rbStart + rbSize; ++i) {
if ((vrb_map_UL[i+BWPStart] & SL_to_bitmap(tda_info.startSymbolIndex, tda_info.nrOfSymbols)) != 0) { if ((vrb_map_UL[i+BWPStart] & SL_to_bitmap(tda_info.startSymbolIndex, tda_info.nrOfSymbols)) != 0) {
LOG_E(MAC, LOG_E(MAC,
...@@ -293,6 +301,7 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_ ...@@ -293,6 +301,7 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
int CCEIndex = get_cce_index(nr_mac, int CCEIndex = get_cce_index(nr_mac,
CC_id, slot, UE->rnti, CC_id, slot, UE->rnti,
&sched_ctrl->aggregation_level, &sched_ctrl->aggregation_level,
beam,
sched_ctrl->search_space, sched_ctrl->search_space,
sched_ctrl->coreset, sched_ctrl->coreset,
&sched_ctrl->sched_pdcch, &sched_ctrl->sched_pdcch,
...@@ -344,7 +353,8 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_ ...@@ -344,7 +353,8 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
CC_id, CC_id,
&sched_ctrl->sched_pdcch, &sched_ctrl->sched_pdcch,
CCEIndex, CCEIndex,
sched_ctrl->aggregation_level); sched_ctrl->aggregation_level,
beam);
for (int rb = rbStart; rb < rbStart + rbSize; rb++) for (int rb = rbStart; rb < rbStart + rbSize; rb++)
vrb_map_UL[rb+BWPStart] |= SL_to_bitmap(tda_info.startSymbolIndex, tda_info.nrOfSymbols); vrb_map_UL[rb+BWPStart] |= SL_to_bitmap(tda_info.startSymbolIndex, tda_info.nrOfSymbols);
......
...@@ -501,11 +501,12 @@ int find_pdcch_candidate(const gNB_MAC_INST *mac, ...@@ -501,11 +501,12 @@ int find_pdcch_candidate(const gNB_MAC_INST *mac,
int cc_id, int cc_id,
int aggregation, int aggregation,
int nr_of_candidates, int nr_of_candidates,
int beam_idx,
const NR_sched_pdcch_t *pdcch, const NR_sched_pdcch_t *pdcch,
const NR_ControlResourceSet_t *coreset, const NR_ControlResourceSet_t *coreset,
uint32_t Y) uint32_t Y)
{ {
const uint16_t *vrb_map = mac->common_channels[cc_id].vrb_map; const uint16_t *vrb_map = mac->common_channels[cc_id].vrb_map[beam_idx];
const int N_ci = 0; const int N_ci = 0;
const int N_rb = pdcch->n_rb; // nb of rbs of coreset per symbol const int N_rb = pdcch->n_rb; // nb of rbs of coreset per symbol
...@@ -546,6 +547,7 @@ int get_cce_index(const gNB_MAC_INST *nrmac, ...@@ -546,6 +547,7 @@ int get_cce_index(const gNB_MAC_INST *nrmac,
const int slot, const int slot,
const rnti_t rnti, const rnti_t rnti,
uint8_t *aggregation_level, uint8_t *aggregation_level,
int beam_idx,
const NR_SearchSpace_t *ss, const NR_SearchSpace_t *ss,
const NR_ControlResourceSet_t *coreset, const NR_ControlResourceSet_t *coreset,
NR_sched_pdcch_t *sched_pdcch, NR_sched_pdcch_t *sched_pdcch,
...@@ -567,6 +569,7 @@ int get_cce_index(const gNB_MAC_INST *nrmac, ...@@ -567,6 +569,7 @@ int get_cce_index(const gNB_MAC_INST *nrmac,
CC_id, CC_id,
*aggregation_level, *aggregation_level,
nr_of_candidates, nr_of_candidates,
beam_idx,
sched_pdcch, sched_pdcch,
coreset, coreset,
Y); Y);
...@@ -577,9 +580,10 @@ void fill_pdcch_vrb_map(gNB_MAC_INST *mac, ...@@ -577,9 +580,10 @@ void fill_pdcch_vrb_map(gNB_MAC_INST *mac,
int CC_id, int CC_id,
NR_sched_pdcch_t *pdcch, NR_sched_pdcch_t *pdcch,
int first_cce, int first_cce,
int aggregation){ int aggregation,
int beam)
uint16_t *vrb_map = mac->common_channels[CC_id].vrb_map; {
uint16_t *vrb_map = mac->common_channels[CC_id].vrb_map[beam];
int N_rb = pdcch->n_rb; // nb of rbs of coreset per symbol int N_rb = pdcch->n_rb; // nb of rbs of coreset per symbol
int L = pdcch->RegBundleSize; int L = pdcch->RegBundleSize;
...@@ -2715,7 +2719,9 @@ void nr_csirs_scheduling(int Mod_idP, frame_t frame, sub_frame_t slot, int n_slo ...@@ -2715,7 +2719,9 @@ void nr_csirs_scheduling(int Mod_idP, frame_t frame, sub_frame_t slot, int n_slo
NR_SCHED_ENSURE_LOCKED(&gNB_mac->sched_lock); NR_SCHED_ENSURE_LOCKED(&gNB_mac->sched_lock);
uint16_t *vrb_map = gNB_mac->common_channels[CC_id].vrb_map; // TODO implement beam procedures
int beam = 0;
uint16_t *vrb_map = gNB_mac->common_channels[CC_id].vrb_map[beam];
UE_info->sched_csirs = 0; UE_info->sched_csirs = 0;
...@@ -3093,20 +3099,21 @@ void UL_tti_req_ahead_initialization(gNB_MAC_INST *gNB, int n, int CCid, frame_t ...@@ -3093,20 +3099,21 @@ void UL_tti_req_ahead_initialization(gNB_MAC_INST *gNB, int n, int CCid, frame_t
} }
} }
bool beam_allocation_procedure(NR_beam_info_t *beam_info, int frame, int slot, int beam_index, int slots_per_frame) // return index of beam in period if valid or -1 if not valid
int beam_allocation_procedure(NR_beam_info_t *beam_info, int frame, int slot, int beam_index, int slots_per_frame)
{ {
// if digital beamforming, no restriction // if no beam allocation for analog beamforming we always return beam index 0 (no multiple beams)
if(!beam_info->beam_allocation) if(!beam_info->beam_allocation)
return true; return 0;
const int index = ((frame * slots_per_frame + slot) / beam_info->slots_in_beam_period) % beam_info->beam_allocation_size; const int index = ((frame * slots_per_frame + slot) / beam_info->slots_in_beam_period) % beam_info->beam_allocation_size;
for (int i = 0; i < beam_info->beams_per_period; i++) { for (int i = 0; i < beam_info->beams_per_period; i++) {
if (beam_info->beam_allocation[i][index] == -1 || if (beam_info->beam_allocation[i][index] == -1 ||
beam_info->beam_allocation[i][index] == beam_index) { beam_info->beam_allocation[i][index] == beam_index) {
beam_info->beam_allocation[i][index] = beam_index; beam_info->beam_allocation[i][index] = beam_index;
return true; return i;
} }
} }
return false; return -1;
} }
void reset_beam_status(NR_beam_info_t *beam_info, int frame, int slot, int beam_index, int slots_per_frame) void reset_beam_status(NR_beam_info_t *beam_info, int frame, int slot, int beam_index, int slots_per_frame)
......
...@@ -470,7 +470,8 @@ static void nr_configure_srs(nfapi_nr_srs_pdu_t *srs_pdu, ...@@ -470,7 +470,8 @@ static void nr_configure_srs(nfapi_nr_srs_pdu_t *srs_pdu,
srs_pdu->beamforming.prg_size = 1; srs_pdu->beamforming.prg_size = 1;
} }
uint16_t *vrb_map_UL = &RC.nrmac[module_id]->common_channels[CC_id].vrb_map_UL[buffer_index * MAX_BWP_SIZE]; // TODO properly use beam allocation
uint16_t *vrb_map_UL = &RC.nrmac[module_id]->common_channels[CC_id].vrb_map_UL[0][buffer_index * MAX_BWP_SIZE];
uint64_t mask = SL_to_bitmap(13 - srs_pdu->time_start_position, srs_pdu->num_symbols); uint64_t mask = SL_to_bitmap(13 - srs_pdu->time_start_position, srs_pdu->num_symbols);
for (int i = 0; i < srs_pdu->bwp_size; ++i) for (int i = 0; i < srs_pdu->bwp_size; ++i)
vrb_map_UL[i + srs_pdu->bwp_start] |= mask; vrb_map_UL[i + srs_pdu->bwp_start] |= mask;
......
...@@ -279,8 +279,9 @@ void nr_csi_meas_reporting(int Mod_idP, ...@@ -279,8 +279,9 @@ void nr_csi_meas_reporting(int Mod_idP,
int bwp_start = ul_bwp->BWPStart; int bwp_start = ul_bwp->BWPStart;
// going through the list of PUCCH resources to find the one indexed by resource_id // going through the list of PUCCH resources to find the one indexed by resource_id
int beam_idx = 0; // TODO proper beam allocation
const int index = ul_buffer_index(sched_frame, sched_slot, ul_bwp->scs, nrmac->vrb_map_UL_size); const int index = ul_buffer_index(sched_frame, sched_slot, ul_bwp->scs, nrmac->vrb_map_UL_size);
uint16_t *vrb_map_UL = &nrmac->common_channels[0].vrb_map_UL[index * MAX_BWP_SIZE]; uint16_t *vrb_map_UL = &nrmac->common_channels[0].vrb_map_UL[beam_idx][index * MAX_BWP_SIZE];
const int m = pucch_Config->resourceToAddModList->list.count; const int m = pucch_Config->resourceToAddModList->list.count;
for (int j = 0; j < m; j++) { for (int j = 0; j < m; j++) {
NR_PUCCH_Resource_t *pucchres = pucch_Config->resourceToAddModList->list.array[j]; NR_PUCCH_Resource_t *pucchres = pucch_Config->resourceToAddModList->list.array[j];
...@@ -1325,8 +1326,15 @@ int nr_acknack_scheduling(gNB_MAC_INST *mac, ...@@ -1325,8 +1326,15 @@ int nr_acknack_scheduling(gNB_MAC_INST *mac,
else { // unoccupied occasion else { // unoccupied occasion
// checking if in ul_slot the resources potentially to be assigned to this PUCCH are available // checking if in ul_slot the resources potentially to be assigned to this PUCCH are available
set_pucch_allocation(ul_bwp, r_pucch, bwp_size, curr_pucch); set_pucch_allocation(ul_bwp, r_pucch, bwp_size, curr_pucch);
int beam = beam_allocation_procedure(&mac->beam_info, pucch_frame, pucch_slot, beam_index, n_slots_frame);
if (beam < 0) {
LOG_D(NR_MAC,
"DL %4d.%2d, UL_ACK %4d.%2d beam resources for this occasion are already occupied, move to the following occasion\n",
frame, slot, pucch_frame, pucch_slot);
continue;
}
const int index = ul_buffer_index(pucch_frame, pucch_slot, ul_bwp->scs, mac->vrb_map_UL_size); const int index = ul_buffer_index(pucch_frame, pucch_slot, ul_bwp->scs, mac->vrb_map_UL_size);
uint16_t *vrb_map_UL = &mac->common_channels[CC_id].vrb_map_UL[index * MAX_BWP_SIZE]; uint16_t *vrb_map_UL = &mac->common_channels[CC_id].vrb_map_UL[beam][index * MAX_BWP_SIZE];
bool ret = test_pucch0_vrb_occupation(curr_pucch, bool ret = test_pucch0_vrb_occupation(curr_pucch,
vrb_map_UL, vrb_map_UL,
bwp_start, bwp_start,
...@@ -1337,13 +1345,6 @@ int nr_acknack_scheduling(gNB_MAC_INST *mac, ...@@ -1337,13 +1345,6 @@ int nr_acknack_scheduling(gNB_MAC_INST *mac,
frame, slot, pucch_frame, pucch_slot); frame, slot, pucch_frame, pucch_slot);
continue; continue;
} }
ret = beam_allocation_procedure(&mac->beam_info, pucch_frame, pucch_slot, beam_index, n_slots_frame);
if (!ret) {
LOG_D(NR_MAC,
"DL %4d.%2d, UL_ACK %4d.%2d beam resources for this occasion are already occupied, move to the following occasion\n",
frame, slot, pucch_frame, pucch_slot);
continue;
}
// allocating a new PUCCH structure for this occasion // allocating a new PUCCH structure for this occasion
curr_pucch->active = true; curr_pucch->active = true;
curr_pucch->frame = pucch_frame; curr_pucch->frame = pucch_frame;
...@@ -1433,8 +1434,9 @@ void nr_sr_reporting(gNB_MAC_INST *nrmac, frame_t SFN, sub_frame_t slot) ...@@ -1433,8 +1434,9 @@ void nr_sr_reporting(gNB_MAC_INST *nrmac, frame_t SFN, sub_frame_t slot)
continue; continue;
} }
else { else {
int beam_idx = 0; // TODO proper beam allocation
const int index = ul_buffer_index(SFN, slot, ul_bwp->scs, nrmac->vrb_map_UL_size); const int index = ul_buffer_index(SFN, slot, ul_bwp->scs, nrmac->vrb_map_UL_size);
uint16_t *vrb_map_UL = &nrmac->common_channels[CC_id].vrb_map_UL[index * MAX_BWP_SIZE]; uint16_t *vrb_map_UL = &nrmac->common_channels[CC_id].vrb_map_UL[beam_idx][index * MAX_BWP_SIZE];
const int bwp_start = ul_bwp->BWPStart; const int bwp_start = ul_bwp->BWPStart;
const int bwp_size = ul_bwp->BWPSize; const int bwp_size = ul_bwp->BWPSize;
set_pucch_allocation(ul_bwp, -1, bwp_size, curr_pucch); set_pucch_allocation(ul_bwp, -1, bwp_size, curr_pucch);
......
...@@ -1667,6 +1667,7 @@ static bool allocate_ul_retransmission(gNB_MAC_INST *nrmac, ...@@ -1667,6 +1667,7 @@ static bool allocate_ul_retransmission(gNB_MAC_INST *nrmac,
int CCEIndex = get_cce_index(nrmac, int CCEIndex = get_cce_index(nrmac,
CC_id, slot, UE->rnti, CC_id, slot, UE->rnti,
&sched_ctrl->aggregation_level, &sched_ctrl->aggregation_level,
0, // TODO use beam index
sched_ctrl->search_space, sched_ctrl->search_space,
sched_ctrl->coreset, sched_ctrl->coreset,
&sched_ctrl->sched_pdcch, &sched_ctrl->sched_pdcch,
...@@ -1684,7 +1685,8 @@ static bool allocate_ul_retransmission(gNB_MAC_INST *nrmac, ...@@ -1684,7 +1685,8 @@ static bool allocate_ul_retransmission(gNB_MAC_INST *nrmac,
CC_id, CC_id,
&sched_ctrl->sched_pdcch, &sched_ctrl->sched_pdcch,
CCEIndex, CCEIndex,
sched_ctrl->aggregation_level); sched_ctrl->aggregation_level,
0); // TODO use beam index when implemented
/* frame/slot in sched_pusch has been set previously. In the following, we /* frame/slot in sched_pusch has been set previously. In the following, we
* overwrite the information in the retransmission information before storing * overwrite the information in the retransmission information before storing
...@@ -1825,6 +1827,7 @@ static void pf_ul(module_id_t module_id, ...@@ -1825,6 +1827,7 @@ static void pf_ul(module_id_t module_id,
int CCEIndex = get_cce_index(nrmac, int CCEIndex = get_cce_index(nrmac,
CC_id, slot, UE->rnti, CC_id, slot, UE->rnti,
&sched_ctrl->aggregation_level, &sched_ctrl->aggregation_level,
0, // TODO use beam index
sched_ctrl->search_space, sched_ctrl->search_space,
sched_ctrl->coreset, sched_ctrl->coreset,
&sched_ctrl->sched_pdcch, &sched_ctrl->sched_pdcch,
...@@ -1870,7 +1873,8 @@ static void pf_ul(module_id_t module_id, ...@@ -1870,7 +1873,8 @@ static void pf_ul(module_id_t module_id,
CC_id, CC_id,
&sched_ctrl->sched_pdcch, &sched_ctrl->sched_pdcch,
CCEIndex, CCEIndex,
sched_ctrl->aggregation_level); sched_ctrl->aggregation_level,
0); // TODO use beam index);
NR_sched_pusch_t *sched_pusch = &sched_ctrl->sched_pusch; NR_sched_pusch_t *sched_pusch = &sched_ctrl->sched_pusch;
sched_pusch->mcs = min(nrmac->min_grant_mcs, sched_pusch->mcs); sched_pusch->mcs = min(nrmac->min_grant_mcs, sched_pusch->mcs);
...@@ -1941,6 +1945,7 @@ static void pf_ul(module_id_t module_id, ...@@ -1941,6 +1945,7 @@ static void pf_ul(module_id_t module_id,
int CCEIndex = get_cce_index(nrmac, int CCEIndex = get_cce_index(nrmac,
CC_id, slot, iterator->UE->rnti, CC_id, slot, iterator->UE->rnti,
&sched_ctrl->aggregation_level, &sched_ctrl->aggregation_level,
0, // TODO use beam index
sched_ctrl->search_space, sched_ctrl->search_space,
sched_ctrl->coreset, sched_ctrl->coreset,
&sched_ctrl->sched_pdcch, &sched_ctrl->sched_pdcch,
...@@ -2046,7 +2051,8 @@ static void pf_ul(module_id_t module_id, ...@@ -2046,7 +2051,8 @@ static void pf_ul(module_id_t module_id,
CC_id, CC_id,
&sched_ctrl->sched_pdcch, &sched_ctrl->sched_pdcch,
CCEIndex, CCEIndex,
sched_ctrl->aggregation_level); sched_ctrl->aggregation_level,
0); // TODO use beam index);
n_rb_sched -= sched_pusch->rbSize; n_rb_sched -= sched_pusch->rbSize;
for (int rb = 0; rb < sched_ctrl->sched_pusch.rbSize; rb++) for (int rb = 0; rb < sched_ctrl->sched_pusch.rbSize; rb++)
...@@ -2112,7 +2118,8 @@ static bool nr_fr1_ulsch_preprocessor(module_id_t module_id, frame_t frame, sub_ ...@@ -2112,7 +2118,8 @@ static bool nr_fr1_ulsch_preprocessor(module_id_t module_id, frame_t frame, sub_
* vrb_map_UL) overlap with the "default" tda and exclude those RBs. * vrb_map_UL) overlap with the "default" tda and exclude those RBs.
* Calculate largest contiguous RBs */ * Calculate largest contiguous RBs */
const int index = ul_buffer_index(sched_frame, sched_slot, mu, nr_mac->vrb_map_UL_size); const int index = ul_buffer_index(sched_frame, sched_slot, mu, nr_mac->vrb_map_UL_size);
uint16_t *vrb_map_UL = &nr_mac->common_channels[CC_id].vrb_map_UL[index * MAX_BWP_SIZE]; // TODO improve handling of beam in vrb_map (for now just using 0)
uint16_t *vrb_map_UL = &nr_mac->common_channels[CC_id].vrb_map_UL[0][index * MAX_BWP_SIZE];
const uint16_t bwpSize = current_BWP->BWPSize; const uint16_t bwpSize = current_BWP->BWPSize;
const uint16_t bwpStart = current_BWP->BWPStart; const uint16_t bwpStart = current_BWP->BWPStart;
......
...@@ -215,6 +215,7 @@ int find_pdcch_candidate(const gNB_MAC_INST *mac, ...@@ -215,6 +215,7 @@ int find_pdcch_candidate(const gNB_MAC_INST *mac,
int cc_id, int cc_id,
int aggregation, int aggregation,
int nr_of_candidates, int nr_of_candidates,
int beam_idx,
const NR_sched_pdcch_t *pdcch, const NR_sched_pdcch_t *pdcch,
const NR_ControlResourceSet_t *coreset, const NR_ControlResourceSet_t *coreset,
uint32_t Y); uint32_t Y);
...@@ -223,7 +224,8 @@ void fill_pdcch_vrb_map(gNB_MAC_INST *mac, ...@@ -223,7 +224,8 @@ void fill_pdcch_vrb_map(gNB_MAC_INST *mac,
int CC_id, int CC_id,
NR_sched_pdcch_t *pdcch, NR_sched_pdcch_t *pdcch,
int first_cce, int first_cce,
int aggregation); int aggregation,
int beam);
void fill_dci_pdu_rel15(const NR_UE_ServingCell_Info_t *servingCellInfo, void fill_dci_pdu_rel15(const NR_UE_ServingCell_Info_t *servingCellInfo,
const NR_UE_DL_BWP_t *current_DL_BWP, const NR_UE_DL_BWP_t *current_DL_BWP,
...@@ -396,6 +398,7 @@ int get_cce_index(const gNB_MAC_INST *nrmac, ...@@ -396,6 +398,7 @@ int get_cce_index(const gNB_MAC_INST *nrmac,
const int slot, const int slot,
const rnti_t rnti, const rnti_t rnti,
uint8_t *aggregation_level, uint8_t *aggregation_level,
int beam_idx,
const NR_SearchSpace_t *ss, const NR_SearchSpace_t *ss,
const NR_ControlResourceSet_t *coreset, const NR_ControlResourceSet_t *coreset,
NR_sched_pdcch_t *sched_pdcch, NR_sched_pdcch_t *sched_pdcch,
...@@ -422,7 +425,7 @@ int get_mcs_from_bler(const NR_bler_options_t *bler_options, ...@@ -422,7 +425,7 @@ int get_mcs_from_bler(const NR_bler_options_t *bler_options,
int ul_buffer_index(int frame, int slot, int scs, int size); int ul_buffer_index(int frame, int slot, int scs, int size);
void UL_tti_req_ahead_initialization(gNB_MAC_INST *gNB, int n, int CCid, frame_t frameP, int slotP); void UL_tti_req_ahead_initialization(gNB_MAC_INST *gNB, int n, int CCid, frame_t frameP, int slotP);
bool beam_allocation_procedure(NR_beam_info_t *beam_info, int frame, int slot, int beam_index, int slots_per_frame); int beam_allocation_procedure(NR_beam_info_t *beam_info, int frame, int slot, int beam_index, int slots_per_frame);
void reset_beam_status(NR_beam_info_t *beam_info, int frame, int slot, int beam_index, int slots_per_frame); void reset_beam_status(NR_beam_info_t *beam_info, int frame, int slot, int beam_index, int slots_per_frame);
void nr_sr_reporting(gNB_MAC_INST *nrmac, frame_t frameP, sub_frame_t slotP); void nr_sr_reporting(gNB_MAC_INST *nrmac, frame_t frameP, sub_frame_t slotP);
......
...@@ -100,6 +100,7 @@ ...@@ -100,6 +100,7 @@
#define MAX_NUM_OF_SSB 64 #define MAX_NUM_OF_SSB 64
#define MAX_NUM_NR_PRACH_PREAMBLES 64 #define MAX_NUM_NR_PRACH_PREAMBLES 64
#define MIN_NUM_PRBS_TO_SCHEDULE 5 #define MIN_NUM_PRBS_TO_SCHEDULE 5
#define MAX_NUM_BEAM_PERIODS 4
extern const uint8_t nr_rv_round_map[4]; extern const uint8_t nr_rv_round_map[4];
...@@ -200,6 +201,8 @@ typedef struct { ...@@ -200,6 +201,8 @@ typedef struct {
frame_t Msg3_frame; frame_t Msg3_frame;
/// Msg3 time domain allocation index /// Msg3 time domain allocation index
int Msg3_tda_id; int Msg3_tda_id;
/// Msg3 beam matrix index
int Msg3_beam_idx;
/// harq_pid used for Msg4 transmission /// harq_pid used for Msg4 transmission
uint8_t harq_pid; uint8_t harq_pid;
/// UE RNTI allocated during RAR /// UE RNTI allocated during RAR
...@@ -258,10 +261,10 @@ typedef struct { ...@@ -258,10 +261,10 @@ typedef struct {
/// Template for RA computations /// Template for RA computations
NR_RA_t ra[NR_NB_RA_PROC_MAX]; NR_RA_t ra[NR_NB_RA_PROC_MAX];
/// VRB map for common channels /// VRB map for common channels
uint16_t vrb_map[275]; uint16_t vrb_map[MAX_NUM_BEAM_PERIODS][275];
/// VRB map for common channels and PUSCH, dynamically allocated because /// VRB map for common channels and PUSCH, dynamically allocated because
/// length depends on number of slots and RBs /// length depends on number of slots and RBs
uint16_t *vrb_map_UL; uint16_t *vrb_map_UL[MAX_NUM_BEAM_PERIODS];
///Number of active SSBs ///Number of active SSBs
int num_active_ssb; int num_active_ssb;
//Total available prach occasions per configuration period //Total available prach occasions per configuration period
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment