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Commit ce1246e0 authored by Robert Schmidt's avatar Robert Schmidt
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Merge remote-tracking branch 'origin/NR_UE_BWP_reworking' into integration_2022_wk02

parents 3b4371e0 01030bbc
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Showing with 654 additions and 907 deletions
common/utils/nr/nr_common.h
View file @ ce1246e0
......@@ -37,7 +37,9 @@
#include "assertions.h"
#include "PHY/defs_common.h"
#define MAX_BWP_SIZE 275
#define MAX_BWP_SIZE 275
#define NR_MAX_NUM_BWP 4
#define NR_MAX_HARQ_PROCESSES 16
typedef struct nr_bandentry_s {
int16_t band;
......
nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h
View file @ ce1246e0
......@@ -22,6 +22,7 @@
#include "platform_types.h"
#include "fapi_nr_ue_constants.h"
#include "PHY/impl_defs_nr.h"
#include "common/utils/nr/nr_common.h"
#define NFAPI_UE_MAX_NUM_CB 8
#define NFAPI_MAX_NUM_UL_PDU 255
......@@ -86,10 +87,12 @@ typedef struct {
typedef struct {
uint16_t rnti;
uint8_t dci_format;
int ss_type;
// n_CCE index of first CCE for PDCCH reception
int n_CCE;
// N_CCE is L, or number of CCEs for DCI
int N_CCE;
int cset_start;
uint8_t payloadSize;
uint8_t payloadBits[16] __attribute__((aligned(16))); // will be cast as uint64
} fapi_nr_dci_indication_pdu_t;
......@@ -413,6 +416,7 @@ typedef struct {
uint8_t num_dci_options; // Num DCIs the UE actually needs to decode (1 or 2)
uint8_t dci_length_options[2];
uint8_t dci_format_options[2];
uint8_t dci_type_options[2];
} fapi_nr_dl_config_dci_dl_pdu_rel15_t;
typedef struct {
......
openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c
View file @ ce1246e0
......@@ -1017,7 +1017,7 @@ void nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
if(nb_rb_coreset==0) return;
#ifdef DEBUG_PDCCH
printf(PHY, "pdcch_channel_estimation: first_carrier_offset %d, BWPStart %d, coreset_start_rb %d, coreset_nb_rb %d\n",
printf("pdcch_channel_estimation: first_carrier_offset %d, BWPStart %d, coreset_start_rb %d, coreset_nb_rb %d\n",
first_carrier_offset, BWPStart, coreset_start_rb, nb_rb_coreset);
#endif
......@@ -1044,7 +1044,6 @@ void nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
int dmrs_ref = 0;
if (coreset->CoreSetType == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG)
dmrs_ref = BWPStart;
// generate pilot
int pilot[(nb_rb_coreset + dmrs_ref) * 3] __attribute__((aligned(16)));
nr_pdcch_dmrs_rx(ue,Ns,ue->nr_gold_pdcch[gNB_id][Ns][symbol], &pilot[0],2000,(nb_rb_coreset+dmrs_ref));
......
openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
View file @ ce1246e0
......@@ -931,10 +931,14 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
else {
dci_ind->SFN = proc->frame_rx;
dci_ind->slot = proc->nr_slot_rx;
dci_ind->dci_list[dci_ind->number_of_dcis].rnti = n_rnti;
dci_ind->dci_list[dci_ind->number_of_dcis].n_CCE = CCEind;
dci_ind->dci_list[dci_ind->number_of_dcis].N_CCE = L;
dci_ind->dci_list[dci_ind->number_of_dcis].dci_format = rel15->dci_format_options[k];
dci_ind->dci_list[dci_ind->number_of_dcis].rnti = n_rnti;
dci_ind->dci_list[dci_ind->number_of_dcis].n_CCE = CCEind;
dci_ind->dci_list[dci_ind->number_of_dcis].N_CCE = L;
dci_ind->dci_list[dci_ind->number_of_dcis].dci_format = rel15->dci_format_options[k];
dci_ind->dci_list[dci_ind->number_of_dcis].ss_type = rel15->dci_type_options[k];
int n_rb, rb_offset;
get_coreset_rballoc(rel15->coreset.frequency_domain_resource, &n_rb, &rb_offset);
dci_ind->dci_list[dci_ind->number_of_dcis].cset_start = rel15->BWPStart + rb_offset;
dci_ind->dci_list[dci_ind->number_of_dcis].payloadSize = dci_length;
memcpy((void*)dci_ind->dci_list[dci_ind->number_of_dcis].payloadBits,(void*)dci_estimation,8);
dci_ind->number_of_dcis++;
......
openair1/PHY/defs_nr_common.h
View file @ ce1246e0
......@@ -80,8 +80,6 @@
#define NR_MAX_DCI_SIZE 1728 //16(L)*2(QPSK)*9(12 RE per REG - 3(DMRS))*6(REG per CCE)
#define NR_MAX_DCI_SIZE_DWORD 54 // ceil(NR_MAX_DCI_SIZE/32)
#define NR_MAX_NUM_BWP 4
#define NR_MAX_PDCCH_AGG_LEVEL 16 // 3GPP TS 38.211 V15.8 Section 7.3.2 Table 7.3.2.1-1: Supported PDCCH aggregation levels
#define NR_MAX_CSET_DURATION 3
......@@ -158,11 +156,6 @@ typedef enum {
MOD_QAM256
}nr_mod_t;
typedef enum {
RA_2STEP = 0,
RA_4STEP
} nr_ra_type_e;
typedef struct {
/// Size of first RBG
uint8_t start_size;
......
openair1/PHY/impl_defs_nr.h
View file @ ce1246e0
......@@ -364,11 +364,6 @@ typedef enum {
pusch_dmrs_type2 = 1
} pusch_dmrs_type_t;
typedef enum {
pusch_len1 = 1,
pusch_len2 = 2
} pusch_maxLength_t;
typedef enum {
txConfig_codebook = 1,
txConfig_nonCodebook = 2
......
openair1/PHY/impl_defs_top.h
View file @ ce1246e0
......@@ -107,6 +107,7 @@
* @}
*/
#include <common/utils/nr/nr_common.h>
#include <common/utils/utils.h>
#include "defs_eNB.h"
#include "types.h"
......@@ -277,8 +278,6 @@
#define DURATION_RX_TO_TX (6) /* For LTE, this duration is fixed to 4 and it is linked to LTE standard for both modes FDD/TDD */
#endif
#define NR_MAX_HARQ_PROCESSES (16)
#define NR_MAX_ULSCH_HARQ_PROCESSES (NR_MAX_HARQ_PROCESSES) /* cf 38.214 6.1 UE procedure for receiving the physical uplink shared channel */
#define NR_MAX_DLSCH_HARQ_PROCESSES (NR_MAX_HARQ_PROCESSES) /* cf 38.214 5.1 UE procedure for receiving the physical downlink shared channel */
#endif
......
openair1/SCHED_NR_UE/harq_nr.h
View file @ ce1246e0
......@@ -35,15 +35,6 @@
/************** DEFINE ********************************************/
#if 0
/* these define are in file PHY/impl_defs_top.h" because of compilation problems due to multiple header files inclusions */
#define NR_MAX_HARQ_PROCESSES (16)
#define NR_MAX_ULSCH_HARQ_PROCESSES (NR_MAX_HARQ_PROCESSES) /* TS 38.214 6.1 UE procedure for receiving the physical uplink shared channel */
#define NR_MAX_DLSCH_HARQ_PROCESSES (NR_MAX_HARQ_PROCESSES) /* TS 38.214 5.1 UE procedure for receiving the physical downlink shared channel */
#endif
#define NR_DEFAULT_DLSCH_HARQ_PROCESSES (8) /* TS 38.214 5.1 */
#define DL_ACKNACK_NO_SET (2)
......
openair1/SCHED_NR_UE/phy_procedures_nr_ue.c
View file @ ce1246e0
......@@ -911,8 +911,8 @@ bool nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
const double N_TA_max = Ta_max * bw_scaling * tc_factor;
NR_UE_MAC_INST_t *mac = get_mac_inst(0);
NR_BWP_Id_t dl_bwp = mac->DL_BWP_Id;
NR_BWP_Id_t ul_bwp = mac->UL_BWP_Id;
NR_BWP_Id_t dl_bwp = mac->current_DL_BWP.bwp_id;
NR_BWP_Id_t ul_bwp = mac->current_UL_BWP.bwp_id;
NR_PUSCH_TimeDomainResourceAllocationList_t *pusch_TimeDomainAllocationList = NULL;
if(ul_bwp){
......
openair1/SIMULATION/NR_PHY/dlsim.c
View file @ ce1246e0
......@@ -434,8 +434,6 @@ int main(int argc, char **argv)
int loglvl=OAILOG_WARNING;
//float target_error_rate = 0.01;
int css_flag=0;
cpuf = get_cpu_freq_GHz();
int8_t enable_ptrs = 0;
int8_t modify_dmrs = 0;
......@@ -463,7 +461,7 @@ int main(int argc, char **argv)
FILE *scg_fd=NULL;
while ((c = getopt(argc, argv, "f:hA:pf:g:i:n:s:S:t:v:x:y:z:M:N:F:GR:d:PI:L:Ea:b:e:m:w:T:U:q:X:Y")) != -1) {
while ((c = getopt(argc, argv, "f:hA:pf:g:i:n:s:S:t:v:x:y:z:M:N:F:GR:d:PI:L:a:b:e:m:w:T:U:q:X:Y")) != -1) {
switch (c) {
case 'f':
scg_fd = fopen(optarg,"r");
......@@ -622,12 +620,6 @@ int main(int argc, char **argv)
loglvl = atoi(optarg);
break;
case 'E':
css_flag=1;
break;
case 'a':
g_rbStart = atoi(optarg);
break;
......@@ -709,7 +701,6 @@ int main(int argc, char **argv)
//printf("-C Generate Calibration information for Abstraction (effective SNR adjustment to remove Pe bias w.r.t. AWGN)\n");
printf("-f raw file containing RRC configuration (generated by gNB)\n");
printf("-F Input filename (.txt format) for RX conformance testing\n");
printf("-E used CSS scheduler\n");
printf("-o CORESET offset\n");
printf("-a Start PRB for PDSCH\n");
printf("-b Number of PRB for PDSCH\n");
......@@ -1122,11 +1113,7 @@ int main(int argc, char **argv)
UE_info->UE_sched_ctrl.harq_processes[harq_pid].ndi = !(trial&1);
UE_info->UE_sched_ctrl.harq_processes[harq_pid].round = round;
if (css_flag == 0) {
nr_schedule_ue_spec(0, frame, slot);
} else {
nr_schedule_css_dlsch_phytest(0,frame,slot);
}
nr_schedule_ue_spec(0, frame, slot);
Sched_INFO.module_id = 0;
Sched_INFO.CC_id = 0;
Sched_INFO.frame = frame;
......
openair2/LAYER2/NR_MAC_COMMON/nr_mac.h
View file @ ce1246e0
......@@ -37,10 +37,8 @@
#include <stdlib.h>
#include <string.h>
#include <stdbool.h>
#include "NR_SubcarrierSpacing.h"
#include "NR_CSI-ReportConfig.h"
#include "openair1/SCHED_NR_UE/harq_nr.h"
#include "common/utils/nr/nr_common.h"
#include "NR_CellGroupConfig.h"
#define NR_SHORT_BSR_TABLE_SIZE 32
#define NR_LONG_BSR_TABLE_SIZE 256
......@@ -567,5 +565,43 @@ typedef struct nr_srs_feedback {
uint8_t tpmi;
} nr_srs_feedback_t;
typedef struct NR_UE_DL_BWP {
NR_BWP_Id_t bwp_id;
int n_dl_bwp;
int scs;
long *cyclicprefix;
uint16_t BWPSize;
uint16_t BWPStart;
uint16_t initial_BWPSize;
uint16_t initial_BWPStart;
NR_PDSCH_TimeDomainResourceAllocationList_t *tdaList;
NR_PDSCH_Config_t *pdsch_Config;
NR_PDSCH_ServingCellConfig_t *pdsch_servingcellconfig;
uint8_t mcsTableIdx;
nr_dci_format_t dci_format;
} NR_UE_DL_BWP_t;
typedef struct NR_UE_UL_BWP {
NR_BWP_Id_t bwp_id;
int n_ul_bwp;
int scs;
long *cyclicprefix;
uint16_t BWPSize;
uint16_t BWPStart;
uint16_t initial_BWPSize;
uint16_t initial_BWPStart;
NR_PUSCH_ServingCellConfig_t *pusch_servingcellconfig;
NR_PUSCH_TimeDomainResourceAllocationList_t *tdaList;
NR_PUSCH_Config_t *pusch_Config;
NR_PUCCH_Config_t *pucch_Config;
NR_PUCCH_ConfigCommon_t *pucch_ConfigCommon;
NR_CSI_MeasConfig_t *csi_MeasConfig;
NR_SRS_Config_t *srs_Config;
uint8_t transform_precoding;
uint8_t mcs_table;
nr_dci_format_t dci_format;
int max_fb_time;
} NR_UE_UL_BWP_t;
#endif /*__LAYER2_MAC_H__ */
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
View file @ ce1246e0
......@@ -3130,16 +3130,45 @@ uint8_t compute_precoding_information(NR_PUSCH_Config_t *pusch_Config,
return nbits;
}
uint16_t get_rb_bwp_dci(nr_dci_format_t format,
int ss_type,
uint16_t cset0_bwp_size,
uint16_t ul_bwp_size,
uint16_t dl_bwp_size,
uint16_t initial_ul_bwp_size,
uint16_t initial_dl_bwp_size)
{
uint16_t N_RB;
if (format == NR_UL_DCI_FORMAT_0_0 || format == NR_UL_DCI_FORMAT_0_1) {
if(format == NR_UL_DCI_FORMAT_0_0 && ss_type == NR_SearchSpace__searchSpaceType_PR_common)
N_RB = initial_ul_bwp_size;
else
N_RB = ul_bwp_size;
}
else {
if(format == NR_DL_DCI_FORMAT_1_0 && ss_type == NR_SearchSpace__searchSpaceType_PR_common) {
N_RB = cset0_bwp_size ? cset0_bwp_size : initial_dl_bwp_size;
}
else
N_RB = dl_bwp_size;
}
return N_RB;
}
uint16_t nr_dci_size(const NR_BWP_DownlinkCommon_t *initialDownlinkBWP,
const NR_BWP_UplinkCommon_t *initialUplinkBWP,
const NR_UE_DL_BWP_t *DL_BWP,
const NR_UE_UL_BWP_t *UL_BWP,
const NR_CellGroupConfig_t *cg,
dci_pdu_rel15_t *dci_pdu,
nr_dci_format_t format,
nr_rnti_type_t rnti_type,
uint16_t N_RB,
int controlResourceSetId,
int bwp_id,
NR_ControlResourceSetId_t coreset_id,
uint16_t cset0_bwp_size) {
int ss_type,
uint16_t cset0_bwp_size,
uint16_t alt_size)
{
uint16_t size = 0;
uint16_t numRBG = 0;
......@@ -3184,20 +3213,28 @@ uint16_t nr_dci_size(const NR_BWP_DownlinkCommon_t *initialDownlinkBWP,
srs_config = (ubwpd && ubwpd->srs_Config) ? ubwpd->srs_Config->choice.setup: NULL;
}
int n_ul_bwp=1,n_dl_bwp=1;
uint16_t N_RB = cset0_bwp_size;
if (DL_BWP)
N_RB = get_rb_bwp_dci(format,
ss_type,
cset0_bwp_size,
UL_BWP->BWPSize,
DL_BWP->BWPSize,
UL_BWP->initial_BWPSize,
DL_BWP->initial_BWPSize);
int n_ul_bwp = 1,n_dl_bwp = 1;
switch(format) {
/*Only sizes for 0_0 and 1_0 are correct at the moment*/
case NR_UL_DCI_FORMAT_0_0:
/// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20
size += 20;
dci_pdu->frequency_domain_assignment.nbits = (uint8_t)ceil(log2((N_RB * (N_RB + 1)) >>1)); // Freq domain assignment -- hopping scenario to be updated
size += dci_pdu->frequency_domain_assignment.nbits;
int dci_10_size = nr_dci_size(initialDownlinkBWP,initialUplinkBWP,cg,dci_pdu,NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB, bwp_id, coreset_id, cset0_bwp_size);
if(dci_10_size >= size)
size += dci_10_size - size; // Padding to match 1_0 size
else {
dci_pdu->frequency_domain_assignment.nbits -= (size - dci_10_size);
size = dci_10_size;
if(alt_size >= size)
size += alt_size - size; // Padding to match 1_0 size
else if (ss_type == NR_SearchSpace__searchSpaceType_PR_common) {
dci_pdu->frequency_domain_assignment.nbits -= (size - alt_size);
size = alt_size;
}
// UL/SUL indicator assumed to be 0
break;
......@@ -3231,17 +3268,16 @@ uint16_t nr_dci_size(const NR_BWP_DownlinkCommon_t *initialDownlinkBWP,
rbg_size_config = 1;
else
rbg_size_config = 0;
numRBG = getNRBG(NRRIV2BW(ubwpc->genericParameters.locationAndBandwidth, MAX_BWP_SIZE),
NRRIV2PRBOFFSET(ubwpc->genericParameters.locationAndBandwidth, MAX_BWP_SIZE),
rbg_size_config);
numRBG = getNRBG(UL_BWP->BWPSize, UL_BWP->BWPStart, rbg_size_config);
if (pusch_Config->resourceAllocation == 0)
dci_pdu->frequency_domain_assignment.nbits = numRBG;
else if (pusch_Config->resourceAllocation == 1)
dci_pdu->frequency_domain_assignment.nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
dci_pdu->frequency_domain_assignment.nbits = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1));
else
dci_pdu->frequency_domain_assignment.nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1;
dci_pdu->frequency_domain_assignment.nbits = ((int)ceil(log2((N_RB * (N_RB + 1)) >> 1)) > numRBG) ? (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)) + 1 : numRBG + 1;
}
else dci_pdu->frequency_domain_assignment.nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
else
dci_pdu->frequency_domain_assignment.nbits = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1));
LOG_D(NR_MAC,"PUSCH Frequency Domain Assignment nbits %d, N_RB %d\n",dci_pdu->frequency_domain_assignment.nbits,N_RB);
size += dci_pdu->frequency_domain_assignment.nbits;
// Time domain assignment
......@@ -3357,14 +3393,11 @@ uint16_t nr_dci_size(const NR_BWP_DownlinkCommon_t *initialDownlinkBWP,
// 3GPP TS 38.212 Section 7.3.1.0: DCI size alignment
// Size of DCI format 1_0 is given by the size of CORESET 0 if CORESET 0 is configured for the cell and the size
// of initial DL bandwidth part if CORESET 0 is not configured for the cell
if(cset0_bwp_size>0) {
N_RB = cset0_bwp_size;
}
size = 28;
size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment
dci_pdu->frequency_domain_assignment.nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
dci_pdu->frequency_domain_assignment.nbits = (uint8_t)ceil(log2((N_RB * (N_RB + 1)) >> 1)); // Freq domain assignment
size += dci_pdu->frequency_domain_assignment.nbits;
if(ss_type == NR_SearchSpace__searchSpaceType_PR_ue_Specific && alt_size >= size)
size += alt_size - size; // Padding to match 0_0 size
dci_pdu->time_domain_assignment.nbits = 4;
dci_pdu->vrb_to_prb_mapping.nbits = 1;
break;
......@@ -3393,15 +3426,13 @@ uint16_t nr_dci_size(const NR_BWP_DownlinkCommon_t *initialDownlinkBWP,
if (pdsch_Config) rbg_size_config = pdsch_Config->rbg_Size;
else rbg_size_config = 0;
numRBG = getNRBG(NRRIV2BW(bwpc->genericParameters.locationAndBandwidth, MAX_BWP_SIZE),
NRRIV2PRBOFFSET(bwpc->genericParameters.locationAndBandwidth, MAX_BWP_SIZE),
rbg_size_config);
numRBG = getNRBG(DL_BWP->BWPSize, DL_BWP->BWPStart, rbg_size_config);
if (pdsch_Config && pdsch_Config->resourceAllocation == 0)
dci_pdu->frequency_domain_assignment.nbits = numRBG;
else if (pdsch_Config == NULL || pdsch_Config->resourceAllocation == 1)
dci_pdu->frequency_domain_assignment.nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
dci_pdu->frequency_domain_assignment.nbits = (int)ceil(log2((N_RB * (N_RB + 1)) >> 1));
else
dci_pdu->frequency_domain_assignment.nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1;
dci_pdu->frequency_domain_assignment.nbits = ((int)ceil(log2((N_RB * (N_RB + 1)) >> 1)) > numRBG) ? (int)ceil(log2((N_RB * (N_RB + 1)) >> 1)) + 1 : numRBG + 1;
size += dci_pdu->frequency_domain_assignment.nbits;
LOG_D(NR_MAC,"dci_pdu->frequency_domain_assignment.nbits %d (N_RB %d)\n",dci_pdu->frequency_domain_assignment.nbits,N_RB);
// Time domain assignment (see table 5.1.2.1.1-1 in 38.214
......@@ -3478,7 +3509,7 @@ uint16_t nr_dci_size(const NR_BWP_DownlinkCommon_t *initialDownlinkBWP,
LOG_D(NR_MAC,"dci_pdu->antenna_ports.nbits %d\n",dci_pdu->antenna_ports.nbits);
// Tx Config Indication
for (int i = 0; i < pdcch_Config->controlResourceSetToAddModList->list.count; i++) {
if (pdcch_Config->controlResourceSetToAddModList->list.array[i]->controlResourceSetId == coreset_id) {
if (pdcch_Config->controlResourceSetToAddModList->list.array[i]->controlResourceSetId == controlResourceSetId) {
long *isTciEnable = pdcch_Config->controlResourceSetToAddModList->list.array[i]->tci_PresentInDCI;
if (isTciEnable != NULL) {
dci_pdu->transmission_configuration_indication.nbits = 3;
......
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h
View file @ ce1246e0
......@@ -43,6 +43,11 @@ typedef enum {
pusch_dmrs_pos3 = 3,
} pusch_dmrs_AdditionalPosition_t;
typedef enum {
pusch_len1 = 1,
pusch_len2 = 2
} pusch_maxLength_t;
typedef enum {
typeA = 0,
typeB = 1
......@@ -75,16 +80,27 @@ uint8_t compute_precoding_information(NR_PUSCH_Config_t *pusch_Config,
const uint8_t *nrOfLayers,
uint32_t *val);
uint16_t nr_dci_size(const NR_BWP_DownlinkCommon_t *initialDLBWP,
const NR_BWP_UplinkCommon_t *initialULBWP,
uint16_t nr_dci_size(const NR_BWP_DownlinkCommon_t *initialDownlinkBWP,
const NR_BWP_UplinkCommon_t *initialUplinkBWP,
const NR_UE_DL_BWP_t *DL_BWP,
const NR_UE_UL_BWP_t *UL_BWP,
const NR_CellGroupConfig_t *cg,
dci_pdu_rel15_t *dci_pdu,
nr_dci_format_t format,
nr_rnti_type_t rnti_type,
uint16_t N_RB,
int controlResourceSetId,
int bwp_id,
NR_ControlResourceSetId_t coreset_id,
uint16_t cset0_bwp_size);
int ss_type,
uint16_t cset0_bwp_size,
uint16_t alt_size);
uint16_t get_rb_bwp_dci(nr_dci_format_t format,
int ss_type,
uint16_t cset0_bwp_size,
uint16_t ul_bwp_size,
uint16_t dl_bwp_size,
uint16_t initial_ul_bwp_size,
uint16_t initial_dl_bwp_size);
void find_aggregation_candidates(uint8_t *aggregation_level,
uint8_t *nr_of_candidates,
......
openair2/LAYER2/NR_MAC_UE/config_ue.c
View file @ ce1246e0
This diff is collapsed.
openair2/LAYER2/NR_MAC_UE/mac_defs.h
View file @ ce1246e0
......@@ -164,6 +164,11 @@ typedef enum {
UE_PHY_HO_PRACH
} NR_UE_L2_STATE_t;
typedef enum {
RA_2STEP = 0,
RA_4STEP
} nr_ra_type_e;
// LTE structure, might need to be adapted for NR
typedef struct {
/// buffer status for each lcgid
......@@ -372,7 +377,6 @@ typedef struct {
} NR_PHY_meas_t;
/*!\brief Top level UE MAC structure */
typedef struct {
......@@ -393,6 +397,9 @@ typedef struct {
NR_RNTI_Value_t *cs_RNTI;
NR_MIB_t *mib;
NR_UE_DL_BWP_t current_DL_BWP;
NR_UE_UL_BWP_t current_UL_BWP;
NR_BWP_Downlink_t *DLbwp[MAX_NUM_BWP_UE];
NR_BWP_Uplink_t *ULbwp[MAX_NUM_BWP_UE];
NR_ControlResourceSet_t *coreset[MAX_NUM_BWP_UE][FAPI_NR_MAX_CORESET_PER_BWP];
......@@ -400,12 +407,6 @@ typedef struct {
frame_type_t frame_type;
/*BWP*/
// dedicated active DL BWP
NR_BWP_Id_t DL_BWP_Id;
// dedicated active UL BWP
NR_BWP_Id_t UL_BWP_Id;
/// Type0-PDCCH seach space
fapi_nr_dl_config_dci_dl_pdu_rel15_t type0_pdcch_dci_config;
uint32_t type0_pdcch_ss_mux_pattern;
......
openair2/LAYER2/NR_MAC_UE/mac_proto.h
View file @ ce1246e0
......@@ -451,12 +451,18 @@ void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pd
void build_ssb_to_ro_map(NR_UE_MAC_INST_t *mac);
void config_bwp_ue(NR_UE_MAC_INST_t *mac, uint32_t *bwp_ind, uint8_t *dci_format);
void configure_ss_coreset(NR_UE_MAC_INST_t *mac,
NR_ServingCellConfig_t *scd,
NR_BWP_Id_t dl_bwp_id);
static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
uint8_t dci_format,
uint8_t dci_size,
uint16_t rnti,
int ss_type,
uint64_t *dci_pdu,
dci_pdu_rel15_t *dci_pdu_rel15);
fapi_nr_ul_config_request_t *get_ul_config_request(NR_UE_MAC_INST_t *mac, int slot);
void fill_ul_config(fapi_nr_ul_config_request_t *ul_config, frame_t frame_tx, int slot_tx, uint8_t pdu_type);
......
openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c
View file @ ce1246e0
......@@ -177,11 +177,11 @@ void init_RA(module_id_t mod_id,
}
}
if (ss_id < 0) {
if (mac->DL_BWP_Id>0) {
ra_ss = mac->DLbwp[mac->DL_BWP_Id-1]->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace;
if (mac->current_DL_BWP.bwp_id>0) {
ra_ss = mac->DLbwp[mac->current_DL_BWP.bwp_id-1]->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace;
if (ra_ss) {
commonSearchSpaceList = mac->DLbwp[mac->DL_BWP_Id-1]->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList;
ss_id = *mac->DLbwp[mac->DL_BWP_Id-1]->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace;
commonSearchSpaceList = mac->DLbwp[mac->current_DL_BWP.bwp_id-1]->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList;
ss_id = *mac->DLbwp[mac->current_DL_BWP.bwp_id-1]->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace;
}
}
}
......@@ -815,7 +815,7 @@ uint8_t nr_ue_get_rach(module_id_t mod_id,
} else if (get_softmodem_params()->nsa) {
uint8_t mac_sdus[MAX_NUM_NR_ULSCH_SEGMENTS_PER_LAYER*1056];
uint8_t mac_sdus[34*1056];
uint16_t sdu_lengths[NB_RB_MAX] = {0};
int TBS_bytes = 848;
int mac_ce_len = 0;
......
openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c
View file @ ce1246e0
This diff is collapsed.
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
View file @ ce1246e0
......@@ -731,8 +731,8 @@ void nr_generate_Msg3_retransmission(module_id_t module_idP, int CC_id, frame_t
uint16_t *vrb_map_UL = &RC.nrmac[module_idP]->common_channels[CC_id].vrb_map_UL[sched_slot * MAX_BWP_SIZE];
const int BWPSize = NRRIV2BW(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
const int BWPStart = NRRIV2PRBOFFSET(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
const int BWPSize = ul_bwp->initial_BWPSize;
const int BWPStart = ul_bwp->initial_BWPStart;
int rbStart = 0;
for (int i = 0; (i < ra->msg3_nb_rb) && (rbStart <= (BWPSize - ra->msg3_nb_rb)); i++) {
......@@ -830,17 +830,18 @@ void nr_generate_Msg3_retransmission(module_id_t module_idP, int CC_id, frame_t
ra->Msg3_tda_id,
ra->msg3_TPC,
1, // Not toggling NDI in msg3 retransmissions
&ra->UL_BWP);
ul_bwp);
fill_dci_pdu_rel15(scc,
ra->CellGroup,
&ra->DL_BWP,
ul_bwp,
dci_pdu,
&uldci_payload,
NR_UL_DCI_FORMAT_0_0,
NR_RNTI_TC,
pusch_pdu->bwp_size,
ul_bwp->bwp_id,
ss,
coreset,
nr_mac->cset0_bwp_size);
......@@ -955,9 +956,8 @@ void nr_get_Msg3alloc(module_id_t module_id,
uint16_t *vrb_map_UL =
&RC.nrmac[module_id]->common_channels[CC_id].vrb_map_UL[ra->Msg3_slot * MAX_BWP_SIZE];
int bwpSize = NRRIV2BW(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
int bwpStart = NRRIV2PRBOFFSET(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
int bwpSize = ul_bwp->initial_BWPSize;
int bwpStart = ul_bwp->initial_BWPStart;
if (bwpSize != ul_bwp->BWPSize || bwpStart != ul_bwp->BWPStart) {
int act_bwp_start = ul_bwp->BWPStart;
int act_bwp_size = ul_bwp->BWPSize;
......@@ -1106,7 +1106,7 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t
nfapi_nr_pusch_pdu_t *pusch_pdu = &future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pusch_pdu;
memset(pusch_pdu, 0, sizeof(nfapi_nr_pusch_pdu_t));
const int ibwp_size = NRRIV2BW(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
const int ibwp_size = ul_bwp->initial_BWPSize;
const int scs = ul_bwp->scs;
const int fh = (ul_bwp->pusch_Config && ul_bwp->pusch_Config->frequencyHopping) ? 1 : 0;
const int startSymbolAndLength = ul_bwp->tdaList->list.array[ra->Msg3_tda_id]->startSymbolAndLength;
......@@ -1153,9 +1153,9 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
long BWPStart = 0;
long BWPSize = 0;
NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config = NULL;
if(*ss->controlResourceSetId!=0) {
if(*ss->controlResourceSetId != 0) {
BWPStart = dl_bwp->BWPStart;
BWPSize = NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
BWPSize = dl_bwp->initial_BWPSize;
} else {
type0_PDCCH_CSS_config = &nr_mac->type0_PDCCH_CSS_config[ra->beam_id];
BWPStart = type0_PDCCH_CSS_config->cset_start_rb;
......@@ -1292,8 +1292,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
pdsch_pdu_rel15->TBSize[0] = TBS;
}
int scc_bwpsize = NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
int bw_tbslbrm = get_dlbw_tbslbrm(scc_bwpsize, ra->CellGroup);
int bw_tbslbrm = get_dlbw_tbslbrm(dl_bwp->initial_BWPSize, ra->CellGroup);
pdsch_pdu_rel15->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(mcsTableIdx,
bw_tbslbrm,
1);
......@@ -1347,12 +1346,13 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
fill_dci_pdu_rel15(scc,
ra->CellGroup,
dl_bwp,
&ra->UL_BWP,
&pdcch_pdu_rel15->dci_pdu[pdcch_pdu_rel15->numDlDci - 1],
&dci_payload,
NR_DL_DCI_FORMAT_1_0,
NR_RNTI_RA,
BWPSize,
dl_bwp->bwp_id,
ss,
coreset,
nr_mac->cset0_bwp_size);
......@@ -1678,8 +1678,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
int x_Overhead = 0;
nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead, pdsch_pdu_rel15->numDmrsCdmGrpsNoData, tb_scaling);
int scc_bwpsize = NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
int bw_tbslbrm = get_dlbw_tbslbrm(scc_bwpsize, ra->CellGroup);
int bw_tbslbrm = get_dlbw_tbslbrm(dl_bwp->initial_BWPSize, ra->CellGroup);
pdsch_pdu_rel15->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(mcsTableIdx,
bw_tbslbrm,
1);
......@@ -1746,12 +1745,13 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
fill_dci_pdu_rel15(scc,
ra->CellGroup,
dl_bwp,
&ra->UL_BWP,
&pdcch_pdu_rel15->dci_pdu[pdcch_pdu_rel15->numDlDci - 1],
&dci_payload,
NR_DL_DCI_FORMAT_1_0,
NR_RNTI_TC,
pdsch_pdu_rel15->BWPSize,
dl_bwp->bwp_id,
ss,
coreset,
nr_mac->cset0_bwp_size);
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c
View file @ ce1246e0
......@@ -494,14 +494,15 @@ void nr_fill_nfapi_dl_sib1_pdu(int Mod_idP,
int rnti_type = NR_RNTI_SI;
fill_dci_pdu_rel15(scc,
NULL,
NULL,
NULL,
&pdcch_pdu_rel15->dci_pdu[pdcch_pdu_rel15->numDlDci - 1],
&dci_payload,
dci_format,
rnti_type,
pdsch_pdu_rel15->BWPSize,
0,
gNB_mac->sched_ctrlCommon->search_space,
gNB_mac->sched_ctrlCommon->coreset,
gNB_mac->cset0_bwp_size);
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
View file @ ce1246e0
......@@ -1012,7 +1012,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
long maxMIMO_Layers = current_BWP->pdsch_servingcellconfig ? *current_BWP->pdsch_servingcellconfig->ext1->maxMIMO_Layers : 1;
const int nl_tbslbrm = min(maxMIMO_Layers, 4);
// Maximum number of PRBs across all configured DL BWPs
int scc_bwpsize = NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
int scc_bwpsize = current_BWP->initial_BWPSize;
int bw_tbslbrm = get_dlbw_tbslbrm(scc_bwpsize, cg);
pdsch_pdu->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(current_BWP->mcsTableIdx,
bw_tbslbrm,
......@@ -1110,12 +1110,13 @@ void nr_schedule_ue_spec(module_id_t module_id,
fill_dci_pdu_rel15(scc,
cg,
current_BWP,
&UE->current_UL_BWP,
dci_pdu,
&dci_payload,
current_BWP->dci_format,
rnti_type,
pdsch_pdu->BWPSize,
bwp_id,
sched_ctrl->search_space,
sched_ctrl->coreset,
gNB_mac->cset0_bwp_size);
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
View file @ ce1246e0
......@@ -55,130 +55,6 @@ extern RAN_CONTEXT_t RC;
//#define ENABLE_MAC_PAYLOAD_DEBUG 1
/*Scheduling of DLSCH with associated DCI in common search space
* current version has only a DCI for type 1 PDCCH for C_RNTI*/
void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
frame_t frameP,
sub_frame_t slotP) {
uint8_t CC_id;
gNB_MAC_INST *nr_mac = RC.nrmac[module_idP];
NR_COMMON_channels_t *cc = &nr_mac->common_channels[0];
nfapi_nr_dl_tti_request_body_t *dl_req;
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu;
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu;
nfapi_nr_pdu_t *TX_req;
uint16_t rnti = 0x1234;
// int time_domain_assignment,k0;
NR_ServingCellConfigCommon_t *scc=cc->ServingCellConfigCommon;
int dlBWP_carrier_bandwidth = NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
/*
int scs = scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.subcarrierSpacing;
int slots_per_frame = 10*(1<<scs);
int FR = *scc->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0] >= 257 ? nr_FR2 : nr_FR1;
*/
for (CC_id=0; CC_id<MAX_NUM_CCs; CC_id++) {
LOG_D(MAC, "Scheduling common search space DCI type 1 dlBWP BW.firstRB %d.%d\n",
dlBWP_carrier_bandwidth,
NRRIV2PRBOFFSET(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE));
dl_req = &nr_mac->DL_req[CC_id].dl_tti_request_body;
dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
memset((void*)dl_tti_pdcch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t));
dl_tti_pdcch_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE;
dl_tti_pdcch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu));
dl_tti_pdsch_pdu = &nr_mac->DL_req[CC_id].dl_tti_request_body.dl_tti_pdu_list[nr_mac->DL_req[CC_id].dl_tti_request_body.nPDUs+1];
memset((void *)dl_tti_pdsch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t));
dl_tti_pdsch_pdu->PDUType = NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE;
dl_tti_pdsch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdsch_pdu));
// nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15;
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15;
pdsch_pdu_rel15->pduBitmap = 0;
pdsch_pdu_rel15->rnti = rnti;
pdsch_pdu_rel15->pduIndex = 0;
// BWP
pdsch_pdu_rel15->BWPSize = NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
pdsch_pdu_rel15->BWPStart = NRRIV2PRBOFFSET(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
pdsch_pdu_rel15->SubcarrierSpacing = scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.subcarrierSpacing;
pdsch_pdu_rel15->CyclicPrefix = 0;
pdsch_pdu_rel15->NrOfCodewords = 1;
int mcsIndex = 9;
pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcsIndex,0);
pdsch_pdu_rel15->qamModOrder[0] = 2;
pdsch_pdu_rel15->mcsIndex[0] = mcsIndex;
pdsch_pdu_rel15->mcsTable[0] = 0;
pdsch_pdu_rel15->rvIndex[0] = 0;
pdsch_pdu_rel15->dataScramblingId = *scc->physCellId;
pdsch_pdu_rel15->nrOfLayers = 1;
pdsch_pdu_rel15->transmissionScheme = 0;
pdsch_pdu_rel15->refPoint = 0; // Point A
pdsch_pdu_rel15->dmrsConfigType = 0; // Type 1 by default for InitialBWP
pdsch_pdu_rel15->dlDmrsScramblingId = *scc->physCellId;
pdsch_pdu_rel15->SCID = 0;
pdsch_pdu_rel15->numDmrsCdmGrpsNoData = 1;
pdsch_pdu_rel15->dmrsPorts = 1;
pdsch_pdu_rel15->resourceAlloc = 1;
pdsch_pdu_rel15->rbStart = 0;
pdsch_pdu_rel15->rbSize = 6;
pdsch_pdu_rel15->VRBtoPRBMapping = 1; // non-interleaved, check if this is ok for initialBWP
// choose shortest PDSCH
int startSymbolAndLength=0;
int StartSymbolIndex=-1,NrOfSymbols=14;
int StartSymbolIndex_tmp,NrOfSymbols_tmp;
int mappingtype_tmp, mappingtype=0;
for (int i=0;
i<scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count;
i++) {
startSymbolAndLength = scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength;
SLIV2SL(startSymbolAndLength,&StartSymbolIndex_tmp,&NrOfSymbols_tmp);
mappingtype_tmp = scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->mappingType;
if (NrOfSymbols_tmp < NrOfSymbols) {
NrOfSymbols = NrOfSymbols_tmp;
StartSymbolIndex = StartSymbolIndex_tmp;
mappingtype = mappingtype_tmp;
}
}
AssertFatal(StartSymbolIndex>=0,"StartSymbolIndex is negative\n");
pdsch_pdu_rel15->StartSymbolIndex = StartSymbolIndex;
pdsch_pdu_rel15->NrOfSymbols = NrOfSymbols;
pdsch_pdu_rel15->dlDmrsSymbPos = fill_dmrs_mask(NULL,
scc->dmrs_TypeA_Position,
NrOfSymbols,
StartSymbolIndex,
mappingtype,
1);
nr_mac->DL_req[CC_id].dl_tti_request_body.nPDUs+=2;
TX_req = &nr_mac->TX_req[CC_id].pdu_list[nr_mac->TX_req[CC_id].Number_of_PDUs];
TX_req->PDU_length = 6;
TX_req->PDU_index = nr_mac->pdu_index[CC_id]++;
TX_req->num_TLV = 1;
TX_req->TLVs[0].length = 8;
// why do we copy from RAR_pdu here? Shouldn't we fill some more or less
// meaningful data, e.g., padding + random data?
//memcpy((void *)&TX_req->TLVs[0].value.direct[0], (void *)&cc[CC_id].RAR_pdu[0].payload[0], TX_req->TLVs[0].length);
nr_mac->TX_req[CC_id].Number_of_PDUs++;
nr_mac->TX_req[CC_id].SFN=frameP;
nr_mac->TX_req[CC_id].Slot=slotP;
}
}
uint32_t target_dl_mcs = 9;
uint32_t target_dl_Nl = 1;
uint32_t target_dl_bw = 50;
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @ ce1246e0
......@@ -1384,28 +1384,62 @@ void prepare_dci(const NR_CellGroupConfig_t *CellGroup,
void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
const NR_CellGroupConfig_t *CellGroup,
const NR_UE_DL_BWP_t *current_BWP,
const NR_UE_DL_BWP_t *current_DL_BWP,
const NR_UE_UL_BWP_t *current_UL_BWP,
nfapi_nr_dl_dci_pdu_t *pdcch_dci_pdu,
dci_pdu_rel15_t *dci_pdu_rel15,
int dci_format,
int rnti_type,
int N_RB,
int bwp_id,
NR_SearchSpace_t *ss,
NR_ControlResourceSet_t *coreset,
uint16_t cset0_bwp_size) {
uint8_t fsize = 0, pos = 0;
uint16_t cset0_bwp_size)
{
uint8_t fsize = 0, pos = 0;
uint64_t *dci_pdu = (uint64_t *)pdcch_dci_pdu->Payload;
*dci_pdu=0;
NR_ControlResourceSetId_t coreset_id = coreset->controlResourceSetId;
*dci_pdu = 0;
uint16_t alt_size = 0;
uint16_t N_RB;
const int controlResourceSetId = *ss->controlResourceSetId;
if(current_DL_BWP) {
N_RB = get_rb_bwp_dci(dci_format,
ss->searchSpaceType->present,
cset0_bwp_size,
current_UL_BWP->BWPSize,
current_DL_BWP->BWPSize,
current_UL_BWP->initial_BWPSize,
current_DL_BWP->initial_BWPSize);
// computing alternative size for padding
dci_pdu_rel15_t temp_pdu;
if(dci_format == NR_DL_DCI_FORMAT_1_0)
alt_size = nr_dci_size(scc->downlinkConfigCommon->initialDownlinkBWP,
scc->uplinkConfigCommon->initialUplinkBWP,
current_DL_BWP, current_UL_BWP,
CellGroup, &temp_pdu, NR_UL_DCI_FORMAT_0_0, rnti_type,
controlResourceSetId, bwp_id, ss->searchSpaceType->present, cset0_bwp_size, 0);
if(dci_format == NR_UL_DCI_FORMAT_0_0)
alt_size = nr_dci_size(scc->downlinkConfigCommon->initialDownlinkBWP,
scc->uplinkConfigCommon->initialUplinkBWP,
current_DL_BWP, current_UL_BWP,
CellGroup, &temp_pdu, NR_DL_DCI_FORMAT_1_0, rnti_type,
controlResourceSetId, bwp_id, ss->searchSpaceType->present, cset0_bwp_size, 0);
}
else
N_RB = cset0_bwp_size;
int dci_size = nr_dci_size(scc->downlinkConfigCommon->initialDownlinkBWP,
scc->uplinkConfigCommon->initialUplinkBWP,
CellGroup, dci_pdu_rel15, dci_format,
rnti_type, N_RB, bwp_id, coreset_id, cset0_bwp_size);
current_DL_BWP, current_UL_BWP,
CellGroup, dci_pdu_rel15, dci_format, rnti_type, controlResourceSetId,
bwp_id, ss->searchSpaceType->present, cset0_bwp_size, alt_size);
pdcch_dci_pdu->PayloadSizeBits = dci_size;
AssertFatal(dci_size <= 64, "DCI sizes above 64 bits not yet supported");
if (dci_format == NR_DL_DCI_FORMAT_1_1 || dci_format == NR_UL_DCI_FORMAT_0_1)
prepare_dci(CellGroup, current_BWP, coreset, dci_pdu_rel15, dci_format);
prepare_dci(CellGroup, current_DL_BWP, coreset, dci_pdu_rel15, dci_format);
/// Payload generation
switch (dci_format) {
......@@ -2389,7 +2423,7 @@ void configure_UE_BWP(gNB_MAC_INST *nr_mac,
UL_BWP->tdaList = scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList;
// setting generic parameters
NR_BWP_t dl_genericParameters = (DL_BWP->bwp_id>0 && dl_bwp) ?
NR_BWP_t dl_genericParameters = (DL_BWP->bwp_id > 0 && dl_bwp) ?
dl_bwp->bwp_Common->genericParameters:
scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters;
......@@ -2397,8 +2431,10 @@ void configure_UE_BWP(gNB_MAC_INST *nr_mac,
DL_BWP->cyclicprefix = dl_genericParameters.cyclicPrefix;
DL_BWP->BWPSize = NRRIV2BW(dl_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
DL_BWP->BWPStart = NRRIV2PRBOFFSET(dl_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
DL_BWP->initial_BWPSize = NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
DL_BWP->initial_BWPStart = NRRIV2PRBOFFSET(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
NR_BWP_t ul_genericParameters = (UL_BWP->bwp_id>0 && ul_bwp) ?
NR_BWP_t ul_genericParameters = (UL_BWP->bwp_id > 0 && ul_bwp) ?
ul_bwp->bwp_Common->genericParameters:
scc->uplinkConfigCommon->initialUplinkBWP->genericParameters;
......@@ -2406,6 +2442,8 @@ void configure_UE_BWP(gNB_MAC_INST *nr_mac,
UL_BWP->cyclicprefix = ul_genericParameters.cyclicPrefix;
UL_BWP->BWPSize = NRRIV2BW(ul_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
UL_BWP->BWPStart = NRRIV2PRBOFFSET(ul_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
UL_BWP->initial_BWPSize = NRRIV2BW(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
UL_BWP->initial_BWPStart = NRRIV2PRBOFFSET(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
// Set downlink MCS table
if (DL_BWP->pdsch_Config &&
......
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
View file @ ce1246e0
......@@ -263,7 +263,7 @@ int nr_process_mac_pdu(instance_t module_idP,
// in sched_ctrl we set normalized PH wrt MCS and PRBs
long *deltaMCS = ul_bwp->pusch_Config ? ul_bwp->pusch_Config->pusch_PowerControl->deltaMCS : NULL;
sched_ctrl->ph = PH +
compute_ph_factor(sched_pusch->mu,
compute_ph_factor(ul_bwp->scs,
sched_pusch->tb_size<<3,
sched_pusch->rbSize,
sched_pusch->nrOfLayers,
......@@ -1758,7 +1758,6 @@ void pf_ul(module_id_t module_id,
/* Calculate the current scheduling bytes */
const int B = cmax(sched_ctrl->estimated_ul_buffer - sched_ctrl->sched_ul_bytes, 0);
/* adjust rbSize and MCS according to PHR and BPRE */
sched_pusch->mu = scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.subcarrierSpacing;
if(sched_ctrl->pcmax!=0 ||
sched_ctrl->ph!=0) // verify if the PHR related parameter have been initialized
nr_ue_max_mcs_min_rb(current_BWP->scs, sched_ctrl->ph, sched_pusch, current_BWP, min_rb, B, &max_rbSize, &sched_pusch->mcs);
......@@ -2163,7 +2162,7 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
if (!maxMIMO_Layers)
maxMIMO_Layers = current_BWP->pusch_Config->maxRank;
AssertFatal (maxMIMO_Layers != NULL,"Option with max MIMO layers not configured is not supported\n");
const int scc_bwpsize = NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
const int scc_bwpsize = current_BWP->initial_BWPSize;
int bw_tbslbrm = get_ulbw_tbslbrm(scc_bwpsize, cg);
pusch_pdu->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(current_BWP->mcs_table,
bw_tbslbrm,
......@@ -2261,12 +2260,13 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
fill_dci_pdu_rel15(scc,
cg,
&UE->current_DL_BWP,
current_BWP,
dci_pdu,
&uldci_payload,
current_BWP->dci_format,
rnti_types[0],
pusch_pdu->bwp_size,
current_BWP->bwp_id,
ss,
coreset,
nr_mac->cset0_bwp_size);
......
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
View file @ ce1246e0
......@@ -171,10 +171,6 @@ void nr_preprocessor_phytest(module_id_t module_id,
* fixed set of resources */
bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_t slot);
void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
frame_t frameP,
sub_frame_t subframeP);
void handle_nr_uci_pucch_0_1(module_id_t mod_id,
frame_t frame,
sub_frame_t slot,
......@@ -289,13 +285,14 @@ void fill_pdcch_vrb_map(gNB_MAC_INST *mac,
void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
const NR_CellGroupConfig_t *CellGroup,
const NR_UE_DL_BWP_t *dl_bwp,
const NR_UE_DL_BWP_t *current_DL_BWP,
const NR_UE_UL_BWP_t *current_UL_BWP,
nfapi_nr_dl_dci_pdu_t *pdcch_dci_pdu,
dci_pdu_rel15_t *dci_pdu_rel15,
int dci_formats,
int rnti_types,
int N_RB,
int dci_format,
int rnti_type,
int bwp_id,
NR_SearchSpace_t *ss,
NR_ControlResourceSet_t *coreset,
uint16_t cset0_bwp_size);
......
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
View file @ ce1246e0
......@@ -92,40 +92,6 @@ typedef struct {
int len;
} NR_list_t;
typedef struct NR_UE_DL_BWP {
NR_BWP_Id_t bwp_id;
int n_dl_bwp;
int scs;
long *cyclicprefix;
uint16_t BWPSize;
uint16_t BWPStart;
NR_PDSCH_TimeDomainResourceAllocationList_t *tdaList;
NR_PDSCH_Config_t *pdsch_Config;
NR_PDSCH_ServingCellConfig_t *pdsch_servingcellconfig;
uint8_t mcsTableIdx;
nr_dci_format_t dci_format;
} NR_UE_DL_BWP_t;
typedef struct NR_UE_UL_BWP {
NR_BWP_Id_t bwp_id;
int n_ul_bwp;
int scs;
long *cyclicprefix;
uint16_t BWPSize;
uint16_t BWPStart;
NR_PUSCH_ServingCellConfig_t *pusch_servingcellconfig;
NR_PUSCH_TimeDomainResourceAllocationList_t *tdaList;
NR_PUSCH_Config_t *pusch_Config;
NR_PUCCH_Config_t *pucch_Config;
NR_PUCCH_ConfigCommon_t *pucch_ConfigCommon;
NR_CSI_MeasConfig_t *csi_MeasConfig;
NR_SRS_Config_t *srs_Config;
uint8_t transform_precoding;
uint8_t mcs_table;
nr_dci_format_t dci_format;
int max_fb_time;
} NR_UE_UL_BWP_t;
typedef enum {
RA_IDLE = 0,
Msg2 = 1,
......
openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c
View file @ ce1246e0
......@@ -638,41 +638,35 @@ static void copy_ul_tti_data_req_to_dl_info(nr_downlink_indication_t *dl_info, n
static void fill_dci_from_dl_config(nr_downlink_indication_t*dl_ind, fapi_nr_dl_config_request_t *dl_config)
{
if (!dl_ind->dci_ind)
{
return;
}
AssertFatal(dl_config->number_pdus < sizeof(dl_config->dl_config_list) / sizeof(dl_config->dl_config_list[0]),
"Too many dl_config pdus %d", dl_config->number_pdus);
for (int i = 0; i < dl_config->number_pdus; i++)
{
for (int i = 0; i < dl_config->number_pdus; i++) {
LOG_D(PHY, "In %s: filling DCI with a total of %d total DL PDUs (dl_config %p) \n",
__FUNCTION__, dl_config->number_pdus, dl_config);
fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15_dci = &dl_config->dl_config_list[i].dci_config_pdu.dci_config_rel15;
int num_dci_options = rel15_dci->num_dci_options;
if (num_dci_options <= 0)
{
LOG_D(NR_MAC, "num_dci_opts = %d for pdu[%d] in dl_config_list\n", rel15_dci->num_dci_options, i);
}
AssertFatal(num_dci_options <= sizeof(rel15_dci->dci_length_options) / sizeof(rel15_dci->dci_length_options[0]),
"num_dci_options %d > dci_length_options array\n", num_dci_options);
AssertFatal(num_dci_options <= sizeof(rel15_dci->dci_format_options) / sizeof(rel15_dci->dci_format_options[0]),
"num_dci_options %d > dci_format_options array\n", num_dci_options);
for (int j = 0; j < num_dci_options; j++)
{
for (int j = 0; j < num_dci_options; j++) {
int num_dcis = dl_ind->dci_ind->number_of_dcis;
AssertFatal(num_dcis <= sizeof(dl_ind->dci_ind->dci_list) / sizeof(dl_ind->dci_ind->dci_list[0]),
"dl_config->number_pdus %d > dci_ind->dci_list array\n", num_dcis);
for (int k = 0; k < num_dcis; k++)
{
for (int k = 0; k < num_dcis; k++) {
LOG_T(NR_PHY, "Received len %d, length options[%d] %d, format assigned %d, format options[%d] %d\n",
dl_ind->dci_ind->dci_list[k].payloadSize, j, rel15_dci->dci_length_options[j],
dl_ind->dci_ind->dci_list[k].dci_format, j, rel15_dci->dci_format_options[j]);
if (rel15_dci->dci_length_options[j] == dl_ind->dci_ind->dci_list[k].payloadSize)
{
if (rel15_dci->dci_length_options[j] == dl_ind->dci_ind->dci_list[k].payloadSize) {
dl_ind->dci_ind->dci_list[k].dci_format = rel15_dci->dci_format_options[j];
dl_ind->dci_ind->dci_list[k].ss_type = rel15_dci->dci_type_options[j];
LOG_D(NR_PHY, "format assigned dl_ind->dci_ind->dci_list[k].dci_format %d\n",
dl_ind->dci_ind->dci_list[k].dci_format);
}
......
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