dci_tools.c 143 KB
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/*******************************************************************************

  Eurecom OpenAirInterface
  Copyright(c) 1999 - 2011 Eurecom

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.


  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information
  Openair Admin: openair_admin@eurecom.fr
  Openair Tech : openair_tech@eurecom.fr
  Forums       : http://forums.eurecom.fsr/openairinterface
  Address      : Eurecom, 2229, route des crêtes, 06560 Valbonne Sophia Antipolis, France

*******************************************************************************/

/*! \file PHY/LTE_TRANSPORT/dci_tools.c
 * \brief PHY Support routines (eNB/UE) for filling PDSCH/PUSCH/DLSCH/ULSCH data structures based on DCI PDUs generated by eNB MAC scheduler. 
 * \author R. Knopp
 * \date 2011
 * \version 0.1
 * \company Eurecom
 * \email: knopp@eurecom.fr
 * \note
 * \warning
 */
#include "PHY/defs.h"
#include "PHY/extern.h"
#include "SCHED/defs.h"
#include "MAC_INTERFACE/defs.h"
#include "MAC_INTERFACE/extern.h"
#ifdef DEBUG_DCI_TOOLS
#include "PHY/vars.h"
#endif

//#define DEBUG_DCI

uint32_t  localRIV2alloc_LUT6[32];
uint32_t  distRIV2alloc_LUT6[32];
uint16_t RIV2nb_rb_LUT6[32];
uint16_t RIV2first_rb_LUT6[32];
uint16_t RIV_max6=0;

uint32_t  localRIV2alloc_LUT25[512];
uint32_t  distRIV2alloc_LUT25[512];
uint16_t RIV2nb_rb_LUT25[512];
uint16_t RIV2first_rb_LUT25[512];
uint16_t RIV_max25=0;


uint32_t  localRIV2alloc_LUT50_0[1600];
uint32_t  distRIV2alloc_LUT50_0[1600];
uint32_t  localRIV2alloc_LUT50_1[1600];
uint32_t  distRIV2alloc_LUT50_1[1600];
uint16_t RIV2nb_rb_LUT50[1600];
uint16_t RIV2first_rb_LUT50[1600];
uint16_t RIV_max50=0;

uint32_t  localRIV2alloc_LUT100_0[6000];
uint32_t  distRIV2alloc_LUT100_0[6000];
uint32_t  localRIV2alloc_LUT100_1[6000];
uint32_t  distRIV2alloc_LUT100_1[6000];
uint32_t  localRIV2alloc_LUT100_2[6000];
uint32_t  distRIV2alloc_LUT100_2[6000];
uint32_t  localRIV2alloc_LUT100_3[6000];
uint32_t  distRIV2alloc_LUT100_3[6000];
uint16_t RIV2nb_rb_LUT100[6000];
uint16_t RIV2first_rb_LUT100[6000];
uint16_t RIV_max100=0;


extern uint32_t current_dlsch_cqi;

// Table 8.6.3-3 36.213
uint16_t beta_cqi[16] = {0,   //reserved
			 0,   //reserved
			 9,   //1.125
			 10,  //1.250
			 11,  //1.375
			 13,  //1.625
			 14,  //1.750
			 16,  //2.000
			 18,  //2.250
			 20,  //2.500
			 23,  //2.875
			 25,  //3.125
			 28,  //3.500
			 32,  //4.000
			 40,  //5.000
			 50}; //6.250

// Table 8.6.3-2 36.213
uint16_t beta_ri[16] = {10,   //1.250
			13,   //1.625
			16,   //2.000
			20,   //2.500
			25,   //3.125
			32,   //4.000
			40,   //5.000
			50,   //6.250
			64,   //8.000
			80,   //10.000
			101,  //12.625
			127,  //15.875
			160,  //20.000
			0,    //reserved 
			0,    //reserved
			0};   //reserved

// Table 8.6.3-2 36.213
uint16_t beta_ack[16] = {16,  //2.000
			 20,  //2.500
			 25,  //3.125
			 32,  //4.000
			 40,  //5.000
			 50,  //6.250
			 64,  //8.000
			 80,  //10.000
			 101, //12.625
			 127, //15.875
			 160, //20.000
			 248, //31.000
			 400, //50.000
			 640, //80.000
			 808};//126.00

int8_t delta_PUSCH_abs[4] = {-4,-1,1,4};
int8_t delta_PUSCH_acc[4] = {-1,0,1,3};

int8_t *delta_PUCCH_lut = delta_PUSCH_acc;
		    
void conv_rballoc(uint8_t ra_header,uint32_t rb_alloc,uint32_t N_RB_DL,uint32_t *rb_alloc2) {

  uint32_t i,shift,subset;
  rb_alloc2[0] = 0; rb_alloc2[1] = 0; rb_alloc2[2] = 0; rb_alloc2[3] = 0;

  //  printf("N_RB_DL %d, ra_header %d, rb_alloc %x\n",N_RB_DL,ra_header,rb_alloc);

  switch (N_RB_DL) {

  case 6:
    rb_alloc2[0] = rb_alloc&0x3f;
    break;

  case 25:
    if (ra_header == 0) {// Type 0 Allocation
      
      for (i=12;i>0;i--) {
          if ((rb_alloc&(1<<i)) != 0)
              rb_alloc2[0] |= (3<<((2*(12-i))));
          //      printf("rb_alloc2 (type 0) %x\n",rb_alloc2);
      }
      if ((rb_alloc&1) != 0)
          rb_alloc2[0] |= (1<<24);
    }
    else {
      subset = rb_alloc&1;
      shift  = (rb_alloc>>1)&1;
      for (i=0;i<11;i++) {
	if ((rb_alloc&(1<<(i+2))) != 0)
	  rb_alloc2[0] |= (1<<(2*i));
	//printf("rb_alloc2 (type 1) %x\n",rb_alloc2);
      }
      if ((shift == 0) && (subset == 1))
	rb_alloc2[0]<<=1;
      else if ((shift == 1) && (subset == 0))
	rb_alloc2[0]<<=4;
      else if ((shift == 1) && (subset == 1))
	rb_alloc2[0]<<=3;
    }
    break;
  case 50:
    if (ra_header == 0) {// Type 0 Allocation

      for (i=16; i>0; i--) {
        if ((rb_alloc&(1<<i)) != 0)
          rb_alloc2[(3*(16-i))>>5] |= (7<<((3*(16-i))%32));
      }
      /*
      for (i=1;i<=16;i++) {
        if ((rb_alloc&(1<<(16-i))) != 0) 
          rb_alloc2[(3*i)>>5] |= (7<<((3*i)%32));
      }
      */
      // bit mask across 
      if ((rb_alloc2[0]>>31)==1)
        rb_alloc2[1] |= 1;
      if ((rb_alloc&1) != 0)
          rb_alloc2[1] |= (3<<16);
      /*      
      for (i=0;i<16;i++) {
	if (((rb_alloc>>(16-i))&1) != 0)
	  rb_alloc2[(3*i)>>5] |= (7<<((3*i)%32));
	if ((i==10)&&((rb_alloc&(1<<6))!=0))
	  rb_alloc2[1] = 1;
	//	printf("rb_alloc2[%d] (type 0) %x ((%x>>%d)&1=%d)\n",(3*i)>>5,rb_alloc2[(3*i)>>5],rb_alloc,i,(rb_alloc>>i)&1);

      }
      // fill in 2 from last bit instead of 3
      if ((rb_alloc&1) != 0)
	rb_alloc2[1] |= (3<<i);
      //    printf("rb_alloc2[%d] (type 0) %x ((%x>>%d)&1=%d)\n",(3*i)>>5,rb_alloc2[(3*i)>>5],rb_alloc,i,(rb_alloc>>i)&1);
      */
218
      //      printf("rb_alloc[1]=%x,rb_alloc[0]=%x\n",rb_alloc2[1],rb_alloc2[0]);
219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576
    }
    else {
      LOG_E(PHY,"resource type 1 not supported for  N_RB_DL=100\n");
      exit(-1);
      /*
	subset = rb_alloc&1;
	shift  = (rb_alloc>>1)&1;
	for (i=0;i<11;i++) {
	if ((rb_alloc&(1<<(i+2))) != 0)
	rb_alloc2 |= (1<<(2*i));
	//      printf("rb_alloc2 (type 1) %x\n",rb_alloc2);
	}
	if ((shift == 0) && (subset == 1))
	rb_alloc2<<=1;
	else if ((shift == 1) && (subset == 0))
	rb_alloc2<<=4;
	else if ((shift == 1) && (subset == 1))
	rb_alloc2<<=3;
      */
    }
    break;

  case 100:
    if (ra_header == 0) {// Type 0 Allocation
      for (i=0;i<25;i++) {
	if ((rb_alloc&(1<<(24-i))) != 0)
	  rb_alloc2[(4*i)>>5] |= (0xf<<((4*i)%32));
	//	printf("rb_alloc2[%d] (type 0) %x (%d)\n",(4*i)>>5,rb_alloc2[(4*i)>>5],rb_alloc&(1<<i));
      }
    }
    else {
      LOG_E(PHY,"resource type 1 not supported for  N_RB_DL=100\n");
      exit(-1);
      /*
	subset = rb_alloc&1;
	shift  = (rb_alloc>>1)&1;
	for (i=0;i<11;i++) {
	if ((rb_alloc&(1<<(i+2))) != 0)
	rb_alloc2 |= (1<<(2*i));
	//      printf("rb_alloc2 (type 1) %x\n",rb_alloc2);
	}
	if ((shift == 0) && (subset == 1))
	rb_alloc2<<=1;
	else if ((shift == 1) && (subset == 0))
	rb_alloc2<<=4;
	else if ((shift == 1) && (subset == 1))
	rb_alloc2<<=3;
      */
    }
    break;

  default:
    break;
  }

}



uint32_t conv_nprb(uint8_t ra_header,uint32_t rb_alloc,int N_RB_DL) {

  uint32_t nprb=0,i;

  switch (N_RB_DL) {
  case 6:
    for (i=0;i<6;i++) {
      if ((rb_alloc&(1<<i)) != 0)
	nprb += 1;
    }
    break;
  case 25:
    if (ra_header == 0) {// Type 0 Allocation
      
        for (i=12;i>0;i--) {
            if ((rb_alloc&(1<<i)) != 0)
                nprb += 2;
        }
        if ((rb_alloc&1) != 0)
            nprb += 1;
    }
    else {
      for (i=0;i<11;i++) {
	if ((rb_alloc&(1<<(i+2))) != 0)
	  nprb += 1;
      }
    }
    break;
  case 50:
    if (ra_header == 0) {// Type 0 Allocation
            
      for (i=0;i<16;i++) {
	if ((rb_alloc&(1<<(16-i))) != 0)
	  nprb += 3;
      }
      if ((rb_alloc&1) != 0)
	nprb += 2;

    }
    else {
      for (i=0;i<17;i++) {
	if ((rb_alloc&(1<<(i+2))) != 0)
	  nprb += 1;
      }
    }
    break;
  case 100:
    if (ra_header == 0) {// Type 0 Allocation
      
      for (i=0;i<25;i++) {
	if ((rb_alloc&(1<<(24-i))) != 0)
	  nprb += 4;
      }
    }
    else {
      for (i=0;i<25;i++) {
	if ((rb_alloc&(1<<(i+2))) != 0)
	  nprb += 1;
      }
    }
    break;
  }

  return(nprb);
}

uint16_t computeRIV(uint16_t N_RB_DL,uint16_t RBstart,uint16_t Lcrbs) {

    uint16_t RIV;
    
    if (Lcrbs<=(1+(N_RB_DL>>1)))
        RIV = (N_RB_DL*(Lcrbs-1)) + RBstart;
    else
        RIV = (N_RB_DL*(N_RB_DL+1-Lcrbs)) + (N_RB_DL-1-RBstart);
    
    return(RIV);
}

int dist6[6]={0,2,3,5,1,4};
int dist50[50]={};
int dist100[100]={};

void generate_RIV_tables() {

  // 6RBs localized RIV
  uint8_t Lcrbs,RBstart;
  uint8_t distpos;
  uint16_t RIV;
  uint32_t alloc0,alloc_dist0;
  uint32_t alloc1,alloc_dist1;
  uint32_t alloc2,alloc_dist2;
  uint32_t alloc3,alloc_dist3;

  for (RBstart=0;RBstart<6;RBstart++) {
    alloc0 = 0;
    alloc_dist0 = 0;
    for (Lcrbs=1;Lcrbs<=(6-RBstart);Lcrbs++) {
      //printf("RBstart %d, len %d --> ",RBstart,Lcrbs);
      alloc0 |= (1<<(RBstart+Lcrbs-1));
      // This is the RB<->VRB relationship for N_RB_DL=25
      alloc_dist0 |= (1<<dist6[RBstart+Lcrbs-1]);

      RIV=computeRIV(6,RBstart,Lcrbs);
      if (RIV>RIV_max6)
	RIV_max6 = RIV;

      //      printf("RIV %d (%d) : first_rb %d NBRB %d\n",RIV,localRIV2alloc_LUT25[RIV],RBstart,Lcrbs);
      localRIV2alloc_LUT6[RIV] = alloc0;
      distRIV2alloc_LUT6[RIV]  = alloc_dist0;
      RIV2nb_rb_LUT6[RIV]      = Lcrbs;
      RIV2first_rb_LUT6[RIV]   = RBstart;
    }
  }


  for (RBstart=0;RBstart<25;RBstart++) {
      alloc0 = 0;
      alloc_dist0 = 0;
      for (Lcrbs=1;Lcrbs<=(25-RBstart);Lcrbs++) {
          //      printf("RBstart %d, len %d --> ",RBstart,Lcrbs);
          alloc0 |= (1<<(RBstart+Lcrbs-1));
          // This is the RB<->VRB relationship for N_RB_DL=25
          distpos = ((RBstart+Lcrbs-1)*6)%23;
          if (distpos == 0)
              distpos = 23;
          alloc_dist0 |= (1<<distpos);
          
          RIV=computeRIV(25,RBstart,Lcrbs);
          if (RIV>RIV_max25)
              RIV_max25 = RIV;
          
          //      printf("RIV %d (%d) : first_rb %d NBRB %d\n",RIV,localRIV2alloc_LUT25[RIV],RBstart,Lcrbs);
          localRIV2alloc_LUT25[RIV] = alloc0;
          distRIV2alloc_LUT25[RIV]  = alloc_dist0;
          RIV2nb_rb_LUT25[RIV]      = Lcrbs;
          RIV2first_rb_LUT25[RIV]   = RBstart;
      }
  }


  for (RBstart=0;RBstart<50;RBstart++) {
    alloc0 = 0;
    alloc_dist0 = 0;
    alloc1 = 0;
    alloc_dist1 = 0;
    for (Lcrbs=1;Lcrbs<=(50-RBstart);Lcrbs++) {
      //      printf("RBstart %d, len %d --> ",RBstart,Lcrbs);

      if ((RBstart+Lcrbs-1)<32)
	alloc0 |= (1<<(RBstart+Lcrbs-1));
      else
	alloc1 |= (1<<(RBstart+Lcrbs-33));

      if (dist50[RBstart+Lcrbs-1]<32)
	alloc_dist0 |= (1<<dist50[RBstart+Lcrbs-1]);
      else
	alloc_dist1 |= (1<<dist50[RBstart+Lcrbs-33]);

      RIV=computeRIV(50,RBstart,Lcrbs);
      if (RIV>RIV_max50)
	RIV_max50 = RIV;

      //      printf("RIV %d : first_rb %d NBRB %d\n",RIV,RBstart,Lcrbs);
      localRIV2alloc_LUT50_0[RIV] = alloc0;
      localRIV2alloc_LUT50_1[RIV] = alloc1;
      distRIV2alloc_LUT50_0[RIV]  = alloc_dist0;
      distRIV2alloc_LUT50_1[RIV]  = alloc_dist1;
      RIV2nb_rb_LUT50[RIV]        = Lcrbs;
      RIV2first_rb_LUT50[RIV]     = RBstart;
    }
  }


  for (RBstart=0;RBstart<100;RBstart++) {
    alloc0 = 0;
    alloc_dist0 = 0;
    alloc1 = 0;
    alloc_dist1 = 0;
    alloc2 = 0;
    alloc_dist2 = 0;
    alloc3 = 0;
    alloc_dist3 = 0;

    for (Lcrbs=1;Lcrbs<=(100-RBstart);Lcrbs++) {

      if ((RBstart+Lcrbs-1)<32)
	alloc0 |= (1<<(RBstart+Lcrbs-1));
      else if ((RBstart+Lcrbs-1)<64)
	alloc1 |= (1<<(RBstart+Lcrbs-33));
      else if ((RBstart+Lcrbs-1)<96)
	alloc2 |= (1<<(RBstart+Lcrbs-65));
      else
	alloc3 |= (1<<(RBstart+Lcrbs-97));

      if (dist100[RBstart+Lcrbs-1]<32)
	alloc_dist0 |= (1<<dist100[RBstart+Lcrbs-1]);
      else if (dist100[RBstart+Lcrbs-1]<64)
	alloc_dist1 |= (1<<dist100[RBstart+Lcrbs-33]);
      else if (dist100[RBstart+Lcrbs-1]<64)
	alloc_dist2 |= (1<<dist100[RBstart+Lcrbs-65]);
      else
	alloc_dist3 |= (1<<dist100[RBstart+Lcrbs-97]);

      RIV=computeRIV(100,RBstart,Lcrbs);
      if (RIV>RIV_max100)
	RIV_max100 = RIV;

      //      printf("RIV %d : first_rb %d NBRB %d\n",RIV,RBstart,Lcrbs);
      localRIV2alloc_LUT100_0[RIV] = alloc0;
      distRIV2alloc_LUT100_0[RIV]  = alloc_dist0;
      localRIV2alloc_LUT100_1[RIV] = alloc1;
      distRIV2alloc_LUT100_1[RIV]  = alloc_dist1;
      localRIV2alloc_LUT100_2[RIV] = alloc2;
      distRIV2alloc_LUT100_2[RIV]  = alloc_dist2;
      localRIV2alloc_LUT100_3[RIV] = alloc3;
      distRIV2alloc_LUT100_3[RIV]  = alloc_dist3;
      RIV2nb_rb_LUT100[RIV]      = Lcrbs;
      RIV2first_rb_LUT100[RIV]   = RBstart;
    }
  }
}

// Ngap = 3, N_VRB_DL=6, P=1, N_row=2, N_null=4*2-6=2
// permutation for even slots :
//    n_PRB'(0,2,4) = (0,1,2), n_PRB'(1,3,5) = (4,5,6)
//    n_PRB''(0,1,2,3) = (0,2,4,6)
//    => n_tilde_PRB(5) = (4)
//       n_tilde_PRB(4) = (1)
//       n_tilde_PRB(2,3) = (3,5)
//       n_tilde_PRB(0,1) = (0,2)


 
uint32_t get_rballoc(uint8_t vrb_type,uint16_t rb_alloc_dci) {

  if (vrb_type == 0)
    return(localRIV2alloc_LUT25[rb_alloc_dci]);
  else
    return(distRIV2alloc_LUT25[rb_alloc_dci]);

}

uint8_t get_transmission_mode(uint16_t Mod_id, uint16_t rnti) {
  unsigned char UE_id;

  // find the UE_index corresponding to rnti
  UE_id = find_ue(rnti,PHY_vars_eNB_g[Mod_id]);

  return(PHY_vars_eNB_g[Mod_id]->transmission_mode[UE_id]);
}

int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
				       void *dci_pdu,
				       uint16_t rnti,
				       DCI_format_t dci_format,
				       LTE_eNB_DLSCH_t **dlsch,
				       LTE_DL_FRAME_PARMS *frame_parms,
				       PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated,
				       uint16_t si_rnti,
				       uint16_t ra_rnti,
				       uint16_t p_rnti,
				       uint16_t DL_pmi_single) {

  uint8_t harq_pid;
  uint32_t rballoc,RIV_max;
  uint8_t NPRB,tbswap,tpmi=0;
  LTE_eNB_DLSCH_t *dlsch0=NULL,*dlsch1;
  uint8_t frame_type=frame_parms->frame_type;
  uint8_t vrb_type=0;
  uint8_t mcs=0;
  uint8_t I_mcs = 0;
  uint8_t rv=0;
  uint8_t ndi=0;
  uint8_t rah=0;
  uint8_t TPC=0;
  //   printf("Generate eNB DCI, format %d, rnti %x (pdu %p)\n",dci_format,rnti,dci_pdu);

  switch (dci_format) {

  case format0:
    return(-1);
    break;
  case format1A:  // This is DLSCH allocation for control traffic

 

    dlsch[0]->subframe_tx[subframe] = 1;

    switch (frame_parms->N_RB_DL) {
    case 6:
      if (frame_type == TDD) {
	vrb_type = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
	mcs      = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
	rballoc  = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
	rv       = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rv;
	ndi      = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->ndi;
	TPC      = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->TPC; 
	harq_pid = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid;

577
	//	      printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157
      }
      else {
	vrb_type = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->vrb_type;
	mcs      = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->mcs;
	rballoc  = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rv;
	ndi      = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->ndi;
	TPC      = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->TPC; 
	harq_pid = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->harq_pid;

	//      printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }
      
      if (vrb_type == 0)
	dlsch[0]->rb_alloc[0]                       = localRIV2alloc_LUT6[rballoc];
      else
	dlsch[0]->rb_alloc[0]                       = distRIV2alloc_LUT6[rballoc];
      
      dlsch[0]->nb_rb                               = RIV2nb_rb_LUT6[rballoc];//NPRB;
      RIV_max = RIV_max6;

      
      break;
    case 25:
      if (frame_type == TDD) {
	vrb_type = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
	mcs      = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
	rballoc  = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
	rv       = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rv;
	ndi      = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->ndi;
	TPC      = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->TPC; 
	harq_pid = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid;

	//      printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }
      else {
	vrb_type = ((DCI1A_5MHz_FDD_t *)dci_pdu)->vrb_type;
	mcs      = ((DCI1A_5MHz_FDD_t *)dci_pdu)->mcs;
	rballoc  = ((DCI1A_5MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1A_5MHz_FDD_t *)dci_pdu)->rv;
	ndi      = ((DCI1A_5MHz_FDD_t *)dci_pdu)->ndi;
	TPC      = ((DCI1A_5MHz_FDD_t *)dci_pdu)->TPC; 
	harq_pid = ((DCI1A_5MHz_FDD_t *)dci_pdu)->harq_pid;

	//      printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }

      if (vrb_type == 0)
	dlsch[0]->rb_alloc[0]                       = localRIV2alloc_LUT25[rballoc];
      else
	dlsch[0]->rb_alloc[0]                       = distRIV2alloc_LUT25[rballoc];
      
      dlsch[0]->nb_rb                               = RIV2nb_rb_LUT25[rballoc];//NPRB;
      RIV_max = RIV_max25;      
      break;
    case 50:
      if (frame_type == TDD) {
	vrb_type = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
	mcs      = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->mcs;
	rballoc  = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rballoc;
	rv       = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rv;
	ndi      = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->ndi;
	TPC      = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->TPC; 
	harq_pid = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->harq_pid;

	//      printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }
      else {
	vrb_type = ((DCI1A_10MHz_FDD_t *)dci_pdu)->vrb_type;
	mcs      = ((DCI1A_10MHz_FDD_t *)dci_pdu)->mcs;
	rballoc  = ((DCI1A_10MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1A_10MHz_FDD_t *)dci_pdu)->rv;
	ndi      = ((DCI1A_10MHz_FDD_t *)dci_pdu)->ndi;
	TPC      = ((DCI1A_10MHz_FDD_t *)dci_pdu)->TPC; 
	harq_pid = ((DCI1A_10MHz_FDD_t *)dci_pdu)->harq_pid;
	//      printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }

      if (vrb_type == 0) {
	dlsch[0]->rb_alloc[0]                       = localRIV2alloc_LUT50_0[rballoc];
	dlsch[0]->rb_alloc[1]                       = localRIV2alloc_LUT50_1[rballoc];
      }
      else {
	dlsch[0]->rb_alloc[0]                       = distRIV2alloc_LUT50_0[rballoc];
	dlsch[0]->rb_alloc[1]                       = distRIV2alloc_LUT50_1[rballoc];
      }
      dlsch[0]->nb_rb                               = RIV2nb_rb_LUT50[rballoc];//NPRB;
      RIV_max = RIV_max50;
      break;
    case 100:
      if (frame_type == TDD) {
	vrb_type = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
	mcs      = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->mcs;
	rballoc  = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->rballoc;
	rv       = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->rv;
	ndi      = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->ndi;
	TPC      = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->TPC; 
	harq_pid = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
	//      printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }
      else {
	vrb_type = ((DCI1A_20MHz_FDD_t *)dci_pdu)->vrb_type;
	mcs      = ((DCI1A_20MHz_FDD_t *)dci_pdu)->mcs;
	rballoc  = ((DCI1A_20MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1A_20MHz_FDD_t *)dci_pdu)->rv;
	ndi      = ((DCI1A_20MHz_FDD_t *)dci_pdu)->ndi;
	TPC      = ((DCI1A_20MHz_FDD_t *)dci_pdu)->TPC; 
	harq_pid = ((DCI1A_20MHz_FDD_t *)dci_pdu)->harq_pid;
	//      printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }

      if (vrb_type == 0) {
	dlsch[0]->rb_alloc[0]                       = localRIV2alloc_LUT100_0[rballoc];
	dlsch[0]->rb_alloc[1]                       = localRIV2alloc_LUT100_1[rballoc];
	dlsch[0]->rb_alloc[2]                       = localRIV2alloc_LUT100_2[rballoc];
	dlsch[0]->rb_alloc[3]                       = localRIV2alloc_LUT100_3[rballoc];
      }
      else {
	dlsch[0]->rb_alloc[0]                       = distRIV2alloc_LUT100_0[rballoc];
	dlsch[0]->rb_alloc[1]                       = distRIV2alloc_LUT100_1[rballoc];
	dlsch[0]->rb_alloc[2]                       = distRIV2alloc_LUT100_2[rballoc];
	dlsch[0]->rb_alloc[3]                       = distRIV2alloc_LUT100_3[rballoc];
      }
      dlsch[0]->nb_rb                               = RIV2nb_rb_LUT100[rballoc];//NPRB;
      RIV_max = RIV_max100;
      break;
    }

    // harq_pid field is reserved
    if ((rnti==si_rnti) || (rnti==ra_rnti) || (rnti==p_rnti)){  //
      harq_pid=0;
      // see 36-212 V8.6.0 p. 45
      NPRB      = (TPC&1)+2;
      ndi       = 1;
      // 36-213 sec.7.1.7.2 p.26
      I_mcs     = mcs;
    }
    else {
      if (harq_pid>1) {
	LOG_E(PHY,"ERROR: Format 1A: harq_pid > 1\n");
	return(-1);
      }
      if (rballoc>RIV_max) {
	LOG_E(PHY,"ERROR: Format 1A: rb_alloc (%x) > RIV_max (%x)\n",rballoc,RIV_max);
	return(-1);
      }
      NPRB      = dlsch[0]->nb_rb;
      I_mcs     = get_I_TBS(mcs);
    }

    if (NPRB==0)
      return(-1);

    //  printf("NPRB %d, nb_rb %d, ndi %d\n",NPRB,dlsch[0]->nb_rb,ndi);
    dlsch[0]->harq_processes[harq_pid]->rvidx     = rv; 

    dlsch[0]->harq_processes[harq_pid]->Nl          = 1;
    dlsch[0]->layer_index = 0;
    dlsch[0]->harq_processes[harq_pid]->mimo_mode   = (frame_parms->mode1_flag == 1) ? SISO : ALAMOUTI;
    dlsch[0]->harq_processes[harq_pid]->Ndi         = ndi;
    dlsch[0]->dl_power_off = 1;

    if (dlsch[0]->harq_processes[harq_pid]->Ndi == 1) {
      dlsch[0]->harq_processes[harq_pid]->status = ACTIVE;
      //            printf("Setting DLSCH process %d to ACTIVE\n",harq_pid);
    }



    dlsch[0]->harq_processes[harq_pid]->mcs         = mcs;
    dlsch[0]->harq_processes[harq_pid]->TBS         = TBStable[I_mcs][NPRB-1];

    dlsch[0]->current_harq_pid = harq_pid;
    dlsch[0]->harq_ids[subframe] = harq_pid;

    dlsch[0]->active = 1;
    dlsch0 = dlsch[0];

    dlsch[0]->rnti = rnti;

    dlsch[0]->harq_ids[subframe] = harq_pid;
    if (dlsch[0]->harq_processes[harq_pid]->Ndi == 1)
      dlsch[0]->harq_processes[harq_pid]->status = ACTIVE;

    break;
  case format1:

    switch (frame_parms->N_RB_DL) {

    case 6:
      if (frame_type == TDD) {
	mcs       = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->mcs;
	rballoc   = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rballoc;
	rah       = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rah;
	rv        = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rv;
	ndi       = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->ndi;
	harq_pid  = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->harq_pid;
      }
      else {
	mcs      = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->mcs;
	rah      = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rah;
	rballoc  = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rv;
	ndi      = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->ndi;
	harq_pid = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
      }
      break;
    case 25:
      
      if (frame_type == TDD) {
	mcs       = ((DCI1_5MHz_TDD_t *)dci_pdu)->mcs;
	rballoc   = ((DCI1_5MHz_TDD_t *)dci_pdu)->rballoc;
	rah       = ((DCI1_5MHz_TDD_t *)dci_pdu)->rah;
	rv        = ((DCI1_5MHz_TDD_t *)dci_pdu)->rv;
	ndi       = ((DCI1_5MHz_TDD_t *)dci_pdu)->ndi;
	harq_pid  = ((DCI1_5MHz_TDD_t *)dci_pdu)->harq_pid;
      }
      else {
	mcs      = ((DCI1_5MHz_FDD_t *)dci_pdu)->mcs;
	rah      = ((DCI1_5MHz_FDD_t *)dci_pdu)->rah;
	rballoc  = ((DCI1_5MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1_5MHz_FDD_t *)dci_pdu)->rv;
	ndi      = ((DCI1_5MHz_FDD_t *)dci_pdu)->ndi;
	harq_pid = ((DCI1_5MHz_FDD_t *)dci_pdu)->harq_pid;
      }
      break;
    case 50:
      if (frame_type == TDD) {
	mcs       = ((DCI1_10MHz_TDD_t *)dci_pdu)->mcs;
	rballoc   = ((DCI1_10MHz_TDD_t *)dci_pdu)->rballoc;
	rah       = ((DCI1_10MHz_TDD_t *)dci_pdu)->rah;
	rv        = ((DCI1_10MHz_TDD_t *)dci_pdu)->rv;
	ndi       = ((DCI1_10MHz_TDD_t *)dci_pdu)->ndi;
	harq_pid  = ((DCI1_10MHz_TDD_t *)dci_pdu)->harq_pid;
      }
      else {
	mcs      = ((DCI1_10MHz_FDD_t *)dci_pdu)->mcs;
	rah      = ((DCI1_10MHz_FDD_t *)dci_pdu)->rah;
	rballoc  = ((DCI1_10MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1_10MHz_FDD_t *)dci_pdu)->rv;
	ndi      = ((DCI1_10MHz_FDD_t *)dci_pdu)->ndi;
	harq_pid = ((DCI1_10MHz_FDD_t *)dci_pdu)->harq_pid;
      }
      break;

    case 100:
      if (frame_type == TDD) {
	mcs       = ((DCI1_20MHz_TDD_t *)dci_pdu)->mcs;
	rballoc   = ((DCI1_20MHz_TDD_t *)dci_pdu)->rballoc;
	rah       = ((DCI1_20MHz_TDD_t *)dci_pdu)->rah;
	rv        = ((DCI1_20MHz_TDD_t *)dci_pdu)->rv;
	ndi       = ((DCI1_20MHz_TDD_t *)dci_pdu)->ndi;
	harq_pid  = ((DCI1_20MHz_TDD_t *)dci_pdu)->harq_pid;
      }
      else {
	mcs      = ((DCI1_20MHz_FDD_t *)dci_pdu)->mcs;
	rah      = ((DCI1_20MHz_FDD_t *)dci_pdu)->rah;
	rballoc  = ((DCI1_20MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1_20MHz_FDD_t *)dci_pdu)->rv;
	ndi      = ((DCI1_20MHz_FDD_t *)dci_pdu)->ndi;
	harq_pid = ((DCI1_20MHz_FDD_t *)dci_pdu)->harq_pid;
      }
      break;

    }

    if (harq_pid>=8) {
      LOG_E(PHY,"ERROR: Format 1: harq_pid >= 8\n");
      return(-1);
    }

    // msg("DCI: Setting subframe_tx for subframe %d\n",subframe);
    dlsch[0]->subframe_tx[subframe] = 1;

    conv_rballoc(rah,
		 rballoc,frame_parms->N_RB_DL,
		 dlsch[0]->rb_alloc);

    dlsch[0]->nb_rb = conv_nprb(rah,
				rballoc,
				frame_parms->N_RB_DL);

    NPRB      = dlsch[0]->nb_rb;


    if (NPRB==0)
      return(-1);


    dlsch[0]->harq_processes[harq_pid]->rvidx       = rv;

    dlsch[0]->harq_processes[harq_pid]->Nl          = 1;
    dlsch[0]->layer_index = 0;
    dlsch[0]->harq_processes[harq_pid]->mimo_mode   = (frame_parms->mode1_flag == 1) ? SISO : ALAMOUTI;
    dlsch[0]->dl_power_off = 1;
    dlsch[0]->harq_processes[harq_pid]->Ndi         = ndi;

    dlsch[0]->active = 1;

    if (dlsch[0]->harq_processes[harq_pid]->Ndi == 1) {
      dlsch[0]->harq_processes[harq_pid]->status = ACTIVE;
      //            printf("Setting DLSCH process %d to ACTIVE\n",harq_pid);
      // MCS and TBS don't change across HARQ rounds
    dlsch[0]->harq_processes[harq_pid]->mcs         = mcs;
    dlsch[0]->harq_processes[harq_pid]->TBS         = TBStable[get_I_TBS(dlsch[0]->harq_processes[harq_pid]->mcs)][NPRB-1];

    }


    dlsch[0]->current_harq_pid = harq_pid;
    dlsch[0]->harq_ids[subframe] = harq_pid;



    dlsch0 = dlsch[0];

    dlsch[0]->rnti = rnti;


    break;
  case format2_2A_L10PRB:

    return(-1);
    break;
  case format2_2A_M10PRB:

    harq_pid  = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->harq_pid;
    if (harq_pid>=8) {
      LOG_E(PHY,"ERROR: Format 2_2A_M10PRB: harq_pid >= 8\n");
      return(-1);
    }


    tbswap = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->tb_swap;
    if (tbswap == 0) {
      dlsch0 = dlsch[0];
      dlsch1 = dlsch[1];
    }
    else{
      dlsch0 = dlsch[1];
      dlsch1 = dlsch[0];
    }

    dlsch0->subframe_tx[subframe] = 1;

    dlsch0->current_harq_pid = harq_pid;
    dlsch1->current_harq_pid = harq_pid;
    dlsch0->harq_ids[subframe] = harq_pid;
    dlsch1->harq_ids[subframe] = harq_pid;
    //    printf("Setting DLSCH harq id %d to subframe %d\n",harq_pid,subframe);


    conv_rballoc(((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rah,
		 ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rballoc,frame_parms->N_RB_DL,
		 dlsch0->rb_alloc);
    dlsch1->rb_alloc[0]                         = dlsch0->rb_alloc[0];

    dlsch0->nb_rb                               = conv_nprb(((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rah,
							    ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rballoc,
							    frame_parms->N_RB_DL);
    dlsch1->nb_rb                               = dlsch0->nb_rb;

    dlsch0->harq_processes[harq_pid]->mcs       = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs1;
    dlsch1->harq_processes[harq_pid]->mcs       = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs2;
    dlsch0->harq_processes[harq_pid]->rvidx     = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rv1;
    dlsch1->harq_processes[harq_pid]->rvidx     = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rv2;

    // check if either TB is disabled (see 36-213 V8.6 p. 26)


    if ((dlsch0->harq_processes[harq_pid]->rvidx == 1) && (dlsch0->harq_processes[harq_pid]->mcs == 0))
      dlsch0->harq_processes[harq_pid]->status = DISABLED;

    if ((dlsch1->harq_processes[harq_pid]->rvidx == 1) && (dlsch1->harq_processes[harq_pid]->mcs == 0))
      dlsch1->harq_processes[harq_pid]->status = DISABLED;

    dlsch0->harq_processes[harq_pid]->Nl        = 1;

    dlsch0->layer_index                         = tbswap;
    dlsch1->layer_index                         = 1-tbswap;

    // Fix this
    tpmi = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->tpmi;

    switch (tpmi) {
    case 0 :
      dlsch0->harq_processes[harq_pid]->mimo_mode   = ALAMOUTI;
      break;
    case 1:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = UNIFORM_PRECODING11;
      dlsch0->pmi_alloc                             = pmi_extend(frame_parms,0);
      break;
    case 2:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = UNIFORM_PRECODING1m1;
      dlsch0->pmi_alloc                             = pmi_extend(frame_parms,1);
      break;
    case 3:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = UNIFORM_PRECODING1j;
      dlsch0->pmi_alloc                             = pmi_extend(frame_parms,2);
      break;
    case 4:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = UNIFORM_PRECODING1mj;
      dlsch0->pmi_alloc                             = pmi_extend(frame_parms,3);
      break;
    case 5:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = PUSCH_PRECODING0;
      dlsch0->pmi_alloc                             = DL_pmi_single;
      break;
    case 6:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = PUSCH_PRECODING1;
      return(-1);
      break;
    }

    //    printf("Set pmi %x (tpmi %d)\n",dlsch0->pmi_alloc,tpmi);


    if (frame_parms->mode1_flag == 1)
      dlsch0->harq_processes[harq_pid]->mimo_mode   = SISO;

    dlsch0->harq_processes[harq_pid]->Ndi         = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi1;
    if (dlsch0->harq_processes[harq_pid]->Ndi == 1) {
      dlsch0->harq_processes[harq_pid]->status = ACTIVE;
      //      printf("Setting DLSCH process %d to ACTIVE\n",harq_pid);
    }

    dlsch0->harq_processes[harq_pid]->mcs         = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs1;
    if (dlsch0->nb_rb > 0) {
#ifdef TBS_FIX
      dlsch0->harq_processes[harq_pid]->TBS         = 3*TBStable[get_I_TBS(dlsch0->harq_processes[harq_pid]->mcs)][dlsch0->nb_rb-1]/4;
      dlsch0->harq_processes[harq_pid]->TBS = (dlsch0->harq_processes[harq_pid]->TBS>>3)<<3;
#else
      dlsch0->harq_processes[harq_pid]->TBS         = TBStable[get_I_TBS(dlsch0->harq_processes[harq_pid]->mcs)][dlsch0->nb_rb-1];
#endif 
    }
    else {
      dlsch0->harq_processes[harq_pid]->TBS = 0;
    }

    dlsch0->active = 1;

    dlsch0->rnti = rnti;
    dlsch1->rnti = rnti;

    dlsch0->dl_power_off = 1;
    dlsch1->dl_power_off = 1;

    break;
  case format1E_2A_M10PRB:

    harq_pid  = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->harq_pid;
    if (harq_pid>=8) {
      LOG_E(PHY,"ERROR: Format 1E_2A_M10PRB: harq_pid >= 8\n");
      return(-1);
    }

    /*
      tbswap = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->tb_swap;
      if (tbswap == 0) {
      dlsch0 = dlsch[0];
      dlsch1 = dlsch[1];
      }
      else{
      dlsch0 = dlsch[1];
      dlsch1 = dlsch[0];
      }
    */
    dlsch0 = dlsch[0];
    dlsch0->subframe_tx[subframe] = 1;

    dlsch0->current_harq_pid = harq_pid;
    //dlsch1->current_harq_pid = harq_pid;
    dlsch0->harq_ids[subframe] = harq_pid;
    //dlsch1->harq_ids[subframe] = harq_pid;
    //    printf("Setting DLSCH harq id %d to subframe %d\n",harq_pid,subframe);

    conv_rballoc(((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rah,
		 ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rballoc,frame_parms->N_RB_DL,
		 dlsch0->rb_alloc);
		 
    //dlsch1->rb_alloc[0]                         = dlsch0->rb_alloc[0];

    dlsch0->nb_rb                               = conv_nprb(((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rah,
							    ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rballoc,
							    frame_parms->N_RB_DL);
    //dlsch1->nb_rb                               = dlsch0->nb_rb;

    dlsch0->harq_processes[harq_pid]->mcs       = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs;
    //dlsch1->harq_processes[harq_pid]->mcs       = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs2;
    dlsch0->harq_processes[harq_pid]->rvidx     = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rv;
    //dlsch1->harq_processes[harq_pid]->rvidx     = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rv2;

    // check if either TB is disabled (see 36-213 V8.6 p. 26) --> only for format 2 and 2A

    //if ((dlsch0->harq_processes[harq_pid]->rvidx == 1) && (dlsch0->harq_processes[harq_pid]->mcs == 0))
    //  dlsch0->harq_processes[harq_pid]->status = DISABLED;

    //if ((dlsch1->harq_processes[harq_pid]->rvidx == 1) && (dlsch1->harq_processes[harq_pid]->mcs == 0))
    // dlsch1->harq_processes[harq_pid]->status = DISABLED;

    dlsch0->harq_processes[harq_pid]->Nl        = 1;

    //dlsch0->layer_index                         = tbswap;
    //dlsch1->layer_index                         = 1-tbswap;

    // Fix this
    tpmi = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->tpmi;

    switch (tpmi) {
    case 0 :
      dlsch0->harq_processes[harq_pid]->mimo_mode   = ALAMOUTI;
      break;
    case 1:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = UNIFORM_PRECODING11;
      dlsch0->pmi_alloc                             = pmi_extend(frame_parms,0);
      break;
    case 2:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = UNIFORM_PRECODING1m1;
      dlsch0->pmi_alloc                             = pmi_extend(frame_parms,1);
      break;
    case 3:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = UNIFORM_PRECODING1j;
      dlsch0->pmi_alloc                             = pmi_extend(frame_parms,2);
      break;
    case 4:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = UNIFORM_PRECODING1mj;
      dlsch0->pmi_alloc                             = pmi_extend(frame_parms,3);
      break;
    case 5:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = PUSCH_PRECODING0;
      dlsch0->pmi_alloc                             = DL_pmi_single;
      break;
    case 6:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = PUSCH_PRECODING1;
      return(-1);
      break;
    }

    //    printf("Set pmi %x (tpmi %d)\n",dlsch0->pmi_alloc,tpmi);


    if (frame_parms->mode1_flag == 1)
      dlsch0->harq_processes[harq_pid]->mimo_mode   = SISO;

    dlsch0->harq_processes[harq_pid]->Ndi         = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi;
    if (dlsch0->harq_processes[harq_pid]->Ndi == 1) {
      dlsch0->harq_processes[harq_pid]->status = ACTIVE;
      //      printf("Setting DLSCH process %d to ACTIVE\n",harq_pid);
    }

    dlsch0->harq_processes[harq_pid]->mcs         = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs;
    if (dlsch0->nb_rb > 0) {
#ifdef TBS_FIX
      dlsch0->harq_processes[harq_pid]->TBS         = 3*TBStable[get_I_TBS(dlsch0->harq_processes[harq_pid]->mcs)][dlsch0->nb_rb-1]/4;
      dlsch0->harq_processes[harq_pid]->TBS = (dlsch0->harq_processes[harq_pid]->TBS>>3)<<3;
#else
      dlsch0->harq_processes[harq_pid]->TBS         = TBStable[get_I_TBS(dlsch0->harq_processes[harq_pid]->mcs)][dlsch0->nb_rb-1];
#endif 
    }
    else {
      dlsch0->harq_processes[harq_pid]->TBS = 0;
    }

    dlsch0->active = 1;

    dlsch0->rnti = rnti;
    //dlsch1->rnti = rnti;

    //    dlsch0->dl_power_off = 1;
    dlsch0->dl_power_off = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->dl_power_off;
    //dlsch1->dl_power_off = 1;

    break;
  default:
    LOG_E(PHY,"Unknown DCI format\n");
    return(-1);
    break;
  }
#ifdef DEBUG_DCI
  if (dlsch0) {
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    msg("dlsch0 eNB: dlsch0   %p\n",dlsch0);
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    msg("dlsch0 eNB: rnti     %x\n",dlsch0->rnti);
    msg("dlsch0 eNB: NBRB     %d\n",dlsch0->nb_rb);
    msg("dlsch0 eNB: rballoc  %x\n",dlsch0->rb_alloc[0]);
    msg("dlsch0 eNB: harq_pid %d\n",harq_pid);
    msg("dlsch0 eNB: Ndi      %d\n",dlsch0->harq_processes[harq_pid]->Ndi);
    msg("dlsch0 eNB: rvidx    %d\n",dlsch0->harq_processes[harq_pid]->rvidx);
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    msg("dlsch0 eNB: TBS      %d (NPRB %d)\n",dlsch0->harq_processes[harq_pid]->TBS,NPRB);
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    msg("dlsch0 eNB: mcs      %d\n",dlsch0->harq_processes[harq_pid]->mcs);
    msg("dlsch0 eNB: tpmi %d\n",tpmi);
    msg("dlsch0 eNB: mimo_mode %d\n",dlsch0->harq_processes[harq_pid]->mimo_mode);
  }
#endif

  // compute DL power control parameters   
  computeRhoA_eNB(pdsch_config_dedicated, dlsch[0]);
  
  computeRhoB_eNB(pdsch_config_dedicated,&(frame_parms->pdsch_config_common),frame_parms->nb_antennas_tx_eNB,dlsch[0]);

  return(0);
}


int dump_dci(LTE_DL_FRAME_PARMS *frame_parms, DCI_ALLOC_t *dci) {

  switch (dci->format) {

  case format0:   // This is an UL SCH allocation so nothing here, inform MAC
    if ((frame_parms->frame_type == TDD) &&
	(frame_parms->tdd_config>0))
      switch(frame_parms->N_RB_DL) {
      case 6:
	LOG_D(PHY,"DCI format0 (TDD, 1.5MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, dai %d, cqi_req %d\n",
	    dci->rnti,
	    ((uint32_t*)&dci->dci_pdu[0])[0],
	    ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->hopping,
	    ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,
	    ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs,
	    ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi,
	    ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC,
	    ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cshift,
	    ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai,
	    ((DCI0_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cqi_req);
	break;
      case 25:
	LOG_D(PHY,"DCI format0 (TDD1-6, 5MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, dai %d, cqi_req %d\n",
	    dci->rnti,
	    ((uint32_t*)&dci->dci_pdu[0])[0],
	    ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->hopping,
	    ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,
	    ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs,
	    ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi,
	    ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC,
	    ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cshift,
	    ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai,
	    ((DCI0_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cqi_req);
	break;
      case 50:
	LOG_D(PHY,"DCI format0 (TDD1-6, 10MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, dai %d, cqi_req %d\n",
	    dci->rnti,
	    ((uint32_t*)&dci->dci_pdu[0])[0],
	    ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->hopping,
	    ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,
	    ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs,
	    ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi,
	    ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC,
	    ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cshift,
	    ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai,
	    ((DCI0_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cqi_req);
	break;
      case 100:
	LOG_D(PHY,"DCI format0 (TDD1-6, 20MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, dai %d, cqi_req %d\n",
	    dci->rnti,
	    ((uint32_t*)&dci->dci_pdu[0])[0],
	    ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->hopping,
	    ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,
	    ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs,
	    ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi,
	    ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC,
	    ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cshift,
	    ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai,
	    ((DCI0_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->cqi_req);
	break;
      default:
	break;
      }
    else if (frame_parms->frame_type == FDD)
      switch(frame_parms->N_RB_DL) {
      case 6:
	LOG_D(PHY,"DCI format0 (FDD, 1.5MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, cqi_req %d\n",
	    dci->rnti,
	    ((uint32_t*)&dci->dci_pdu[0])[0],
	    ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->hopping,
	    ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
	    ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
	    ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
	    ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->TPC,
	    ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->cshift,
	    ((DCI0_1_5MHz_FDD_t *)&dci->dci_pdu[0])->cqi_req);
	break;
      case 25:
	LOG_D(PHY,"DCI format0 (FDD, 5MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, cqi_req %d\n",
	    dci->rnti,
	    ((uint32_t*)&dci->dci_pdu[0])[0],
	    ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->hopping,
	    ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
	    ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
	    ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
	    ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->TPC,
	    ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->cshift,
	    ((DCI0_5MHz_FDD_t *)&dci->dci_pdu[0])->cqi_req);
	break;
      case 50:
	LOG_D(PHY,"DCI format0 (FDD, 10MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, cqi_req %d\n",
	    dci->rnti,
	    ((uint32_t*)&dci->dci_pdu[0])[0],
	    ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->hopping,
	    ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
	    ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
	    ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
	    ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->TPC,
	    ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->cshift,
	    ((DCI0_10MHz_FDD_t *)&dci->dci_pdu[0])->cqi_req);
	break;
      case 100:
	LOG_D(PHY,"DCI format0 (FDD, 20MHz), rnti %x (%x): hopping %d, rb_alloc %x, mcs %d, ndi %d, TPC %d, cshift %d, cqi_req %d\n",
	    dci->rnti,
	    ((uint32_t*)&dci->dci_pdu[0])[0],
	    ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->hopping,
	    ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
	    ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
	    ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
	    ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->TPC,
	    ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->cshift,
	    ((DCI0_20MHz_FDD_t *)&dci->dci_pdu[0])->cqi_req);
	break;
      default:
	break;
      }
    else
      LOG_E(PHY,"Don't know how to handle TDD format 0 yet\n");
    break;

  case format1:
    if ((frame_parms->frame_type == TDD) &&
	(frame_parms->tdd_config>0))

      switch(frame_parms->N_RB_DL) {
      case 6:
	LOG_D(PHY,"DCI format1 (TDD 1.5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d, dai %d\n",
	    dci->rnti,
	    ((uint32_t*)&dci->dci_pdu)[0],
	    ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->rah,
	    ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->rballoc,
	    ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->mcs,
	    ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->harq_pid,
	    ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->ndi,
	    ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->rv,
	    ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->TPC,
	    ((DCI1_1_5MHz_TDD_t *)&dci->dci_pdu[0])->dai);
	break;
      case 25:
	LOG_D(PHY,"DCI format1 (TDD 5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d, dai %d\n",
	    dci->rnti,
	    ((uint32_t*)&dci->dci_pdu)[0],
	    ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->rah,
	    ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->rballoc,
	    ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->mcs,
	    ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->harq_pid,
	    ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->ndi,
	    ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->rv,
	    ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->TPC,
	    ((DCI1_5MHz_TDD_t *)&dci->dci_pdu[0])->dai);
	break;
      case 50:
	LOG_D(PHY,"DCI format1 (TDD 10 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d, dai %d\n",
	    dci->rnti,
	    ((uint32_t*)&dci->dci_pdu)[0],
	    ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->rah,
	    ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->rballoc,
	    ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->mcs,
	    ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->harq_pid,
	    ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->ndi,
	    ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->rv,
	    ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->TPC,
	    ((DCI1_10MHz_TDD_t *)&dci->dci_pdu[0])->dai);
	break;
      case 100:
	LOG_D(PHY,"DCI format1 (TDD 20 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d, dai %d\n",
	    dci->rnti,
	    ((uint32_t*)&dci->dci_pdu)[0],
	    ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->rah,
	    ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->rballoc,
	    ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->mcs,
	    ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->harq_pid,
	    ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->ndi,
	    ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->rv,
	    ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->TPC,
	    ((DCI1_20MHz_TDD_t *)&dci->dci_pdu[0])->dai);
	break;
      default:
	break;
      }
    else if (frame_parms->frame_type == FDD) {
      switch(frame_parms->N_RB_DL) {
      case 6:
	LOG_D(PHY,"DCI format1 (FDD, 1.5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d\n",
	    dci->rnti,
	    ((uint32_t*)&dci->dci_pdu)[0],
	    ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rah,
	    ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
	    ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
	    ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid,
	    ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
	    ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rv,
	    ((DCI1_1_5MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
	break;
      case 25:
	LOG_D(PHY,"DCI format1 (FDD, 5 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d\n",
	    dci->rnti,
	    ((uint32_t*)&dci->dci_pdu)[0],
	    ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->rah,
	    ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
	    ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
	    ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid,
	    ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
	    ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->rv,
	    ((DCI1_5MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
	break;
      case 50:
	LOG_D(PHY,"DCI format1 (FDD, 10 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d\n",
	    dci->rnti,
	    ((uint32_t*)&dci->dci_pdu)[0],
	    ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->rah,
	    ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
	    ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
	    ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid,
	    ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
	    ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->rv,
	    ((DCI1_10MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
	break;
      case 100:
	LOG_D(PHY,"DCI format1 (FDD, 20 MHz), rnti %x (%x): rah %d, rb_alloc %x, mcs %d, harq_pid %d, ndi %d, RV %d, TPC %d\n",
	    dci->rnti,
	    ((uint32_t*)&dci->dci_pdu)[0],
	    ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->rah,
	    ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,
	    ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->mcs,
	    ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid,
	    ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->ndi,
	    ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->rv,
	    ((DCI1_20MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
	break;
      default:
	break;
      }
    }

    else 
      LOG_E(PHY,"Don't know how to handle TDD format 0 yet\n");
    break;
  case format1A:  // This is DLSCH allocation for control traffic
    if ((frame_parms->frame_type == TDD) &&
	(frame_parms->tdd_config>0)) {
      switch (frame_parms->N_RB_DL) {
      case 6:
	msg("DCI format1A (TDD1-6, 1_5MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
	msg("VRB_TYPE %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->vrb_type);
	msg("RB_ALLOC %x (NB_RB %d)\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT25[((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc]);
	msg("MCS %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs);
	msg("HARQ_PID %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->harq_pid);
	msg("NDI %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi);
	msg("RV %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rv);
	msg("TPC %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC);
	msg("DAI %d\n",((DCI1A_1_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai);
	break;
      case 25:
	msg("DCI format1A (TDD1-6, 5MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
	msg("VRB_TYPE %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->vrb_type);
	msg("RB_ALLOC %d (NB_RB %d)\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT25[((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc]);
	msg("MCS %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs);
	msg("HARQ_PID %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->harq_pid);
	msg("NDI %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi);
	msg("RV %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rv);
	msg("TPC %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC);
	msg("DAI %d\n",((DCI1A_5MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai);
	break;
      case 50:
	msg("DCI format1A (TDD1-6, 10MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
	msg("VRB_TYPE %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->vrb_type);
	msg("RB_ALLOC %x (NB_RB %d)\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT25[((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc]);
	msg("MCS %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs);
	msg("HARQ_PID %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->harq_pid);
	msg("NDI %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi);
	msg("RV %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rv);
	msg("TPC %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC);
	msg("DAI %d\n",((DCI1A_10MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai);
	break;
      case 100:
	msg("DCI format1A (TDD1-6, 20MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
	msg("VRB_TYPE %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->vrb_type);
	msg("RB_ALLOC %x (NB_RB %d)\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT25[((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rballoc]);
	msg("MCS %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->mcs);
	msg("HARQ_PID %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->harq_pid);
	msg("NDI %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->ndi);
	msg("RV %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->rv);
	msg("TPC %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->TPC);
	msg("DAI %d\n",((DCI1A_20MHz_TDD_1_6_t *)&dci->dci_pdu[0])->dai);
	break;
      default:
	break;
      }
	
    }
    else if (frame_parms->frame_type == FDD) {
      switch (frame_parms->N_RB_DL) {
      case 6:
	msg("DCI format1A(FDD, 1.5MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
	msg("VRB_TYPE %d\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->vrb_type);
	msg("RB_ALLOC %x (NB_RB %d)\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT25[((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc]);
	msg("MCS %d\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->mcs);
	msg("HARQ_PID %d\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid);
	msg("NDI %d\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->ndi);
	msg("RV %d\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->rv);
	msg("TPC %d\n",((DCI1A_1_5MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
	break;
      case 25:
	msg("DCI format1A(FDD, 5MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
	msg("VRB_TYPE %d\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->vrb_type);
	msg("RB_ALLOC %x (NB_RB %d)\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT25[((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->rballoc]);
	msg("MCS %d\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->mcs);
	msg("HARQ_PID %d\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid);
	msg("NDI %d\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->ndi);
	msg("RV %d\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->rv);
	msg("TPC %d\n",((DCI1A_5MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
	break;
      case 50:
	msg("DCI format1A(FDD, 10MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
	msg("VRB_TYPE %d\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->vrb_type);
	msg("RB_ALLOC %x (NB_RB %d)\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT25[((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->rballoc]);
	msg("MCS %d\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->mcs);
	msg("HARQ_PID %d\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid);
	msg("NDI %d\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->ndi);
	msg("RV %d\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->rv);
	msg("TPC %d\n",((DCI1A_10MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
	break;
      case 100:
	msg("DCI format1A(FDD, 20MHz), rnti %x (%x)\n",dci->rnti,((uint32_t*)&dci->dci_pdu[0])[0]);
	msg("VRB_TYPE %d\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->vrb_type);
	msg("RB_ALLOC %x (NB_RB %d)\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->rballoc,RIV2nb_rb_LUT25[((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->rballoc]);
	msg("MCS %d\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->mcs);
	msg("HARQ_PID %d\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->harq_pid);
	msg("NDI %d\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->ndi);
	msg("RV %d\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->rv);
	msg("TPC %d\n",((DCI1A_20MHz_FDD_t *)&dci->dci_pdu[0])->TPC);
	break;
      default:
	break;
      }
    }
    break;
  case format2_2A_L10PRB:
    break;
  case format2_2A_M10PRB:

    msg("DCI format2_2A_M10PRB, rnti %x (%8x %8x): harq_pid %d, tb_swap %d, rah %d, rb_alloc %x, mcs1 %d, mcs2 %d, rv1 %d, rv2 %d, tpmi %d, ndi1 %d, ndi2 %d\n",
	dci->rnti,
	((uint32_t *)&dci->dci_pdu)[1],
	((uint32_t *)&dci->dci_pdu)[0],
	((DCI2_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->harq_pid,
	((DCI2_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->tb_swap,
	((DCI2_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->rah,
	((DCI2_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->rballoc,
	((DCI2_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->mcs1,
	((DCI2_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->mcs2,
	((DCI2_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->rv1,
	((DCI2_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->rv2,
	((DCI2_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->tpmi,
	((DCI2_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->ndi1,
	((DCI2_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->ndi2
	);

    break;
  case format1E_2A_M10PRB:

    msg("DCI format1E_2A_M10PRB, rnti %x (%8x): harq_pid %d, rah %d, rb_alloc %x, mcs %d, rv %d, tpmi %d, ndi %d, dl_power_offset %d\n",
	dci->rnti,
	((uint32_t *)&dci->dci_pdu)[0],
	((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->harq_pid,
	//((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->tb_swap,
	((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->rah,
	((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->rballoc,
	((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->mcs,
	((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->rv,
	((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->tpmi,
	((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->ndi,
	((DCI1E_5MHz_2A_M10PRB_TDD_t *)&dci->dci_pdu[0])->dl_power_off
	);

    break;
  default:
    LOG_E(PHY,"dci_tools.c: dump_dci, unknown format %d\n",dci->format);
    return(-1);
    break;
  }
  return(0);
}


int generate_ue_dlsch_params_from_dci(uint8_t subframe,
                                      void *dci_pdu,
                                      uint16_t rnti,
                                      DCI_format_t dci_format,
                                      LTE_UE_DLSCH_t **dlsch,
                                      LTE_DL_FRAME_PARMS *frame_parms,
                                      PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated,
                                      uint16_t si_rnti,
                                      uint16_t ra_rnti,
                                      uint16_t p_rnti) {

    uint8_t harq_pid=0;
    uint32_t rballoc=0,RIV_max;
    uint8_t frame_type=frame_parms->frame_type;
    uint8_t vrb_type=0;
    uint8_t mcs=0;
    uint8_t rv=0;
    uint8_t ndi=0;
    uint8_t rah=0;
    uint8_t TPC=0;
    uint8_t NPRB=0,tbswap=0,tpmi=0;
    LTE_UE_DLSCH_t *dlsch0=NULL,*dlsch1=NULL;

#ifdef DEBUG_DCI
    msg("dci_tools.c: Filling ue dlsch params -> rnti %x, dci_format %d\n",rnti,dci_format);
#endif

    switch (dci_format) {

    case format0:   // This is an UL SACH allocation so nothing here, inform MAC
      LOG_E(PHY,"format0 not possible\n");
        return(-1);
        break;
    case format1A:

        switch (frame_parms->N_RB_DL) {
        case 6:
            if (frame_type == TDD) {
                vrb_type = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
                mcs      = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
                rballoc  = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
                rv       = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rv;
                ndi      = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->ndi;
                TPC      = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->TPC; 
                harq_pid = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
                //	printf("TDD 1A: mcs %d, rballoc %x,rv %d, TPC %d\n",mcs,rballoc,rv,TPC);
            }
            else {
                vrb_type = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->vrb_type;
                mcs      = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->mcs;
                rballoc  = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rballoc;
                rv       = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rv;
                ndi      = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->ndi;
                TPC      = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->TPC; 
                harq_pid  = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
                //printf("FDD 1A: mcs %d, rballoc %x,rv %d, TPC %d\n",mcs,rballoc,rv,TPC);
            }

            if ((rnti==si_rnti) || (rnti==p_rnti) || (rnti==ra_rnti)){  //
                harq_pid = 0;
                // see 36-212 V8.6.0 p. 45
                NPRB = (TPC&1) + 2;
                ndi  = 1;
            }
            else {
                
                if (harq_pid>1) {
		  LOG_E(PHY,"Format 1A: harq_pid > 1\n");
                    return(-1);
                }
                
                NPRB = RIV2nb_rb_LUT6[rballoc];            
                dlsch[0]->harq_processes[harq_pid]->delta_PUCCH = delta_PUCCH_lut[TPC&3];      
            }
            
            if (vrb_type == 0)
                dlsch[0]->harq_processes[harq_pid]->rb_alloc[0] = localRIV2alloc_LUT6[rballoc];
            else
                dlsch[0]->harq_processes[harq_pid]->rb_alloc[0] = distRIV2alloc_LUT6[rballoc];
            
            dlsch[0]->harq_processes[harq_pid]->nb_rb = RIV2nb_rb_LUT6[rballoc];//NPRB;
            RIV_max = RIV_max6;
            
            break;
        case 25:
            
            if (frame_type == TDD) {
                vrb_type = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
                mcs      = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
                rballoc  = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
                rv       = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rv;
                ndi      = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->ndi;
                TPC      = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->TPC; 
                harq_pid = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
                //printf("TDD 1A: mcs %d, rballoc %x,rv %d, TPC %d\n",mcs,rballoc,rv,TPC);
            }
            else {
                vrb_type = ((DCI1A_5MHz_FDD_t *)dci_pdu)->vrb_type;
                mcs      = ((DCI1A_5MHz_FDD_t *)dci_pdu)->mcs;
                rballoc  = ((DCI1A_5MHz_FDD_t *)dci_pdu)->rballoc;
                rv       = ((DCI1A_5MHz_FDD_t *)dci_pdu)->rv;
                ndi      = ((DCI1A_5MHz_FDD_t *)dci_pdu)->ndi;
                TPC      = ((DCI1A_5MHz_FDD_t *)dci_pdu)->TPC; 
                harq_pid  = ((DCI1A_5MHz_FDD_t *)dci_pdu)->harq_pid;
                //printf("FDD 1A: mcs %d, rballoc %x,rv %d, TPC %d\n",mcs,rballoc,rv,TPC);
            }

            if ((rnti==si_rnti) || (rnti==p_rnti) || (rnti==ra_rnti)){  //
                harq_pid = 0;
                // see 36-212 V8.6.0 p. 45
                NPRB = (TPC&1) + 2;
                ndi  = 1; // bit is reserved
            }
            else {
                
                if (harq_pid>1) {
		  LOG_E(PHY,"Format 1A: harq_pid > 1\n");
                    return(-1);
                }
                
                NPRB = RIV2nb_rb_LUT25[rballoc];            
                dlsch[0]->harq_processes[harq_pid]->delta_PUCCH = delta_PUCCH_lut[TPC&3];      
            }

            if (vrb_type == 0)
                dlsch[0]->harq_processes[harq_pid]->rb_alloc[0] = localRIV2alloc_LUT25[rballoc];
            else
                dlsch[0]->harq_processes[harq_pid]->rb_alloc[0] = distRIV2alloc_LUT25[rballoc];
            
            dlsch[0]->harq_processes[harq_pid]->nb_rb = RIV2nb_rb_LUT25[rballoc];//NPRB;
            RIV_max = RIV_max25;    
            
            break;
        case 50:
            if (frame_type == TDD) {
                vrb_type = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
                mcs      = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->mcs;
                rballoc  = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rballoc;
                rv       = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rv;
                ndi      = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->ndi;
                TPC      = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->TPC; 
                harq_pid = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
                //	printf("TDD 1A: mcs %d, rballoc %x,rv %d, TPC %d\n",mcs,rballoc,rv,TPC);
            }
            else {
                vrb_type = ((DCI1A_10MHz_FDD_t *)dci_pdu)->vrb_type;
                mcs      = ((DCI1A_10MHz_FDD_t *)dci_pdu)->mcs;
                rballoc  = ((DCI1A_10MHz_FDD_t *)dci_pdu)->rballoc;
                rv       = ((DCI1A_10MHz_FDD_t *)dci_pdu)->rv;
                ndi      = ((DCI1A_10MHz_FDD_t *)dci_pdu)->ndi;
                TPC      = ((DCI1A_10MHz_FDD_t *)dci_pdu)->TPC; 
                harq_pid  = ((DCI1A_10MHz_FDD_t *)dci_pdu)->harq_pid;
                //printf("FDD 1A: mcs %d, rballoc %x,rv %d, TPC %d\n",mcs,rballoc,rv,TPC);
            }
            
            if ((rnti==si_rnti) || (rnti==p_rnti) || (rnti==ra_rnti)){  //
                harq_pid = 0;
                // see 36-212 V8.6.0 p. 45
                NPRB = (TPC&1) + 2;
                ndi  = 1;
            }
            else {
                
                if (harq_pid>1) {
		  LOG_E(PHY,"Format 1A: harq_pid > 1\n");
                    return(-1);
                }
                
                NPRB = RIV2nb_rb_LUT50[rballoc];            
                dlsch[0]->harq_processes[harq_pid]->delta_PUCCH = delta_PUCCH_lut[TPC&3];      
            }

            if (vrb_type == 0) {
                dlsch[0]->harq_processes[harq_pid]->rb_alloc[0] = localRIV2alloc_LUT50_0[rballoc];
                dlsch[0]->harq_processes[harq_pid]->rb_alloc[1] = localRIV2alloc_LUT50_1[rballoc];
            }
            else {
                dlsch[0]->harq_processes[harq_pid]->rb_alloc[0] = distRIV2alloc_LUT50_0[rballoc];
                dlsch[0]->harq_processes[harq_pid]->rb_alloc[1] = distRIV2alloc_LUT50_1[rballoc];
            }
            dlsch[0]->harq_processes[harq_pid]->nb_rb  = RIV2nb_rb_LUT50[rballoc];//NPRB;
            RIV_max = RIV_max50;
            break;
        case 100:
            if (frame_type == TDD) {
                vrb_type = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
                mcs      = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->mcs;
                rballoc  = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->rballoc;
                rv       = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->rv;
                ndi      = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->ndi;
                TPC      = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->TPC; 
                harq_pid = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
                //	printf("TDD 1A: mcs %d, rballoc %x,rv %d, TPC %d\n",mcs,rballoc,rv,TPC);
            }
            else {
                vrb_type = ((DCI1A_20MHz_FDD_t *)dci_pdu)->vrb_type;
                mcs      = ((DCI1A_20MHz_FDD_t *)dci_pdu)->mcs;
                rballoc  = ((DCI1A_20MHz_FDD_t *)dci_pdu)->rballoc;
                rv       = ((DCI1A_20MHz_FDD_t *)dci_pdu)->rv;
                ndi      = ((DCI1A_20MHz_FDD_t *)dci_pdu)->ndi;
                TPC      = ((DCI1A_20MHz_FDD_t *)dci_pdu)->TPC; 
                harq_pid = ((DCI1A_20MHz_FDD_t *)dci_pdu)->harq_pid;
                //printf("FDD 1A: mcs %d, rballoc %x,rv %d, TPC %d\n",mcs,rballoc,rv,TPC);
            }

            if ((rnti==si_rnti) || (rnti==p_rnti) || (rnti==ra_rnti)){  //
                harq_pid = 0;
                // see 36-212 V8.6.0 p. 45
                NPRB = (TPC&1) + 2;
                ndi  = 1;
            }
            else {
                
                if (harq_pid>1) {
		  LOG_E(PHY,"Format 1A: harq_pid > 1\n");
                    return(-1);
                }
                
                NPRB = RIV2nb_rb_LUT100[rballoc];            
                dlsch[0]->harq_processes[harq_pid]->delta_PUCCH = delta_PUCCH_lut[TPC&3];      
            }

            if (vrb_type == 0) {
                dlsch[0]->harq_processes[harq_pid]->rb_alloc[0] = localRIV2alloc_LUT100_0[rballoc];
                dlsch[0]->harq_processes[harq_pid]->rb_alloc[1] = localRIV2alloc_LUT100_1[rballoc];
                dlsch[0]->harq_processes[harq_pid]->rb_alloc[2] = localRIV2alloc_LUT100_2[rballoc];
                dlsch[0]->harq_processes[harq_pid]->rb_alloc[3] = localRIV2alloc_LUT100_3[rballoc];
            }
            else {
                dlsch[0]->harq_processes[harq_pid]->rb_alloc[0] = distRIV2alloc_LUT100_0[rballoc];
                dlsch[0]->harq_processes[harq_pid]->rb_alloc[1] = distRIV2alloc_LUT100_1[rballoc];
                dlsch[0]->harq_processes[harq_pid]->rb_alloc[2] = distRIV2alloc_LUT100_2[rballoc];
                dlsch[0]->harq_processes[harq_pid]->rb_alloc[3] = distRIV2alloc_LUT100_3[rballoc];
            }
            dlsch[0]->harq_processes[harq_pid]->nb_rb = RIV2nb_rb_LUT100[rballoc];//NPRB;
            RIV_max = RIV_max100;
            break;
        }
        
        if (rballoc>RIV_max) {
	  LOG_E(PHY,"Format 1A: rb_alloc > RIV_max\n");
            return(-1);
        }
            
        if (NPRB==0) {
	  LOG_E(PHY,"Format 1A: NPRB=0\n");
            return(-1);
        }
1815 1816
        // change the mcs limit from 7 to 8, supported by MAC
        if (mcs > 8) {
1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060
	  LOG_E(PHY,"Format 1A: unlikely mcs for format 1A (%d)\n",mcs);
            return(-1);
        } 

        dlsch[0]->current_harq_pid = harq_pid;
        //    msg("Format 1A: harq_pid %d\n",harq_pid);        
        dlsch[0]->harq_processes[harq_pid]->rvidx = rv;        
        dlsch[0]->harq_processes[harq_pid]->Nl = 1;
        dlsch[0]->layer_index = 0;
        dlsch[0]->harq_processes[harq_pid]->mimo_mode = frame_parms->mode1_flag == 1 ?SISO : ALAMOUTI;
        dlsch[0]->harq_processes[harq_pid]->dl_power_off = 1; //no power offset
        dlsch[0]->harq_processes[harq_pid]->Ndi = ndi;
        dlsch[0]->harq_processes[harq_pid]->mcs = mcs;        
        dlsch[0]->harq_processes[harq_pid]->TBS = TBStable[get_I_TBS(mcs)][NPRB-1];        
        dlsch[0]->rnti = rnti;        
        dlsch0 = dlsch[0];
        break;

  case format1:

    switch (frame_parms->N_RB_DL) {
    case 6:
      if (frame_type == TDD) {
	mcs       = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->mcs;
	rballoc   = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rballoc;
	rah       = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rah;
	rv        = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rv;
	ndi       = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->ndi;
	harq_pid  = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->harq_pid;
      }
      else {
	mcs      = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->mcs;
	rah      = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rah;
	rballoc  = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rv;
	ndi      = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->ndi;
	harq_pid = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
      }
      break;
    case 25:
      if (frame_type == TDD) {
	mcs       = ((DCI1_5MHz_TDD_t *)dci_pdu)->mcs;
	rballoc   = ((DCI1_5MHz_TDD_t *)dci_pdu)->rballoc;
	rah       = ((DCI1_5MHz_TDD_t *)dci_pdu)->rah;
	rv        = ((DCI1_5MHz_TDD_t *)dci_pdu)->rv;
	ndi       = ((DCI1_5MHz_TDD_t *)dci_pdu)->ndi;
	harq_pid  = ((DCI1_5MHz_TDD_t *)dci_pdu)->harq_pid;
      }
      else {
	mcs      = ((DCI1_5MHz_FDD_t *)dci_pdu)->mcs;
	rah      = ((DCI1_5MHz_FDD_t *)dci_pdu)->rah;
	rballoc  = ((DCI1_5MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1_5MHz_FDD_t *)dci_pdu)->rv;
	ndi      = ((DCI1_5MHz_FDD_t *)dci_pdu)->ndi;
	harq_pid = ((DCI1_5MHz_FDD_t *)dci_pdu)->harq_pid;
      }
      break;
    case 50:
      if (frame_type == TDD) {
	mcs       = ((DCI1_10MHz_TDD_t *)dci_pdu)->mcs;
	rballoc   = ((DCI1_10MHz_TDD_t *)dci_pdu)->rballoc;
	rah       = ((DCI1_10MHz_TDD_t *)dci_pdu)->rah;
	rv        = ((DCI1_10MHz_TDD_t *)dci_pdu)->rv;
	ndi       = ((DCI1_10MHz_TDD_t *)dci_pdu)->ndi;
	harq_pid  = ((DCI1_10MHz_TDD_t *)dci_pdu)->harq_pid;
      }
      else {
	mcs      = ((DCI1_10MHz_FDD_t *)dci_pdu)->mcs;
	rah      = ((DCI1_10MHz_FDD_t *)dci_pdu)->rah;
	rballoc  = ((DCI1_10MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1_10MHz_FDD_t *)dci_pdu)->rv;
	ndi      = ((DCI1_10MHz_FDD_t *)dci_pdu)->ndi;
	harq_pid = ((DCI1_10MHz_FDD_t *)dci_pdu)->harq_pid;
      }
      break;
    case 100:
      if (frame_type == TDD) {
	mcs       = ((DCI1_20MHz_TDD_t *)dci_pdu)->mcs;
	rballoc   = ((DCI1_20MHz_TDD_t *)dci_pdu)->rballoc;
	rah       = ((DCI1_20MHz_TDD_t *)dci_pdu)->rah;
	rv        = ((DCI1_20MHz_TDD_t *)dci_pdu)->rv;
	ndi       = ((DCI1_20MHz_TDD_t *)dci_pdu)->ndi;
	harq_pid  = ((DCI1_20MHz_TDD_t *)dci_pdu)->harq_pid;
      }
      else {
	mcs      = ((DCI1_20MHz_FDD_t *)dci_pdu)->mcs;
	rah      = ((DCI1_20MHz_FDD_t *)dci_pdu)->rah;
	rballoc  = ((DCI1_20MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1_20MHz_FDD_t *)dci_pdu)->rv;
	ndi      = ((DCI1_20MHz_FDD_t *)dci_pdu)->ndi;
	harq_pid = ((DCI1_20MHz_FDD_t *)dci_pdu)->harq_pid;
      }
      break;
    }
    if (harq_pid>=8) {
      LOG_E(PHY,"Format 1: harq_pid >= 8\n");
      return(-1);
    }
    dlsch[0]->current_harq_pid = harq_pid;
    dlsch[0]->harq_ack[subframe].harq_id = harq_pid;

    conv_rballoc(rah,rballoc,frame_parms->N_RB_DL,dlsch[0]->harq_processes[harq_pid]->rb_alloc);

    dlsch[0]->harq_processes[harq_pid]->nb_rb = conv_nprb(rah,
                                rballoc,
                                frame_parms->N_RB_DL);

    NPRB = dlsch[0]->harq_processes[harq_pid]->nb_rb;

    //    printf("test PDSCH NPRB %d, rah %d, rballoc %x, rballoc2 %x\n",NPRB,rah,rballoc,dlsch[0]->harq_processes[harq_pid]->rb_alloc[0]);

    if (NPRB==0) {
      LOG_E(PHY,"Format 1: NPRB=0 (rballoc %x,mcs %d, frame_type %d N_RB_DL %d)\n",rballoc,mcs,frame_parms->frame_type,frame_parms->N_RB_DL);
      return(-1);
    }

    //    printf("NPRB %d\n",NPRB);
    dlsch[0]->harq_processes[harq_pid]->delta_PUCCH     = delta_PUCCH_lut[TPC&3];      

    dlsch[0]->harq_processes[harq_pid]->rvidx     = rv;

    dlsch[0]->harq_processes[harq_pid]->Nl          = 1;
    dlsch[0]->layer_index = 0;
    dlsch[0]->harq_processes[harq_pid]->mimo_mode   = (frame_parms->mode1_flag == 1) ? SISO : ALAMOUTI;
    dlsch[0]->harq_processes[harq_pid]->dl_power_off = 1; //no power offset
    dlsch[0]->harq_processes[harq_pid]->Ndi         = ndi;

    if (dlsch[0]->harq_processes[harq_pid]->Ndi == 1) {
      dlsch[0]->harq_processes[harq_pid]->status = ACTIVE;
      //      printf("Setting DLSCH process %d to ACTIVE\n",harq_pid);
    }
    else if (dlsch[0]->harq_processes[harq_pid]->status == SCH_IDLE) {  // we got an Ndi = 0 for a previously decoded process,
      // this happens if either another harq process in the same
      // is NAK or an ACK was not received

      dlsch[0]->harq_ack[subframe].ack              = 1;
      dlsch[0]->harq_ack[subframe].harq_id          = harq_pid;
      dlsch[0]->harq_ack[subframe].send_harq_status = 1;
      dlsch[0]->active = 0;
      //     printf("Got NDI=0 for correctly decoded SDU (harq_pid %d) subframe %d\n",harq_pid,subframe);
      return(0);
    }
    dlsch[0]->harq_processes[harq_pid]->mcs         = mcs;

    dlsch[0]->harq_processes[harq_pid]->TBS         = TBStable[get_I_TBS(mcs)][NPRB-1];
    //    msg("test: MCS %d, NPRB %d, TBS %d\n",mcs,NPRB,dlsch[0]->harq_processes[harq_pid]->TBS);
    dlsch[0]->current_harq_pid = harq_pid;

    dlsch[0]->active = 1;

    dlsch[0]->rnti = rnti;

    dlsch0 = dlsch[0];

    break;

  case format2_2A_L10PRB:
    LOG_E(PHY,"format2_2A_L10PRB not yet implemented\n");
    return(-1);
    break;
  case format2_2A_M10PRB:

    harq_pid  = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->harq_pid;
    if (harq_pid>=8) {
      LOG_E(PHY,"Format 2_2A_M10PRB: harq_pid >= 8\n");
      return(-1);
    }
    dlsch[0]->current_harq_pid = harq_pid;
    dlsch[0]->harq_ack[subframe].harq_id = harq_pid;

    tbswap = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->tb_swap;
    if (tbswap == 0) {
      dlsch0 = dlsch[0];
      dlsch1 = dlsch[1];
    }
    else{
      dlsch0 = dlsch[1];
      dlsch1 = dlsch[0];
    }

    conv_rballoc(((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rah,
		 ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rballoc,frame_parms->N_RB_DL,
		 dlsch0->harq_processes[harq_pid]->rb_alloc);
    dlsch1->harq_processes[harq_pid]->rb_alloc[0]                         = dlsch0->harq_processes[harq_pid]->rb_alloc[0];

    dlsch0->harq_processes[harq_pid]->nb_rb                               = conv_nprb(((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rah,
							    ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rballoc,
							    frame_parms->N_RB_DL);
    dlsch1->harq_processes[harq_pid]->nb_rb                               = dlsch0->harq_processes[harq_pid]->nb_rb;

    dlsch0->harq_processes[harq_pid]->mcs       = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs1;

    dlsch0->harq_processes[harq_pid]->delta_PUCCH     = delta_PUCCH_lut[((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->TPC&3];      
    /*
      if (dlsch0->harq_processes[harq_pid]->mcs>20) {
      msg("dci_tools.c: mcs > 20 disabled for now (asked %d)\n",dlsch0->harq_processes[harq_pid]->mcs);
      return(-1);
      }
    */

    dlsch1->harq_processes[harq_pid]->mcs       = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs2;
    dlsch0->harq_processes[harq_pid]->rvidx     = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rv1;
    dlsch1->harq_processes[harq_pid]->rvidx     = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rv2;

    // check if either TB is disabled (see 36-213 V8.6 p. 26)

    if ((dlsch0->harq_processes[harq_pid]->rvidx == 1) && (dlsch0->harq_processes[harq_pid]->mcs == 0)) {
      dlsch0->harq_processes[harq_pid]->status = DISABLED;
    }
    if ((dlsch1->harq_processes[harq_pid]->rvidx == 1) && (dlsch1->harq_processes[harq_pid]->mcs == 0)) {
      dlsch1->harq_processes[harq_pid]->status = DISABLED;
    }
    dlsch0->harq_processes[harq_pid]->Nl        = 1;

    dlsch0->layer_index                         = tbswap;
    dlsch1->layer_index                         = 1-tbswap;

    // Fix this
    tpmi = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->tpmi;
    //    msg("ue: tpmi %d\n",tpmi);

    switch (tpmi) {
    case 0 :
      dlsch0->harq_processes[harq_pid]->mimo_mode   = ALAMOUTI;
      break;
    case 1:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = UNIFORM_PRECODING11;
      dlsch0->harq_processes[harq_pid]->pmi_alloc                             = pmi_extend(frame_parms,0);
      break;
    case 2:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = UNIFORM_PRECODING1m1;
      dlsch0->harq_processes[harq_pid]->pmi_alloc                             = pmi_extend(frame_parms,1);
      break;
    case 3:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = UNIFORM_PRECODING1j;
      dlsch0->harq_processes[harq_pid]->pmi_alloc                             = pmi_extend(frame_parms,2);
      break;
    case 4:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = UNIFORM_PRECODING1mj;
      dlsch0->harq_processes[harq_pid]->pmi_alloc                             = pmi_extend(frame_parms,3);
      break;
    case 5:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = PUSCH_PRECODING0;
      // pmi stored from ulsch allocation routine
2061 2062
      dlsch0->harq_processes[harq_pid]->pmi_alloc                             = dlsch0->pmi_alloc;
      //LOG_I(PHY,"XXX using PMI %x\n",pmi2hex_2Ar1(dlsch0->harq_processes[harq_pid]->pmi_alloc));
2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217
      break;
    case 6:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = PUSCH_PRECODING1;
      LOG_E(PHY,"Unsupported TPMI\n");
      return(-1);
      break;
    }


    if (frame_parms->mode1_flag == 1)
      dlsch0->harq_processes[harq_pid]->mimo_mode   = SISO;

    dlsch0->harq_processes[harq_pid]->Ndi         = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi1;
    if (dlsch0->harq_processes[harq_pid]->Ndi == 1)
      dlsch0->harq_processes[harq_pid]->status = ACTIVE;
    else if (dlsch0->harq_processes[harq_pid]->status == SCH_IDLE) {  // we got an Ndi = 0 for a previously decoded process,
      // this happens if either another harq process in the same
      // is NAK or an ACK was not received

      dlsch0->harq_ack[subframe].ack              = 1;
      dlsch0->harq_ack[subframe].harq_id          = harq_pid;
      dlsch0->harq_ack[subframe].send_harq_status = 1;
      dlsch0->active = 0;
      return(0);
    }
    dlsch0->harq_processes[harq_pid]->mcs         = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs1;
    if (dlsch0->harq_processes[harq_pid]->nb_rb>1) {
#ifdef TBS_FIX
      dlsch0->harq_processes[harq_pid]->TBS         = 3*TBStable[get_I_TBS(dlsch0->harq_processes[harq_pid]->mcs)][dlsch0->harq_processes[harq_pid]->nb_rb-1]/4;
      dlsch0->harq_processes[harq_pid]->TBS = (dlsch0->harq_processes[harq_pid]->TBS>>3)<<3;
#else
      dlsch0->harq_processes[harq_pid]->TBS         = TBStable[get_I_TBS(dlsch0->harq_processes[harq_pid]->mcs)][dlsch0->harq_processes[harq_pid]->nb_rb-1];
#endif
    }
    else
      dlsch0->harq_processes[harq_pid]->TBS         =0;
    /*
      if (dlsch0->harq_processes[harq_pid]->mcs > 18)
      printf("mcs %d, TBS %d\n",dlsch0->harq_processes[harq_pid]->mcs,dlsch0->harq_processes[harq_pid]->TBS);
    */
    dlsch1->harq_processes[harq_pid]->Ndi         = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi2;
    if (dlsch1->harq_processes[harq_pid]->Ndi == 1)
      dlsch1->harq_processes[harq_pid]->status = ACTIVE;
    dlsch1->harq_processes[harq_pid]->mcs         = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs2;
    if (dlsch1->harq_processes[harq_pid]->nb_rb>1) {
#ifdef TBS_FIX
      dlsch1->harq_processes[harq_pid]->TBS       = 3*TBStable[dlsch1->harq_processes[harq_pid]->mcs][dlsch1->harq_processes[harq_pid]->nb_rb-1]/4;
      dlsch1->harq_processes[harq_pid]->TBS         = (dlsch1->harq_processes[harq_pid]->TBS>>3)<<3;
#else
      dlsch1->harq_processes[harq_pid]->TBS       = TBStable[dlsch1->harq_processes[harq_pid]->mcs][dlsch1->harq_processes[harq_pid]->nb_rb-1];
#endif
    }
    else
      dlsch1->harq_processes[harq_pid]->TBS         = 0;

    dlsch0->rnti = rnti;
    dlsch1->rnti = rnti;

    dlsch0->harq_processes[harq_pid]->dl_power_off = 1; //no power offset
    dlsch1->harq_processes[harq_pid]->dl_power_off = 1; //no power offset

    dlsch0->active = 1;
    dlsch1->active = 1;

    break;
  case format1E_2A_M10PRB:

    harq_pid  = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->harq_pid;
    if (harq_pid>=8) {
      LOG_E(PHY,"Format 1E_2A_M10PRB: harq_pid >= 8\n");
      return(-1);
    }
    dlsch[0]->current_harq_pid = harq_pid;
    dlsch[0]->harq_ack[subframe].harq_id = harq_pid;

    /*
      tbswap = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->tb_swap;
      if (tbswap == 0) {
      dlsch0 = dlsch[0];
      dlsch1 = dlsch[1];
      }
      else{
      dlsch0 = dlsch[1];
      dlsch1 = dlsch[0];
      }
    */
    dlsch0 = dlsch[0];

    conv_rballoc(((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rah,
		 ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rballoc,frame_parms->N_RB_DL,
		 dlsch0->harq_processes[harq_pid]->rb_alloc);
    //dlsch1->harq_processes[harq_pid]->rb_alloc[0]                         = dlsch0->harq_processes[harq_pid]->rb_alloc[0];

    dlsch0->harq_processes[harq_pid]->nb_rb                               = conv_nprb(((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rah,
							    ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rballoc,
							    frame_parms->N_RB_DL);
    //dlsch1->harq_processes[harq_pid]->nb_rb                               = dlsch0->harq_processes[harq_pid]->nb_rb;

    dlsch0->harq_processes[harq_pid]->mcs             = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs;
    dlsch0->harq_processes[harq_pid]->delta_PUCCH     = delta_PUCCH_lut[((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->TPC&3];      



    /*
      if (dlsch0->harq_processes[harq_pid]->mcs>20) {
      msg("dci_tools.c: mcs > 20 disabled for now (asked %d)\n",dlsch0->harq_processes[harq_pid]->mcs);
      return(-1);
      }
    */

    //dlsch1->harq_processes[harq_pid]->mcs       = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs2;
    dlsch0->harq_processes[harq_pid]->rvidx     = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rv;
    //dlsch1->harq_processes[harq_pid]->rvidx     = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->rv2;

    // check if either TB is disabled (see 36-213 V8.6 p. 26)

    if ((dlsch0->harq_processes[harq_pid]->rvidx == 1) && (dlsch0->harq_processes[harq_pid]->mcs == 0)) {
      dlsch0->harq_processes[harq_pid]->status = DISABLED;
    }
    //if ((dlsch1->harq_processes[harq_pid]->rvidx == 1) && (dlsch1->harq_processes[harq_pid]->mcs == 0)) {
    //dlsch1->harq_processes[harq_pid]->status = DISABLED;
    //}
    dlsch0->harq_processes[harq_pid]->Nl        = 1;

    //dlsch0->layer_index                         = tbswap;
    //dlsch1->layer_index                         = 1-tbswap;

    
    // Fix this
    tpmi = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->tpmi;
    //    msg("ue: tpmi %d\n",tpmi);

    switch (tpmi) {
    case 0 :
      dlsch0->harq_processes[harq_pid]->mimo_mode   = ALAMOUTI;
      break;
    case 1:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = UNIFORM_PRECODING11;
      dlsch0->harq_processes[harq_pid]->pmi_alloc   = pmi_extend(frame_parms,0);
      break;
    case 2:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = UNIFORM_PRECODING1m1;
      dlsch0->harq_processes[harq_pid]->pmi_alloc   = pmi_extend(frame_parms,1);
      break;
    case 3:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = UNIFORM_PRECODING1j;
      dlsch0->harq_processes[harq_pid]->pmi_alloc   = pmi_extend(frame_parms,2);
      break;
    case 4:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = UNIFORM_PRECODING1mj;
      dlsch0->harq_processes[harq_pid]->pmi_alloc   = pmi_extend(frame_parms,3);
      break;
    case 5:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = PUSCH_PRECODING0;
      // pmi stored from ulsch allocation routine
2218 2219 2220
      dlsch0->harq_processes[harq_pid]->pmi_alloc                             = dlsch0->pmi_alloc;
      //LOG_I(PHY,"XXX using PMI %x\n",pmi2hex_2Ar1(dlsch0->harq_processes[harq_pid]->pmi_alloc));
     break;
2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571
    case 6:
      dlsch0->harq_processes[harq_pid]->mimo_mode   = PUSCH_PRECODING1;
      LOG_E(PHY,"Unsupported TPMI\n");
      return(-1);
      break;
    }

    
    if (frame_parms->mode1_flag == 1)
      dlsch0->harq_processes[harq_pid]->mimo_mode   = SISO;

    dlsch0->harq_processes[harq_pid]->Ndi         = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi;
    if (dlsch0->harq_processes[harq_pid]->Ndi == 1)
      dlsch0->harq_processes[harq_pid]->status = ACTIVE;
    else if (dlsch0->harq_processes[harq_pid]->status == SCH_IDLE) {  // we got an Ndi = 0 for a previously decoded process,
      // this happens if either another harq process in the same
      // is NAK or an ACK was not received

      dlsch0->harq_ack[subframe].ack              = 1;
      dlsch0->harq_ack[subframe].harq_id          = harq_pid;
      dlsch0->harq_ack[subframe].send_harq_status = 1;
      dlsch0->active = 0;
      return(0);
    }
    dlsch0->harq_processes[harq_pid]->mcs         = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs;
    if (dlsch0->harq_processes[harq_pid]->nb_rb>1) {
#ifdef TBS_FIX
      dlsch0->harq_processes[harq_pid]->TBS         = 3*TBStable[get_I_TBS(dlsch0->harq_processes[harq_pid]->mcs)][dlsch0->harq_processes[harq_pid]->nb_rb-1]/4;
      dlsch0->harq_processes[harq_pid]->TBS = (dlsch0->harq_processes[harq_pid]->TBS>>3)<<3;
#else
      dlsch0->harq_processes[harq_pid]->TBS         = TBStable[get_I_TBS(dlsch0->harq_processes[harq_pid]->mcs)][dlsch0->harq_processes[harq_pid]->nb_rb-1];
#endif
    }
    else
      dlsch0->harq_processes[harq_pid]->TBS         =0;
    /*
      if (dlsch0->harq_processes[harq_pid]->mcs > 18)
      printf("mcs %d, TBS %d\n",dlsch0->harq_processes[harq_pid]->mcs,dlsch0->harq_processes[harq_pid]->TBS);
    */

    /*    dlsch1->harq_processes[harq_pid]->Ndi         = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi2;
	  if (dlsch1->harq_processes[harq_pid]->Ndi == 1)
	  dlsch1->harq_processes[harq_pid]->status = ACTIVE;
	  dlsch1->harq_processes[harq_pid]->mcs         = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs2;
	  if (dlsch1->harq_processes[harq_pid]->nb_rb>1) {
	  #ifdef TBS_FIX
	  dlsch1->harq_processes[harq_pid]->TBS       = 3*TBStable[dlsch1->harq_processes[harq_pid]->mcs][dlsch1->harq_processes[harq_pid]->nb_rb-1]/4;
	  dlsch1->harq_processes[harq_pid]->TBS         = (dlsch1->harq_processes[harq_pid]->TBS>>3)<<3;
	  #else
	  dlsch1->harq_processes[harq_pid]->TBS       = TBStable[dlsch1->harq_processes[harq_pid]->mcs][dlsch1->harq_processes[harq_pid]->nb_rb-1];
	  #endif
	  }
	  else
	  dlsch1->harq_processes[harq_pid]->TBS         = 0;
    */
    dlsch0->rnti = rnti;
    //dlsch1->rnti = rnti;

    dlsch0->active = 1;
    //dlsch1->active = 1;

    dlsch0->harq_processes[harq_pid]->dl_power_off = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->dl_power_off;
    //dlsch1->harq_processes[harq_pid]->dl_power_off = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->dl_power_off;


    break;
  default:
    LOG_E(PHY,"format %d not yet implemented\n",dci_format);
    return(-1);
    break;
  }


#ifdef DEBUG_DCI
  if (dlsch[0]) {
    msg("PDSCH dlsch0 UE: rnti     %x\n",dlsch[0]->rnti);
    msg("PDSCH dlsch0 UE: NBRB     %d\n",dlsch[0]->harq_processes[harq_pid]->nb_rb);
    msg("PDSCH dlsch0 UE: rballoc  %x\n",dlsch[0]->harq_processes[harq_pid]->rb_alloc[0]);
    msg("PDSCH dlsch0 UE: harq_pid %d\n",harq_pid);
    msg("PDSCH dlsch0 UE: Ndi      %d\n",dlsch[0]->harq_processes[harq_pid]->Ndi);
    msg("PDSCH dlsch0 UE: rvidx    %d\n",dlsch[0]->harq_processes[harq_pid]->rvidx);
    msg("PDSCH dlsch0 UE: TBS      %d\n",dlsch[0]->harq_processes[harq_pid]->TBS);
    msg("PDSCH dlsch0 UE: mcs      %d\n",dlsch[0]->harq_processes[harq_pid]->mcs);
    msg("PDSCH dlsch0 UE: pwr_off  %d\n",dlsch[0]->harq_processes[harq_pid]->dl_power_off);
  }
#endif
  dlsch[0]->active=1;

  // compute DL power control parameters   
  computeRhoA_UE(pdsch_config_dedicated, dlsch[0],dlsch[0]->harq_processes[harq_pid]->dl_power_off);

  computeRhoB_UE(pdsch_config_dedicated,&(frame_parms->pdsch_config_common),frame_parms->nb_antennas_tx_eNB,dlsch[0],dlsch[0]->harq_processes[harq_pid]->dl_power_off);

  return(0);
}


uint8_t subframe2harq_pid(LTE_DL_FRAME_PARMS *frame_parms,uint32_t frame,uint8_t subframe) {

#ifdef DEBUG_DCI
  if (frame_parms->frame_type == TDD)
    msg("dci_tools.c: subframe2_harq_pid, subframe %d for TDD configuration %d\n",subframe,frame_parms->tdd_config);
  else
    msg("dci_tools.c: subframe2_harq_pid, subframe %d for FDD \n",subframe);
#endif

  if (frame_parms->frame_type == FDD) {
    return(((frame<<1)+subframe)&7);
  }
  else {

    switch (frame_parms->tdd_config) {

    case 1:
      if ((subframe==2) || 
	  (subframe==3) || 
	  (subframe==7) ||
	  (subframe==8)) 
	switch (subframe) {
	case 2:
	case 3:
	  return(subframe-2);
	  break;
	case 7:
	case 8:
	  return(subframe-5);
	  break;
	default:
	  LOG_E(PHY,"subframe2_harq_pid, Illegal subframe %d for TDD mode %d\n",subframe,frame_parms->tdd_config);
	  //	  mac_xface->macphy_exit("");
	  return(255);
	  break;
	}
      break;
    case 2:
      if ((subframe!=2) && (subframe!=7)) {
	LOG_E(PHY,"subframe2_harq_pid, Illegal subframe %d for TDD mode %d\n",subframe,frame_parms->tdd_config);
	mac_xface->macphy_exit("");
	return(255);
      }
      return(subframe/7);
      break;
    case 3:
      if ((subframe<2) || (subframe>4)) {
	LOG_E(PHY,"subframe2_harq_pid, Illegal subframe %d for TDD mode %d\n",subframe,frame_parms->tdd_config);
	//	mac_xface->macphy_exit("");
	return(255);
      }
      return(subframe-2);
      break;
    case 4:
      if ((subframe<2) || (subframe>3)) {
	LOG_E(PHY,"subframe2_harq_pid, Illegal subframe %d for TDD mode %d\n",subframe,frame_parms->tdd_config);
	//	mac_xface->macphy_exit("");
	return(255);
      }
      return(subframe-2);
      break;
    case 5:
      if (subframe!=2) {
	LOG_E(PHY,"subframe2_harq_pid, Illegal subframe %d for TDD mode %d\n",subframe,frame_parms->tdd_config);
	//	mac_xface->macphy_exit("");
	return(255);
      }
      return(subframe-2);
      break;
    default:
      LOG_E(PHY,"subframe2_harq_pid, Unsupported TDD mode %d\n",frame_parms->tdd_config);
      //      mac_xface->macphy_exit("");
      return(255);

    }
  }
  return(255);
}

uint8_t pdcch_alloc2ul_subframe(LTE_DL_FRAME_PARMS *frame_parms,uint8_t n){

  if ((frame_parms->frame_type == TDD) && 
      (frame_parms->tdd_config == 1) &&
      ((n==1)||(n==6))) // tdd_config 0,1 SF 1,5
    return((n+6)%10);
  else if ((frame_parms->frame_type == TDD) && 
	   (frame_parms->tdd_config == 6) &&
	   ((n==0)||(n==1)||(n==5)||(n==6)))  
    return((n+7)%10);
  else if ((frame_parms->frame_type == TDD) && 
	   (frame_parms->tdd_config == 6) &&
	   (n==9)) // tdd_config 6 SF 9
    return((n+5)%10);
  else
    return((n+4)%10);

}

uint8_t ul_subframe2pdcch_alloc_subframe(LTE_DL_FRAME_PARMS *frame_parms,uint8_t n){

  if ((frame_parms->frame_type == TDD) && 
      (frame_parms->tdd_config == 1) &&
      ((n==7)||(n==2))) // tdd_config 0,1 SF 1,5
    return((n==7)? 1 : 6);
  else if ((frame_parms->frame_type == TDD) && 
	   (frame_parms->tdd_config == 6) &&
	   ((n==7)||(n==8)||(n==2)||(n==3)))  
    return((n+3)%10);
  else if ((frame_parms->frame_type == TDD) && 
	   (frame_parms->tdd_config == 6) &&
	   (n==4)) // tdd_config 6 SF 9
    return(9);
  else
    return((n+6)%10);

}

uint8_t pdcch_alloc2ul_frame(LTE_DL_FRAME_PARMS *frame_parms,uint32_t frame, uint8_t n){

  if ((frame_parms->frame_type == TDD) && 
      (frame_parms->tdd_config == 1) &&
      ((n==1)||(n==6))) // tdd_config 0,1 SF 1,5
    return(frame + (n==1 ? 0 : 1));
  else if ((frame_parms->frame_type == TDD) && 
	   (frame_parms->tdd_config == 6) &&
	   ((n==0)||(n==1)||(n==5)||(n==6)))  
    return(frame + (n>=5 ? 1 : 0));
  else if ((frame_parms->frame_type == TDD) && 
	   (frame_parms->tdd_config == 6) &&
	   (n==9)) // tdd_config 6 SF 9
    return(frame+1);
  else
    return(frame+(n>=6 ? 1 : 0));

}

uint16_t quantize_subband_pmi(PHY_MEASUREMENTS *meas,uint8_t eNB_id) {

  int i, aarx;
  uint16_t pmiq=0;
  uint16_t pmivect = 0;
  uint8_t rank = meas->rank[eNB_id];
  int pmi_re,pmi_im;

  for (i=0;i<NUMBER_OF_SUBBANDS;i++) {
    pmi_re = 0;
    pmi_im = 0;

    if (rank == 0) {
      for (aarx=0; aarx<meas->nb_antennas_rx; aarx++) {
	pmi_re += meas->subband_pmi_re[eNB_id][i][aarx];
	pmi_im += meas->subband_pmi_im[eNB_id][i][aarx];
      }

      //  pmi_re = meas->subband_pmi_re[eNB_id][i][meas->selected_rx_antennas[eNB_id][i]];
      //  pmi_im = meas->subband_pmi_im[eNB_id][i][meas->selected_rx_antennas[eNB_id][i]];

      //      printf("pmi => (%d,%d)\n",pmi_re,pmi_im);
      if ((pmi_re > pmi_im) && (pmi_re > -pmi_im))
	pmiq = PMI_2A_11;
      else if ((pmi_re < pmi_im) && (pmi_re > -pmi_im))
	pmiq = PMI_2A_1j;
      else if ((pmi_re < pmi_im) && (pmi_re < -pmi_im))
	pmiq = PMI_2A_1m1;
      else if ((pmi_re > pmi_im) && (pmi_re < -pmi_im))
	pmiq = PMI_2A_1mj;
      //      printf("subband %d, pmi%d \n",i,pmiq);
      pmivect |= (pmiq<<(2*i));
    }
    else {
      // This needs to be done properly!!!
      msg("PMI feedback for rank>1 not supported!\n");
      pmivect = 0;
    }
  }

  return(pmivect);
}

uint16_t quantize_subband_pmi2(PHY_MEASUREMENTS *meas,uint8_t eNB_id,uint8_t a_id) {

  uint8_t i;
  uint16_t pmiq=0;
  uint16_t pmivect = 0;
  uint8_t rank = meas->rank[eNB_id];
  int pmi_re,pmi_im;

  for (i=0;i<NUMBER_OF_SUBBANDS;i++) {

    if (rank == 0) {
      pmi_re = meas->subband_pmi_re[eNB_id][i][a_id];
      pmi_im = meas->subband_pmi_im[eNB_id][i][a_id];

      if ((pmi_re > pmi_im) && (pmi_re > -pmi_im))
	pmiq = PMI_2A_11;
      else if ((pmi_re < pmi_im) && (pmi_re > -pmi_im))
	pmiq = PMI_2A_1j;
      else if ((pmi_re < pmi_im) && (pmi_re < -pmi_im))
	pmiq = PMI_2A_1m1;
      else if ((pmi_re > pmi_im) && (pmi_re < -pmi_im))
	pmiq = PMI_2A_1mj;
      pmivect |= (pmiq<<(2*i));
    }
    else {
      // This needs to be done properly!!!
      pmivect = 0;
    }
  }

  return(pmivect);
}

uint16_t quantize_wideband_pmi(PHY_MEASUREMENTS *meas,uint8_t eNB_id) {

  uint16_t pmiq=0;
  uint8_t rank = meas->rank[eNB_id];
  //int pmi;
  int pmi_re,pmi_im;

  if (rank == 1) {
    //pmi =
    pmi_re = meas->wideband_pmi_re[eNB_id][meas->selected_rx_antennas[eNB_id][0]];
    pmi_im = meas->wideband_pmi_im[eNB_id][meas->selected_rx_antennas[eNB_id][0]];
    if ((pmi_re > pmi_im) && (pmi_re > -pmi_im))
      pmiq = PMI_2A_11;
    else if ((pmi_re < pmi_im) && (pmi_re > -pmi_im))
      pmiq = PMI_2A_1j;
    else if ((pmi_re < pmi_im) && (pmi_re < -pmi_im))
      pmiq = PMI_2A_1m1;
    else if ((pmi_re > pmi_im) && (pmi_re < -pmi_im))
      pmiq = PMI_2A_1mj;

  }
  else {
    // This needs to be done properly!
    pmiq = PMI_2A_11;
  }


  return(pmiq);
}
/*
  uint8_t sinr2cqi(int sinr) {
  if (sinr<-3)
  return(0);
  if (sinr>14)
  return(10);
  else
  return(3+(sinr>>1));
  }
*/
 
uint8_t sinr2cqi(int sinr,uint8_t trans_mode) {
  // int flag_LA=0;
2572 2573

if(flag_LA==0){
2574
  // Ideal Channel Estimation
2575
       if (sinr<=-4.89)
2576
    return(0);
2577
  else if (sinr < -3.53)
2578
    return(3);
2579
  else if (sinr <= -1.93)
2580
    return(4);
2581
  else if (sinr <= -0.43)
2582
    return(5);
2583
  else if (sinr <= 1.11)
2584
    return(6);
2585
  else if (sinr <= 3.26)
2586
    return(7);
2587
  else if (sinr <= 5)
2588
    return(8);
2589
  else if (sinr <= 7)
2590
    return(9);
2591
  else if (sinr <= 9)
2592 2593
    return(10);
  else if (sinr <= 11)
2594 2595
    return(11);
  else if (sinr <= 13)
2596
    return(12);
2597
  else if (sinr <= 15.5)
2598
    return(13);
2599
  else if (sinr <= 17.5)
2600
    return(14);
2601
  else if (sinr > 19.5)
2602 2603
    return(15);
  }
2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620
 else{
   int h=0;
   int trans_mode_tmp;
   if (trans_mode ==5)
     trans_mode_tmp=2;
  else 
    if(trans_mode ==6)
      trans_mode_tmp=3;
    else
      trans_mode_tmp = trans_mode-1;
   
   for(h=0;h<16;h++){
     if(sinr<=sinr_to_cqi[trans_mode_tmp][h])
       return(h);
   }
 }
 return(0);
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}
//uint32_t fill_subband_cqi(PHY_MEASUREMENTS *meas,uint8_t eNB_id) {
//
//	uint8_t i;
////	uint16_t cqivect = 0;
//	uint32_t cqivect = 0;
//
////	char diff_cqi;
//	int diff_cqi=0;
//
//	for (i=0;i<NUMBER_OF_SUBBANDS;i++) {
//
//		diff_cqi = -sinr2cqi(meas->wideband_cqi_dB[eNB_id][0]) + sinr2cqi(meas->subband_cqi_dB[eNB_id][0][i]);
//
//		// Note, this is Table 7.2.1-2 from 36.213
//		if (diff_cqi<=-1)
//			diff_cqi = 3;
//		else if (diff_cqi>2)
//			diff_cqi = 2;
//		cqivect |= (diff_cqi<<(2*i));
//
//	}
//
//	return(cqivect);
//}


uint32_t fill_subband_cqi(PHY_MEASUREMENTS *meas,uint8_t eNB_id,uint8_t trans_mode) {

  uint8_t i;

  uint32_t cqivect = 0,offset=0;


  int diff_cqi=0;

  for (i=0;i<NUMBER_OF_SUBBANDS;i++) {

    diff_cqi = -sinr2cqi(meas->wideband_cqi_avg[eNB_id],trans_mode) + sinr2cqi(meas->subband_cqi_tot_dB[eNB_id][i],trans_mode);

    // Note, this is Table 7.2.1-2 from 36.213
    if (diff_cqi<=-1)
      offset = 3;
    else
      if (diff_cqi>=2)
	offset = 2;
      else
	offset=(uint32_t)diff_cqi;

    cqivect |= (offset<<(2*i));

  }

  return(cqivect);
}

void fill_CQI(void *o,UCI_format_t uci_format,PHY_MEASUREMENTS *meas,uint8_t eNB_id,uint16_t rnti, uint8_t trans_mode, double sinr_eff) {
  
  //  msg("[PHY][UE] Filling CQI for eNB %d, meas->wideband_cqi_tot[%d] %d\n",
  //      eNB_id,eNB_id,meas->wideband_cqi_tot[eNB_id]);
  double sinr_tmp;
  if(flag_LA==1)
    sinr_tmp = sinr_eff;
  else
    sinr_tmp = meas->wideband_cqi_avg[eNB_id];

  switch (uci_format) {
  case wideband_cqi_rank1_2A:
    ((wideband_cqi_rank1_2A_5MHz *)o)->cqi1 = sinr2cqi(sinr_tmp,trans_mode);
    ((wideband_cqi_rank1_2A_5MHz *)o)->pmi  = quantize_subband_pmi(meas,eNB_id);
    break;
  case wideband_cqi_rank2_2A:
    ((wideband_cqi_rank2_2A_5MHz *)o)->cqi1 = sinr2cqi(sinr_tmp,trans_mode); //FIXME: calculate rank2 cqi
    ((wideband_cqi_rank2_2A_5MHz *)o)->cqi2 = sinr2cqi(sinr_tmp,trans_mode); //FIXME: calculate rank2 cqi
    ((wideband_cqi_rank2_2A_5MHz *)o)->pmi  = quantize_subband_pmi(meas,eNB_id);
    break;
  case HLC_subband_cqi_nopmi:
    ((HLC_subband_cqi_nopmi_5MHz *)o)->cqi1     = sinr2cqi(sinr_tmp,trans_mode);
    ((HLC_subband_cqi_nopmi_5MHz *)o)->diffcqi1 = fill_subband_cqi(meas,eNB_id,trans_mode);
    break;
  case HLC_subband_cqi_rank1_2A:
    ((HLC_subband_cqi_rank1_2A_5MHz *)o)->cqi1     = sinr2cqi(sinr_tmp,trans_mode);
    ((HLC_subband_cqi_rank1_2A_5MHz *)o)->diffcqi1 = fill_subband_cqi(meas,eNB_id,trans_mode);
    ((HLC_subband_cqi_rank1_2A_5MHz *)o)->pmi      = quantize_wideband_pmi(meas,eNB_id);
    break;
  case HLC_subband_cqi_rank2_2A:
    // This has to be improved!!!
    ((HLC_subband_cqi_rank2_2A_5MHz *)o)->cqi1     = sinr2cqi(sinr_tmp,trans_mode);
    ((HLC_subband_cqi_rank2_2A_5MHz *)o)->diffcqi1 = fill_subband_cqi(meas,eNB_id,trans_mode);
    ((HLC_subband_cqi_rank2_2A_5MHz *)o)->cqi2     = sinr2cqi(sinr_tmp,trans_mode);
    ((HLC_subband_cqi_rank2_2A_5MHz *)o)->diffcqi2 = fill_subband_cqi(meas,eNB_id,trans_mode);
    ((HLC_subband_cqi_rank2_2A_5MHz *)o)->pmi      = quantize_subband_pmi(meas,eNB_id);
    break;
  case HLC_subband_cqi_mcs_CBA:
    // this is the cba mcs uci for cba transmission 
    ((HLC_subband_cqi_mcs_CBA_5MHz *)o)->mcs     = 2; //fixme
    ((HLC_subband_cqi_mcs_CBA_5MHz *)o)->crnti  = rnti;
    LOG_I(PHY,"fill uci for cba rnti %x, mcs %d \n", rnti, 2);
    break;
  case ue_selected:
    LOG_E(PHY,"fill_CQI ue_selected CQI not supported yet!!!\n");
    mac_xface->macphy_exit("");
    break;
  default:
    LOG_E(PHY,"unsupported CQI mode (%d)!!!\n",uci_format);
    mac_xface->macphy_exit("");
    break;

  }
}

void reset_cba_uci(void *o) {
  // this is the cba mcs uci for cba transmission 
  ((HLC_subband_cqi_mcs_CBA_5MHz *)o)->mcs     = 0; //fixme
  ((HLC_subband_cqi_mcs_CBA_5MHz *)o)->crnti  = 0x0;
}

uint32_t pmi_extend(LTE_DL_FRAME_PARMS *frame_parms,uint8_t wideband_pmi) {

  uint8_t i,wideband_pmi2=wideband_pmi&3;
  uint32_t pmi_ex = 0;

  for (i=0;i<14;i+=2)
    pmi_ex|=(wideband_pmi2<<i);

  return(pmi_ex);
}


int generate_ue_ulsch_params_from_dci(void *dci_pdu,
				      uint16_t rnti,
				      uint8_t subframe,
				      DCI_format_t dci_format,
				      PHY_VARS_UE *phy_vars_ue,
				      uint16_t si_rnti,
				      uint16_t ra_rnti,
				      uint16_t p_rnti,
				      uint16_t cba_rnti,
				      uint8_t eNB_id,
				      uint8_t use_srs) {

  uint8_t harq_pid;
  uint8_t transmission_mode = phy_vars_ue->transmission_mode[eNB_id];
  ANFBmode_t AckNackFBMode = phy_vars_ue->pucch_config_dedicated[eNB_id].tdd_AckNackFeedbackMode;
  LTE_UE_ULSCH_t *ulsch = phy_vars_ue->ulsch_ue[eNB_id];
  //  LTE_UE_DLSCH_t **dlsch = phy_vars_ue->dlsch_ue[0];
  PHY_MEASUREMENTS *meas = &phy_vars_ue->PHY_measurements;
  LTE_DL_FRAME_PARMS *frame_parms = &phy_vars_ue->lte_frame_parms;
  //  uint32_t current_dlsch_cqi = phy_vars_ue->current_dlsch_cqi[eNB_id];

  uint32_t cqi_req;
  uint32_t dai;
  uint32_t cshift;
  uint32_t TPC;
  uint32_t ndi;
  uint32_t mcs;
  uint32_t rballoc,RIV_max;
  //  uint32_t hopping;
  //  uint32_t type;

  if (dci_format == format0) {

    if (rnti == ra_rnti)
      harq_pid = 0;
    else
      harq_pid = subframe2harq_pid(frame_parms,
				   pdcch_alloc2ul_frame(frame_parms,phy_vars_ue->frame,subframe),
				   pdcch_alloc2ul_subframe(frame_parms,subframe));
    /*    msg("Scheduling eNB ULSCH reception for frame %d, subframe %d harq_pid = %d\n",
	  pdcch_alloc2ul_frame(frame_parms,phy_vars_ue->frame,subframe),
	  pdcch_alloc2ul_subframe(frame_parms,subframe),harq_pid);
    */
    if (harq_pid == 255) {
      LOG_E(PHY, "frame %d, subframe %d, rnti %x, format %d: illegal harq_pid!\n",
	  phy_vars_ue->frame, subframe, rnti, dci_format);
      return(-1);
    }

    switch (frame_parms->N_RB_DL) {
    case 6:
      if (frame_parms->frame_type == TDD) {
	cqi_req = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->cqi_req;
	dai     = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->dai;
	cshift  = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->cshift;
	TPC     = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->TPC;
	ndi     = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->ndi;
	mcs     = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
	rballoc = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
	//	hopping = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->hopping;
	//	type    = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->type;
      }
      else {
	cqi_req = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->cqi_req;
	cshift  = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->cshift;
	TPC     = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->TPC;
	ndi     = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->ndi;
	mcs     = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->mcs;
	rballoc = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->rballoc;
	//	hopping = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->hopping;
	//	type    = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->type;
      }
      RIV_max = RIV_max6;
      ulsch->harq_processes[harq_pid]->first_rb                              = RIV2first_rb_LUT6[rballoc];
      ulsch->harq_processes[harq_pid]->nb_rb                                 = RIV2nb_rb_LUT6[rballoc];

      break;

    case 25:
      if (frame_parms->frame_type == TDD) {
	cqi_req = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->cqi_req;
	dai     = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->dai;
	cshift  = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->cshift;
	TPC     = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->TPC;
	ndi     = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->ndi;
	mcs     = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
	rballoc = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
	//	hopping = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->hopping;
	//	type    = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->type;
      }
      else {
	cqi_req = ((DCI0_5MHz_FDD_t *)dci_pdu)->cqi_req;
	cshift  = ((DCI0_5MHz_FDD_t *)dci_pdu)->cshift;
	TPC     = ((DCI0_5MHz_FDD_t *)dci_pdu)->TPC;
	ndi     = ((DCI0_5MHz_FDD_t *)dci_pdu)->ndi;
	mcs     = ((DCI0_5MHz_FDD_t *)dci_pdu)->mcs;
	rballoc = ((DCI0_5MHz_FDD_t *)dci_pdu)->rballoc;
	//	hopping = ((DCI0_5MHz_FDD_t *)dci_pdu)->hopping;
	//	type    = ((DCI0_5MHz_FDD_t *)dci_pdu)->type;
      }
      RIV_max = RIV_max25;
      ulsch->harq_processes[harq_pid]->first_rb                              = RIV2first_rb_LUT25[rballoc];
      ulsch->harq_processes[harq_pid]->nb_rb                                 = RIV2nb_rb_LUT25[rballoc];
      //      printf("***********rballoc %d, first_rb %d, nb_rb %d\n",rballoc,ulsch->harq_processes[harq_pid]->first_rb,ulsch->harq_processes[harq_pid]->nb_rb);
      break;

    case 50:
      if (frame_parms->frame_type == TDD) {
	cqi_req = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->cqi_req;
	dai     = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->dai;
	cshift  = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->cshift;
	TPC     = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->TPC;
	ndi     = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->ndi;
	mcs     = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->mcs;
	rballoc = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->rballoc;
	//	hopping = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->hopping;
	//	type    = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->type;
      }
      else {
	cqi_req = ((DCI0_10MHz_FDD_t *)dci_pdu)->cqi_req;
	cshift  = ((DCI0_10MHz_FDD_t *)dci_pdu)->cshift;
	TPC     = ((DCI0_10MHz_FDD_t *)dci_pdu)->TPC;
	ndi     = ((DCI0_10MHz_FDD_t *)dci_pdu)->ndi;
	mcs     = ((DCI0_10MHz_FDD_t *)dci_pdu)->mcs;
	rballoc = ((DCI0_10MHz_FDD_t *)dci_pdu)->rballoc;
	//	hopping = ((DCI0_10MHz_FDD_t *)dci_pdu)->hopping;
	//	type    = ((DCI0_10MHz_FDD_t *)dci_pdu)->type;
      }

      RIV_max = RIV_max50;
      ulsch->harq_processes[harq_pid]->first_rb = RIV2first_rb_LUT50[rballoc];
      ulsch->harq_processes[harq_pid]->nb_rb    = RIV2nb_rb_LUT50[rballoc];

      break;
      
    case 100:
      if (frame_parms->frame_type == TDD) {
	cqi_req = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->cqi_req;
	dai     = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->dai;
	cshift  = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->cshift;
	TPC     = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->TPC;
	ndi     = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->ndi;
	mcs     = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->mcs;
	rballoc = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->rballoc;
	//	hopping = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->hopping;
	//	type    = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->type;
      }
      else {
	cqi_req = ((DCI0_20MHz_FDD_t *)dci_pdu)->cqi_req;
	cshift  = ((DCI0_20MHz_FDD_t *)dci_pdu)->cshift;
	TPC     = ((DCI0_20MHz_FDD_t *)dci_pdu)->TPC;
	ndi     = ((DCI0_20MHz_FDD_t *)dci_pdu)->ndi;
	mcs     = ((DCI0_20MHz_FDD_t *)dci_pdu)->mcs;
	rballoc = ((DCI0_20MHz_FDD_t *)dci_pdu)->rballoc;
	//	hopping = ((DCI0_20MHz_FDD_t *)dci_pdu)->hopping;
	//	type    = ((DCI0_20MHz_FDD_t *)dci_pdu)->type;
      }
      RIV_max = RIV_max100;
      ulsch->harq_processes[harq_pid]->first_rb                              = RIV2first_rb_LUT100[rballoc];
      ulsch->harq_processes[harq_pid]->nb_rb                                 = RIV2nb_rb_LUT100[rballoc];

      printf("rb_alloc (20 MHz dci) %d\n",rballoc);
      break;

    default:
      break;
    }


    if (rballoc > RIV_max) {
      LOG_E(PHY,"frame %d, subframe %d, rnti %x, format %d: FATAL ERROR: generate_ue_ulsch_params_from_dci, rb_alloc > RIV_max\n", 	  
	  phy_vars_ue->frame, subframe, rnti, dci_format);
      return(-1);
    }


    // indicate that this process is to be serviced in subframe n+4
    if ((rnti >= cba_rnti) && (rnti < p_rnti))
      ulsch->harq_processes[harq_pid]->subframe_cba_scheduling_flag = 1;
    else 
      ulsch->harq_processes[harq_pid]->subframe_scheduling_flag = 1;
    
    ulsch->harq_processes[harq_pid]->TPC                                   = TPC;

    if (phy_vars_ue->ul_power_control_dedicated[eNB_id].accumulationEnabled == 1) {
      /*
	msg("[PHY][UE %d][PUSCH %d] Frame %d subframe %d: f_pusch (ACC) %d, adjusting by %d (TPC %d)\n",
	phy_vars_ue->Mod_id,harq_pid,phy_vars_ue->frame,subframe,ulsch->f_pusch,
	delta_PUSCH_acc[phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->TPC],
	phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->TPC);
      */
      ulsch->f_pusch += delta_PUSCH_acc[phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->TPC];
    }
    else {
      /*
	msg("[PHY][UE %d][PUSCH %d] Frame %d subframe %d: f_pusch (ABS) %d, adjusting to %d (TPC %d)\n",
	phy_vars_ue->Mod_id,harq_pid,phy_vars_ue->frame,subframe,ulsch->f_pusch,
	delta_PUSCH_abs[phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->TPC],
	phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->TPC);
      */
      ulsch->f_pusch = delta_PUSCH_abs[phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->TPC];
    }
    ulsch->harq_processes[harq_pid]->Ndi                                   = ndi;

    ulsch->harq_processes[harq_pid]->n_DMRS                                = cshift;     

    //printf("nb_rb %d, first_rb %d (RIV %d)\n",ulsch->harq_processes[harq_pid]->nb_rb,ulsch->harq_processes[harq_pid]->first_rb,rballoc);
    if ((rnti >= cba_rnti) && (rnti < p_rnti)){
      // ulsch->cba_rnti[0]=rnti;
    } else {
      ulsch->rnti = rnti;
    }
    //    msg("[PHY][UE] DCI format 0: harq_pid %d nb_rb %d, rballoc %d\n",harq_pid,ulsch->harq_processes[harq_pid]->nb_rb,
    //	   ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->rballoc);
    //Mapping of cyclic shift field in DCI format0 to n_DMRS2 (3GPP 36.211, Table 5.5.2.1.1-1)
    if(cshift == 0)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 0;
    else if(cshift == 1)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 6;
    else if(cshift == 2)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 3;
    else if(cshift == 3)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 4;
    else if(cshift == 4)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 2;
    else if(cshift == 5)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 8;
    else if(cshift == 6)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 10;
    else if(cshift == 7)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 9;

    LOG_D(PHY,"[UE %d][PUSCH %d] Frame %d, subframe %d : Programming PUSCH with n_DMRS2 %d (cshift %d)\n",
	  phy_vars_ue->Mod_id,harq_pid,phy_vars_ue->frame,subframe,ulsch->harq_processes[harq_pid]->n_DMRS2,cshift);

    //reserved for cooperative communication
    /*
      if(ulsch->n_DMRS2 == 6)
      ulsch->cooperation_flag = 2;
      else
      ulsch->cooperation_flag = 0;
    */

    if ((ulsch->harq_processes[harq_pid]->nb_rb>0) && (ulsch->harq_processes[harq_pid]->nb_rb < 25))
      ulsch->power_offset = ue_power_offsets[ulsch->harq_processes[harq_pid]->nb_rb-1];

    //    if (ulsch->harq_processes[harq_pid]->Ndi == 1)
    //    ulsch->harq_processes[harq_pid]->status = ACTIVE;


    if (cqi_req == 1) {
      ulsch->O_RI = 1; //we only support 2 antenna ports, so this is always 1 according to 3GPP 36.213 Table 
      switch(transmission_mode){ 
	// The aperiodic CQI reporting mode is fixed for every transmission mode instead of being configured by higher layer signaling
      case 1:
	if ((rnti >= cba_rnti) && (rnti < p_rnti)){
	  ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
	  ulsch->uci_format                          = HLC_subband_cqi_mcs_CBA;
	  ulsch->o_RI[0]                             = 0;
	}
	else  if(meas->rank[eNB_id] == 0){
	  ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
	  ulsch->uci_format                          = HLC_subband_cqi_nopmi;
	  ulsch->o_RI[0]                             = 0;
	}
	else{
	  ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
	  ulsch->uci_format                          = HLC_subband_cqi_nopmi;
	  ulsch->o_RI[0]                             = 1;
	}
	break;
      case 2:
	if ((rnti >= cba_rnti) && (rnti < p_rnti)){
	  ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
	  ulsch->uci_format                          = HLC_subband_cqi_mcs_CBA;
	  ulsch->o_RI[0]                             = 0;
	} 
	else if(meas->rank[eNB_id] == 0){
	  ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
	  ulsch->uci_format                          = HLC_subband_cqi_nopmi;
	  ulsch->o_RI[0]                             = 0;
	}
	else{
	  ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
	  ulsch->uci_format                          = HLC_subband_cqi_nopmi;
	  ulsch->o_RI[0]                             = 1;
	}
	break;
      case 3:
	if ((rnti >= cba_rnti) && (rnti < p_rnti)){
	  ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
	  ulsch->uci_format                          = HLC_subband_cqi_mcs_CBA;
	  ulsch->o_RI[0]                             = 0;
	} 
	else if(meas->rank[eNB_id] == 0){
	  ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
	  ulsch->uci_format                          = HLC_subband_cqi_nopmi;
	  ulsch->o_RI[0]                             = 0;
	}
	else{
	  ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
	  ulsch->uci_format                          = HLC_subband_cqi_nopmi;
	  ulsch->o_RI[0]                             = 1;
	}
	break;
      case 4:
	if ((rnti >= cba_rnti) && (rnti < p_rnti)){
	  ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
	  ulsch->uci_format                          = HLC_subband_cqi_mcs_CBA;
	  ulsch->o_RI[0]                             = 0;
	}
	else if(meas->rank[eNB_id] == 0){
	  ulsch->O                                   = sizeof_wideband_cqi_rank1_2A_5MHz;
	  ulsch->uci_format                          = wideband_cqi_rank1_2A;
	  ulsch->o_RI[0]                             = 0;
	}
	else{
	  ulsch->O                                   = sizeof_wideband_cqi_rank2_2A_5MHz;
	  ulsch->uci_format                          = wideband_cqi_rank2_2A;
	  ulsch->o_RI[0]                             = 1;
	}
	break;
      case 5:
	if ((rnti >= cba_rnti) && (rnti < p_rnti)){
	  ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
	  ulsch->uci_format                          = HLC_subband_cqi_mcs_CBA;
	  ulsch->o_RI[0]                             = 0;
	}
	else if(meas->rank[eNB_id] == 0){
	  ulsch->O                                   = sizeof_wideband_cqi_rank1_2A_5MHz;
	  ulsch->uci_format                          = wideband_cqi_rank1_2A;
	  ulsch->o_RI[0]                             = 0;
	}
	else{
	  ulsch->O                                   = sizeof_wideband_cqi_rank2_2A_5MHz;
	  ulsch->uci_format                          = wideband_cqi_rank2_2A;
	  ulsch->o_RI[0]                             = 1;
	}
	break;
      case 6:
	if ((rnti >= cba_rnti) && (rnti < p_rnti)){
	  ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
	  ulsch->uci_format                          = HLC_subband_cqi_mcs_CBA;
	  ulsch->o_RI[0]                             = 0;
	}
	else if(meas->rank[eNB_id] == 0){
	  ulsch->O                                   = sizeof_wideband_cqi_rank1_2A_5MHz;
	  ulsch->uci_format                          = wideband_cqi_rank1_2A;
	  ulsch->o_RI[0]                             = 0;
	}
	else{
	  ulsch->O                                   = sizeof_wideband_cqi_rank2_2A_5MHz;
	  ulsch->uci_format                          = wideband_cqi_rank2_2A;
	  ulsch->o_RI[0]                             = 1;
	}
	break;
      case 7:
	if ((rnti >= cba_rnti) && (rnti < p_rnti)){
	  ulsch->O                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
	  ulsch->uci_format                          = HLC_subband_cqi_mcs_CBA;
	  ulsch->o_RI[0]                             = 0;
	}
	else if(meas->rank[eNB_id] == 0){
	  ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
	  ulsch->uci_format                          = HLC_subband_cqi_nopmi;
	  ulsch->o_RI[0]                             = 0;
	}
	else{
	  ulsch->O                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
	  ulsch->uci_format                          = HLC_subband_cqi_nopmi;
	  ulsch->o_RI[0]                             = 1;
	}
	break;
      default:
	LOG_E(PHY,"Incorrect Transmission Mode \n");
	break;
      }
    }
    else {
      ulsch->O_RI = 0;
      ulsch->O                                   = 0;
      ulsch->uci_format                          = HLC_subband_cqi_nopmi;
    }
    
    print_CQI(ulsch->o,ulsch->uci_format,eNB_id);

    //FK: moved this part to ulsch_coding to be more recent
    /*
      fill_CQI(ulsch->o,ulsch->uci_format,meas,eNB_id,transmission_mode);
      print_CQI(ulsch->o,ulsch->uci_format,eNB_id);
   
      // save PUSCH pmi for later (transmission modes 4,5,6)
      // msg("ulsch: saving pmi for DL %x\n",pmi2hex_2Ar1(((wideband_cqi_rank1_2A_5MHz *)ulsch->o)->pmi));
      dlsch[0]->pmi_alloc = ((wideband_cqi_rank1_2A_5MHz *)ulsch->o)->pmi;
    */
    /*
    if (frame_parms->frame_type == TDD) 
      // 2bits if together with SR
      // 1 bit if ACK only?
      // check dai business
      ulsch->harq_processes[harq_pid]->O_ACK                                 = 1; //(dai+1)&3;
    else 
    */  ulsch->harq_processes[harq_pid]->O_ACK                                 = 1;
    

    ulsch->beta_offset_cqi_times8                = beta_cqi[phy_vars_ue->pusch_config_dedicated[eNB_id].betaOffset_CQI_Index];//18;
    ulsch->beta_offset_ri_times8                 = beta_ri[phy_vars_ue->pusch_config_dedicated[eNB_id].betaOffset_RI_Index];//10;
    ulsch->beta_offset_harqack_times8            = beta_ack[phy_vars_ue->pusch_config_dedicated[eNB_id].betaOffset_ACK_Index];//16;

    ulsch->Nsymb_pusch                             = 12-(frame_parms->Ncp<<1)-(use_srs==0?0:1);
    ulsch->srs_active                              = use_srs;
    ulsch->bundling = 1-AckNackFBMode;

    if (ulsch->harq_processes[harq_pid]->Ndi == 1) {
      if ((rnti >= cba_rnti) && (rnti < p_rnti))
		ulsch->harq_processes[harq_pid]->status = CBA_ACTIVE;
      else 
		ulsch->harq_processes[harq_pid]->status = ACTIVE;
      ulsch->harq_processes[harq_pid]->rvidx = 0;
      ulsch->harq_processes[harq_pid]->mcs         = mcs;
      //      ulsch->harq_processes[harq_pid]->calibration_flag =0;
      if (ulsch->harq_processes[harq_pid]->mcs < 29)
	ulsch->harq_processes[harq_pid]->TBS         = TBStable[get_I_TBS_UL(ulsch->harq_processes[harq_pid]->mcs)][ulsch->harq_processes[harq_pid]->nb_rb-1];
      /*
	else if (ulsch->harq_processes[harq_pid]->mcs == 29) {
	ulsch->harq_processes[harq_pid]->mcs = 4;
	ulsch->harq_processes[harq_pid]->TBS         = TBStable[get_I_TBS_UL(ulsch->harq_processes[harq_pid]->mcs)][ulsch->harq_processes[harq_pid]->nb_rb-1];
	//	ulsch->harq_processes[harq_pid]->calibration_flag =1;
	//	printf("Auto-Calibration (UE): mcs %d, TBS %d, nb_rb %d\n",ulsch->harq_processes[harq_pid]->mcs,ulsch->harq_processes[harq_pid]->TBS,ulsch->harq_processes[harq_pid]->nb_rb);
	}*/
      ulsch->harq_processes[harq_pid]->Msc_initial   = 12*ulsch->harq_processes[harq_pid]->nb_rb;
      ulsch->harq_processes[harq_pid]->Nsymb_initial = ulsch->Nsymb_pusch;
      ulsch->harq_processes[harq_pid]->round = 0;

      // a Ndi=1 automatically acknowledges previous PUSCH transmission
      if (phy_vars_ue->ulsch_ue_Msg3_active[eNB_id] == 1) 
	phy_vars_ue->ulsch_ue_Msg3_active[eNB_id] = 0;  
    }
    else {
      //      printf("Ndi = 0 : Setting RVidx from mcs %d\n",((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->mcs);
      ulsch->harq_processes[harq_pid]->rvidx = mcs - 28;
      //      ulsch->harq_processes[harq_pid]->round++;
    }

    // ulsch->n_DMRS2 = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->cshift;

#ifdef DEBUG_DCI
    msg("Format 0 DCI : ulsch (ue): NBRB        %d\n",ulsch->harq_processes[harq_pid]->nb_rb);
    msg("Format 0 DCI :ulsch (ue): first_rb    %d\n",ulsch->harq_processes[harq_pid]->first_rb);
    msg("Format 0 DCI :ulsch (ue): harq_pid    %d\n",harq_pid);
    msg("Format 0 DCI :ulsch (ue): Ndi         %d\n",ulsch->harq_processes[harq_pid]->Ndi);
    msg("Format 0 DCI :ulsch (ue): TBS         %d\n",ulsch->harq_processes[harq_pid]->TBS);
    msg("Format 0 DCI :ulsch (ue): mcs         %d\n",ulsch->harq_processes[harq_pid]->mcs);
    msg("Format 0 DCI :ulsch (ue): O           %d\n",ulsch->O);
    if (frame_parms->frame_type == TDD)
      msg("Format 0 DCI :ulsch (ue): O_ACK/DAI   %d/%d\n",ulsch->harq_processes[harq_pid]->O_ACK,dai);
    else      
      msg("Format 0 DCI :ulsch (ue): O_ACK       %d\n",ulsch->harq_processes[harq_pid]->O_ACK);

    msg("Format 0 DCI :ulsch (ue): Nsymb_pusch   %d\n",ulsch->Nsymb_pusch);
    msg("Format 0 DCI :ulsch (ue): cshift        %d\n",ulsch->harq_processes[harq_pid]->n_DMRS2);
3211 3212
#else
    UNUSED_VARIABLE(dai);
3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574
#endif
    return(0);
  }
  else {
    LOG_E(PHY,"frame %d, subframe %d: FATAL ERROR, generate_ue_ulsch_params_from_dci, Illegal dci_format %d\n",
	phy_vars_ue->frame, subframe,dci_format);
    return(-1);
  }

}

int generate_eNB_ulsch_params_from_dci(void *dci_pdu,
				       uint16_t rnti,
				       uint8_t subframe,
				       DCI_format_t dci_format,
				       uint8_t UE_id,
				       PHY_VARS_eNB *phy_vars_eNB,
				       uint16_t si_rnti,
				       uint16_t ra_rnti,
				       uint16_t p_rnti,
				       uint16_t cba_rnti,
				       uint8_t use_srs) {

  uint8_t harq_pid;
  uint32_t rb_alloc;
  uint8_t transmission_mode=phy_vars_eNB->transmission_mode[UE_id];
  ANFBmode_t AckNackFBMode = phy_vars_eNB->pucch_config_dedicated[UE_id].tdd_AckNackFeedbackMode;
  LTE_eNB_ULSCH_t *ulsch=phy_vars_eNB->ulsch_eNB[UE_id];
  LTE_DL_FRAME_PARMS *frame_parms = &phy_vars_eNB->lte_frame_parms;

  uint32_t cqi_req;
  uint32_t dai=0;
  uint32_t cshift;
  uint32_t TPC;
  uint32_t ndi;
  uint32_t mcs;
  uint32_t rballoc,RIV_max;
  //  uint32_t hopping;
  //  uint32_t type;

#ifdef DEBUG_DCI
  msg("dci_tools.c: filling eNB ulsch params for rnti %x, dci format %d, dci %x, subframe %d\n",
      rnti,dci_format,*(uint32_t*)dci_pdu,subframe);
#endif

  if (dci_format == format0) {

    harq_pid = subframe2harq_pid(frame_parms,			      
				 pdcch_alloc2ul_frame(frame_parms,
						      phy_vars_eNB->frame,
						      subframe),
				 pdcch_alloc2ul_subframe(frame_parms,subframe));



    switch (frame_parms->N_RB_DL) {
    case 6:
      if (frame_parms->frame_type == TDD) {
	cqi_req = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->cqi_req;
	dai     = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->dai;
	cshift  = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->cshift;
	TPC     = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->TPC;
	ndi     = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->ndi;
	mcs     = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
	rballoc = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
	//	hopping = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->hopping;
	//	type    = ((DCI0_1_5MHz_TDD_1_6_t *)dci_pdu)->type;
      }
      else {
	cqi_req = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->cqi_req;
	cshift  = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->cshift;
	TPC     = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->TPC;
	ndi     = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->ndi;
	mcs     = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->mcs;
	rballoc = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->rballoc;
	//	hopping = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->hopping;
	//	type    = ((DCI0_1_5MHz_FDD_t *)dci_pdu)->type;
      }
      RIV_max = RIV_max6;
      ulsch->harq_processes[harq_pid]->first_rb                              = RIV2first_rb_LUT6[rballoc];
      ulsch->harq_processes[harq_pid]->nb_rb                                 = RIV2nb_rb_LUT6[rballoc];

      break;
    case 25:
      if (frame_parms->frame_type == TDD) {
	cqi_req = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->cqi_req;
	dai     = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->dai;
	cshift  = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->cshift;
	TPC     = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->TPC;
	ndi     = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->ndi;
	mcs     = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
	rballoc = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
	//	hopping = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->hopping;
	//	type    = ((DCI0_5MHz_TDD_1_6_t *)dci_pdu)->type;
      }
      else {
	cqi_req = ((DCI0_5MHz_FDD_t *)dci_pdu)->cqi_req;
	cshift  = ((DCI0_5MHz_FDD_t *)dci_pdu)->cshift;
	TPC     = ((DCI0_5MHz_FDD_t *)dci_pdu)->TPC;
	ndi     = ((DCI0_5MHz_FDD_t *)dci_pdu)->ndi;
	mcs     = ((DCI0_5MHz_FDD_t *)dci_pdu)->mcs;
	rballoc = ((DCI0_5MHz_FDD_t *)dci_pdu)->rballoc;
	//	hopping = ((DCI0_5MHz_FDD_t *)dci_pdu)->hopping;
	//	type    = ((DCI0_5MHz_FDD_t *)dci_pdu)->type;
      }
      RIV_max = RIV_max25;
      ulsch->harq_processes[harq_pid]->first_rb                              = RIV2first_rb_LUT25[rballoc];
      ulsch->harq_processes[harq_pid]->nb_rb                                 = RIV2nb_rb_LUT25[rballoc];

      break;
    case 50:
      if (frame_parms->frame_type == TDD) {
	cqi_req = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->cqi_req;
	dai     = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->dai;
	cshift  = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->cshift;
	TPC     = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->TPC;
	ndi     = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->ndi;
	mcs     = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->mcs;
	rballoc = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->rballoc;
	//	hopping = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->hopping;
	//	type    = ((DCI0_10MHz_TDD_1_6_t *)dci_pdu)->type;
      }
      else {
	cqi_req = ((DCI0_10MHz_FDD_t *)dci_pdu)->cqi_req;
	cshift  = ((DCI0_10MHz_FDD_t *)dci_pdu)->cshift;
	TPC     = ((DCI0_10MHz_FDD_t *)dci_pdu)->TPC;
	ndi     = ((DCI0_10MHz_FDD_t *)dci_pdu)->ndi;
	mcs     = ((DCI0_10MHz_FDD_t *)dci_pdu)->mcs;
	rballoc = ((DCI0_10MHz_FDD_t *)dci_pdu)->rballoc;
	//	hopping = ((DCI0_10MHz_FDD_t *)dci_pdu)->hopping;
	//	type    = ((DCI0_10MHz_FDD_t *)dci_pdu)->type;
      }
      RIV_max = RIV_max50;
      ulsch->harq_processes[harq_pid]->first_rb                              = RIV2first_rb_LUT50[rballoc];
      ulsch->harq_processes[harq_pid]->nb_rb                                 = RIV2nb_rb_LUT50[rballoc];

      break;
    case 100:
      if (frame_parms->frame_type == TDD) {
	cqi_req = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->cqi_req;
	dai     = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->dai;
	cshift  = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->cshift;
	TPC     = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->TPC;
	ndi     = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->ndi;
	mcs     = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->mcs;
	rballoc = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->rballoc;
	//	hopping = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->hopping;
	//	type    = ((DCI0_20MHz_TDD_1_6_t *)dci_pdu)->type;
      }
      else {
	cqi_req = ((DCI0_20MHz_FDD_t *)dci_pdu)->cqi_req;
	cshift  = ((DCI0_20MHz_FDD_t *)dci_pdu)->cshift;
	TPC     = ((DCI0_20MHz_FDD_t *)dci_pdu)->TPC;
	ndi     = ((DCI0_20MHz_FDD_t *)dci_pdu)->ndi;
	mcs     = ((DCI0_20MHz_FDD_t *)dci_pdu)->mcs;
	rballoc = ((DCI0_20MHz_FDD_t *)dci_pdu)->rballoc;
	//	hopping = ((DCI0_20MHz_FDD_t *)dci_pdu)->hopping;
	//	type    = ((DCI0_20MHz_FDD_t *)dci_pdu)->type;
      }
      RIV_max = RIV_max100;
      ulsch->harq_processes[harq_pid]->first_rb                              = RIV2first_rb_LUT100[rballoc];
      ulsch->harq_processes[harq_pid]->nb_rb                                 = RIV2nb_rb_LUT100[rballoc];

     printf("eNB: rb_alloc (20 MHz dci) %d\n",rballoc);
      break;
    }
      
    rb_alloc = rballoc;
    if (rb_alloc>RIV_max) {
      LOG_E(PHY,"Format 0: rb_alloc > RIV_max\n");
      return(-1);
    }

#ifdef DEBUG_DCI
    msg("generate_eNB_ulsch_params_from_dci: subframe %d, rnti %x,harq_pid %d\n",subframe,rnti,harq_pid);
#endif

    ulsch->harq_processes[harq_pid]->dci_alloc                             = 1;
    ulsch->harq_processes[harq_pid]->rar_alloc                             = 0;
    ulsch->harq_processes[harq_pid]->TPC                                   = TPC;
    ulsch->harq_processes[harq_pid]->Ndi                                   = ndi;

    ulsch->harq_processes[harq_pid]->n_DMRS                                = cshift;                               


    if (cqi_req == 1) {
      ulsch->O_RI = 1; //we only support 2 antenna ports, so this is always 1 according to 3GPP 36.213 Table 
      switch(transmission_mode){ 
	// The aperiodic CQI reporting mode is fixed for every transmission mode instead of being configured by higher layer signaling
      case 1:
	if ((rnti >= cba_rnti) && (rnti < p_rnti)){ 
	  ulsch->Or2                                   = 0;
	  ulsch->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
	  ulsch->uci_format                            = HLC_subband_cqi_mcs_CBA;
	}
	else {
	  ulsch->Or2                                   = 0;
	  ulsch->Or1                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
	  ulsch->uci_format                            = HLC_subband_cqi_nopmi;
	}
	break;
      case 2:
	if ((rnti >= cba_rnti) && (rnti < p_rnti)){ 
	  ulsch->Or2                                   = 0;
	  ulsch->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
	  ulsch->uci_format                            = HLC_subband_cqi_mcs_CBA;
	}
	else {
	  ulsch->Or2                                   = 0;
	  ulsch->Or1                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
	  ulsch->uci_format                            = HLC_subband_cqi_nopmi;
	}
	break;
      case 3:
	if ((rnti >= cba_rnti) && (rnti < p_rnti)){ 
	  ulsch->Or2                                   = 0;
	  ulsch->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
	  ulsch->uci_format                            = HLC_subband_cqi_mcs_CBA;
	}
	else {
	  ulsch->Or2                                   = 0;
	  ulsch->Or1                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
	  ulsch->uci_format                            = HLC_subband_cqi_nopmi;
	}
	break;
      case 4:
	if ((rnti >= cba_rnti) && (rnti < p_rnti)){ 
	  ulsch->Or2                                   = 0;
	  ulsch->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
	  ulsch->uci_format                            = HLC_subband_cqi_mcs_CBA;
	}
	else {
	  ulsch->Or2                                 = sizeof_wideband_cqi_rank2_2A_5MHz;
	  ulsch->Or1                                 = sizeof_wideband_cqi_rank1_2A_5MHz;
	  ulsch->uci_format                          = wideband_cqi_rank1_2A;
	}
	break;
      case 5:
	if ((rnti >= cba_rnti) && (rnti < p_rnti)){ 
	  ulsch->Or2                                   = 0;
	  ulsch->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
	  ulsch->uci_format                            = HLC_subband_cqi_mcs_CBA;
	}
	else {
	  ulsch->Or2                                 = sizeof_wideband_cqi_rank2_2A_5MHz;
	  ulsch->Or1                                 = sizeof_wideband_cqi_rank1_2A_5MHz;
	  ulsch->uci_format                          = wideband_cqi_rank1_2A;
	}
	break;
      case 6:
	if ((rnti >= cba_rnti) && (rnti < p_rnti)){ 
	  ulsch->Or2                                   = 0;
	  ulsch->Or1                                   = sizeof_HLC_subband_cqi_mcs_CBA_5MHz;
	  ulsch->uci_format                            = HLC_subband_cqi_mcs_CBA;
	}
	else {
	  ulsch->Or2                                 = sizeof_wideband_cqi_rank2_2A_5MHz;
	  ulsch->Or1                                 = sizeof_wideband_cqi_rank1_2A_5MHz;
	  ulsch->uci_format                          = wideband_cqi_rank1_2A;
	}
	break;
      case 7:
	ulsch->Or2                                   = 0;
	ulsch->Or1                                   = sizeof_HLC_subband_cqi_nopmi_5MHz;
	ulsch->uci_format                            = HLC_subband_cqi_nopmi;
	break;
      default:
	LOG_E(PHY,"Incorrect Transmission Mode \n");
	break;
      }
    }
    else {
      ulsch->O_RI = 0;//1;
      ulsch->Or2                                   = 0;
      ulsch->Or1                                   = 0;//sizeof_HLC_subband_cqi_nopmi_5MHz;
      ulsch->uci_format                            = HLC_subband_cqi_nopmi;
    }

    // check this (see comment in generate_ue_ulsch_params_from_dci)
    ulsch->harq_processes[harq_pid]->O_ACK                                 = 1; //(dai+1)&3;


    ulsch->beta_offset_cqi_times8                = beta_cqi[phy_vars_eNB->pusch_config_dedicated[UE_id].betaOffset_CQI_Index];//18;
    ulsch->beta_offset_ri_times8                 = beta_ri[phy_vars_eNB->pusch_config_dedicated[UE_id].betaOffset_RI_Index];//10;
    ulsch->beta_offset_harqack_times8            = beta_ack[phy_vars_eNB->pusch_config_dedicated[UE_id].betaOffset_ACK_Index];//16;

    ulsch->Nsymb_pusch                             = 12-(frame_parms->Ncp<<1)-(use_srs==0?0:1);
    ulsch->srs_active                            = use_srs;
    ulsch->bundling = 1-AckNackFBMode;
    //Mapping of cyclic shift field in DCI format0 to n_DMRS2 (3GPP 36.211, Table 5.5.2.1.1-1)
    if(cshift == 0)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 0;
    else if(cshift == 1)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 6;
    else if(cshift == 2)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 3;
    else if(cshift == 3)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 4;
    else if(cshift == 4)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 2;
    else if(cshift == 5)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 8;
    else if(cshift == 6)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 10;
    else if(cshift == 7)
      ulsch->harq_processes[harq_pid]->n_DMRS2 = 9;


    LOG_D(PHY,"[eNB %d][PUSCH %d] Frame %d, subframe %d : Programming PUSCH with n_DMRS2 %d (cshift %d)\n",
	  phy_vars_eNB->Mod_id,harq_pid,phy_vars_eNB->frame,subframe,ulsch->harq_processes[harq_pid]->n_DMRS2,cshift);




    if (ulsch->harq_processes[harq_pid]->Ndi == 1) {
      if ((rnti >= cba_rnti) && (rnti < p_rnti))
		ulsch->harq_processes[harq_pid]->status = CBA_ACTIVE;
      else 
		ulsch->harq_processes[harq_pid]->status = ACTIVE;
      ulsch->harq_processes[harq_pid]->rvidx = 0;
      ulsch->harq_processes[harq_pid]->mcs         = mcs;
      //      ulsch->harq_processes[harq_pid]->calibration_flag = 0;
      //if (ulsch->harq_processes[harq_pid]->mcs)
      /*
	if (ulsch->harq_processes[harq_pid]->mcs == 29) {
	ulsch->harq_processes[harq_pid]->mcs = 4;
	//	ulsch->harq_processes[harq_pid]->calibration_flag = 1;
	//	printf("Auto-Calibration (eNB): mcs %d, nb_rb %d\n",ulsch->harq_processes[harq_pid]->mcs,ulsch->harq_processes[harq_pid]->nb_rb);
	}
      */
      ulsch->harq_processes[harq_pid]->TBS         = TBStable[get_I_TBS_UL(ulsch->harq_processes[harq_pid]->mcs)][ulsch->harq_processes[harq_pid]->nb_rb-1];
     
      ulsch->harq_processes[harq_pid]->Msc_initial   = 12*ulsch->harq_processes[harq_pid]->nb_rb;
      ulsch->harq_processes[harq_pid]->Nsymb_initial = ulsch->Nsymb_pusch;
      ulsch->harq_processes[harq_pid]->round = 0;
    }
    else {
      if (mcs>28)
	ulsch->harq_processes[harq_pid]->rvidx = mcs - 28;
      else {
	ulsch->harq_processes[harq_pid]->rvidx = 0;
	ulsch->harq_processes[harq_pid]->mcs = mcs;
      }
      //      ulsch->harq_processes[harq_pid]->round++;
    }
    if ((rnti >= cba_rnti) && (rnti < p_rnti)){ 
      ulsch->cba_rnti[0] = rnti;
    }else{
      ulsch->rnti = rnti;      
    }
    //ulsch->n_DMRS2 = cshift;

#ifdef DEBUG_DCI
    msg("ulsch (eNB): NBRB          %d\n",ulsch->harq_processes[harq_pid]->nb_rb);
    msg("ulsch (eNB): first_rb      %d\n",ulsch->harq_processes[harq_pid]->first_rb);
    msg("ulsch (eNB): harq_pid      %d\n",harq_pid);
    msg("ulsch (eNB): Ndi           %d\n",ulsch->harq_processes[harq_pid]->Ndi);
    msg("ulsch (eNB): TBS           %d\n",ulsch->harq_processes[harq_pid]->TBS);
    msg("ulsch (eNB): mcs           %d\n",ulsch->harq_processes[harq_pid]->mcs);
    msg("ulsch (eNB): Or1           %d\n",ulsch->Or1);
    msg("ulsch (eNB): Nsymb_pusch   %d\n",ulsch->Nsymb_pusch);
    msg("ulsch (eNB): cshift        %d\n",ulsch->harq_processes[harq_pid]->n_DMRS2);
3575 3576
#else
    UNUSED_VARIABLE(dai);
3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597
#endif
    return(0);
  }
  else {
    LOG_E(PHY,"generate_eNB_ulsch_params_from_dci, Illegal dci_format %d\n",dci_format);
    return(-1);
  }

}


double sinr_eff_cqi_calc(PHY_VARS_UE *phy_vars_ue, u8 eNB_id){
  u8 transmission_mode = phy_vars_ue->transmission_mode[eNB_id];
  PHY_MEASUREMENTS *meas = &phy_vars_ue->PHY_measurements;
  LTE_DL_FRAME_PARMS *frame_parms =  &phy_vars_ue->lte_frame_parms;
  s32 **dl_channel_est = phy_vars_ue->lte_ue_common_vars.dl_ch_estimates[eNB_id];
  double *s_dB;
  s_dB = phy_vars_ue->sinr_CQI_dB;   
  //  LTE_UE_ULSCH_t *ulsch  = phy_vars_ue->ulsch_ue[eNB_id]; 
  //for the calculation of SINR_eff for CQI calculation
  int count,a_rx,a_tx;
3598 3599 3600 3601 3602
  double abs_channel=0;
  double channelx=0;
  double channely=0;
  double channelx_i=0;
  double channely_i=0;
3603 3604 3605 3606 3607 3608 3609
  u16 q = quantize_subband_pmi(meas,eNB_id);
  u8 qq;
  
  switch(transmission_mode){
  case 1:
    for (count=0;count<frame_parms->N_RB_DL*12;count++)
      {
3610
	for(a_tx=0;a_tx<frame_parms->nb_antennas_tx_eNB;a_tx++)
3611 3612 3613
	  { 
	    for (a_rx=0;a_rx<frame_parms->nb_antennas_rx;a_rx++)
	      {
3614
		s_dB[count] = 10*log10(pow(((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2],2) + pow(((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2],2)) - meas->n0_power_avg_dB;    
3615 3616 3617 3618 3619 3620 3621
	      }
	  }
      }
  break;
 case 2:
   for (count=0;count<frame_parms->N_RB_DL*12;count++)
     {abs_channel=0;
3622
       for(a_tx=0;a_tx<frame_parms->nb_antennas_tx_eNB;a_tx++)
3623 3624 3625
	 { 
	   for (a_rx=0;a_rx<frame_parms->nb_antennas_rx;a_rx++)
	      {
3626
		abs_channel += (pow(((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2],2) + pow(((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2],2)); 
3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639
	      }
	 }
       s_dB[count] = 10*log10(abs_channel/2) - meas->n0_power_avg_dB;
     }
   break;
  case 5:
    for (count=0;count<frame_parms->N_RB_DL*12;count++){
	channelx=0;
	channely=0;
	channelx_i=0;
	channely_i=0;
	qq = (q>>(((count/12)>>2)<<1))&3;
	//printf("pmi_alloc %d: rb %d, pmi %d\n",q,count/12,qq);
3640
    	for(a_tx=0;a_tx<frame_parms->nb_antennas_tx_eNB;a_tx++)
3641 3642 3643 3644 3645 3646
	  { 
	    for (a_rx=0;a_rx<frame_parms->nb_antennas_rx;a_rx++)
	      {
		switch(qq){
		case 0:
		  if (channelx==0 || channely==0){
3647 3648 3649 3650
		    channelx = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		    channely = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
		    channelx_i = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		    channely_i = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];	
3651 3652 3653
		  }
		  else
		    {
3654 3655 3656 3657
		      channelx += ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		      channely += ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
		      channelx_i -= ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		      channely_i -= ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];	
3658 3659 3660 3661
		    }
		  break;
		case 1:
		    if (channelx==0 || channely==0){
3662 3663 3664 3665
		    channelx = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		    channely = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
		    channelx_i = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		    channely_i = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];	
3666 3667 3668
		  }
		  else
		    {
3669 3670 3671 3672
		      channelx -= ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		      channely -= ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
		      channelx_i += ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		      channely_i += ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];	
3673 3674 3675 3676
		    }
		  break;
		case 2:
		    if (channelx==0 || channely==0){
3677 3678 3679 3680
		    channelx = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		    channely = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
		    channelx_i = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		    channely_i = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];	
3681 3682 3683
		  }
		  else
		    {
3684 3685 3686 3687
		      channelx -= ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
		      channely += ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		      channelx_i += ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
		      channely_i -= ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];	
3688 3689 3690 3691
		    }
		  break;
		case 3:
		    if (channelx==0 || channely==0){
3692 3693 3694 3695
		    channelx = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		    channely = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
		    channelx_i = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		    channely_i = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];	
3696 3697 3698
		  }
		  else
		    {
3699 3700 3701 3702
		      channelx += ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
		      channely -= ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		      channelx_i -= ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
		      channely_i += ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];	
3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720
		    }
		  break;
		default:
		  msg("Problem in SINR Calculation for TM5 \n");
		  break;
		}//switch(qq)
	      }//a_rx
	  }//a_tx
	
	s_dB[count] =  10 * log10 ((pow(channelx,2) + pow(channely,2))/2) - 10 * log10 ((pow(channelx_i,2) + pow(channely_i,2))/2) - meas->n0_power_avg_dB;
    }//count
    break;
  case 6:
      for (count=0;count<frame_parms->N_RB_DL*12;count++){
	channelx=0;
	channely=0;
	qq = (q>>(((count/12)>>2)<<1))&3;
	//printf("pmi_alloc %d: rb %d, pmi %d\n",q,count/12,qq);
3721
    	for(a_tx=0;a_tx<frame_parms->nb_antennas_tx_eNB;a_tx++)
3722 3723 3724 3725 3726 3727
	  { 
	    for (a_rx=0;a_rx<frame_parms->nb_antennas_rx;a_rx++)
	      {
		switch(qq){
		case 0:
		  if (channelx==0 || channely==0){
3728 3729
		    channelx = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		    channely = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
3730 3731 3732
		  }
		  else
		    {
3733 3734
		      channelx += ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		      channely += ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
3735 3736 3737 3738
		    }
		  break; 
		case 1:
		    if (channelx==0 || channely==0){
3739 3740
		    channelx = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		    channely = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
3741 3742 3743
		  }
		  else
		    {
3744 3745
		      channelx -= ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		      channely -= ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
3746 3747 3748 3749
		    }
		  break;
		case 2:
		    if (channelx==0 || channely==0){
3750 3751
		    channelx = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		    channely = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
3752 3753 3754
		  }
		  else
		    {
3755 3756
		      channelx -= ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
		      channely += ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
3757 3758 3759 3760
		    }
		  break;
		case 3:
		    if (channelx==0 || channely==0){
3761 3762
		    channelx = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
		    channely = ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
3763 3764 3765
		  }
		  else
		    {
3766 3767
		      channelx += ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+1+(LTE_CE_FILTER_LENGTH)*2];
		      channely -= ((s16 *) dl_channel_est[(a_tx<<1)+a_rx])[2*count+(LTE_CE_FILTER_LENGTH)*2];
3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783
		    }
		  break;
		default:
		  msg("Problem in SINR Calculation for TM6 \n");
		  break;
		}//switch(qq)
	      }//a_rx
	  }//a_tx
	
	s_dB[count] =  10 * log10 ((pow(channelx,2) + pow(channely,2))/2) - meas->n0_power_avg_dB;
    }//count
      break;
      default:
      msg("Problem in SINR Calculation for CQI \n");
      break;
  }
3784
          int ii;
3785
  double sinr_eff = 0;
3786 3787 3788
  double sinr_eff_qpsk=0;
  double sinr_eff_qam16=0;
  double sinr_eff_qam64=0;
3789
  double x = 0;
3790 3791 3792 3793 3794 3795
  double I_qpsk=0;
  double I_qam16=0;
  double I_qam64=0;
  double I_qpsk_avg=0;
  double I_qam16_avg=0;
  double I_qam64_avg=0;
3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845
  double qpsk_max=12.2;
  double qam16_max=19.2;
  double qam64_max=25.2;
  double sinr_min = -20;
  int offset=0;
  
  
  for (offset = 0; offset <= 24; offset++) {
    for(ii=0;ii<12;ii++){
      //x is the sinr_dB in dB
      x = s_dB[(offset*12)+ii];
      if(x<sinr_min){
	I_qpsk +=0;
	I_qam16 +=0;
	I_qam64 +=0;
      }
      else{
	if(x>qpsk_max)
	  I_qpsk += 1;
	else
	  I_qpsk += (q_qpsk[0]*pow(x,7) + q_qpsk[1]*pow(x,6) + q_qpsk[2]*pow(x,5) + q_qpsk[3]*pow(x,4) + q_qpsk[4]*pow(x,3) + q_qpsk[5]*pow(x,2) + q_qpsk[6]*x + q_qpsk[7]);
	
	if(x>qam16_max)
	  I_qam16 += 1;
	else
	  I_qam16 += (q_qam16[0]*pow(x,7) + q_qam16[1]*pow(x,6) + q_qam16[2]*pow(x,5) + q_qam16[3]*pow(x,4) + q_qam16[4]*pow(x,3) + q_qam16[5]*pow(x,2) + q_qam16[6]*x + q_qam16[7]);
	
	if(x>qam64_max)
	  I_qam64 += 1;
	else
	  I_qam64 += (q_qam64[0]*pow(x,7) + q_qam64[1]*pow(x,6) + q_qam64[2]*pow(x,5) + q_qam64[3]*pow(x,4) + q_qam64[4]*pow(x,3) + q_qam64[5]*pow(x,2) + q_qam64[6]*x + q_qam64[7]);
	
      }
    }
  }
  
      // averaging of accumulated MI 
  I_qpsk_avg = I_qpsk/(12*frame_parms->N_RB_DL);  
  I_qam16_avg = I_qam16/(12*frame_parms->N_RB_DL);  
  I_qam64_avg = I_qam64/(12*frame_parms->N_RB_DL);  
  
  // I->SINR_effective Mapping
  
  sinr_eff_qpsk = (p_qpsk[0]*pow(I_qpsk_avg,7) + p_qpsk[1]*pow(I_qpsk_avg,6) + p_qpsk[2]*pow(I_qpsk_avg,5) + p_qpsk[3]*pow(I_qpsk_avg,4) + p_qpsk[4]*pow(I_qpsk_avg,3) + p_qpsk[5]*pow(I_qpsk_avg,2) + p_qpsk[6]*I_qpsk_avg + p_qpsk[7]);
  
  sinr_eff_qam16 = (p_qam16[0]*pow(I_qam16_avg,7) + p_qam16[1]*pow(I_qam16_avg,6) + p_qam16[2]*pow(I_qam16_avg,5) + p_qam16[3]*pow(I_qam16_avg,4) + p_qam16[4]*pow(I_qam16_avg,3) + p_qam16[5]*pow(I_qam16_avg,2) + p_qam16[6]*I_qam16_avg + p_qam16[7]);
  
  sinr_eff_qam64 = (p_qam64[0]*pow(I_qam64_avg,7) + p_qam64[1]*pow(I_qam64_avg,6) + p_qam64[2]*pow(I_qam64_avg,5) + p_qam64[3]*pow(I_qam64_avg,4) + p_qam64[4]*pow(I_qam64_avg,3) + p_qam64[5]*pow(I_qam64_avg,2) + p_qam64[6]*I_qam64_avg + p_qam64[7]);
  sinr_eff = cmax3(sinr_eff_qpsk,sinr_eff_qam16,sinr_eff_qam64);
  
3846
  printf("SINR_Eff = %e\n",sinr_eff);
3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890
  
  return(sinr_eff);
}
//


#ifdef DEBUG_DLSCH_TOOLS
main() {

  int i;
  uint8_t rah;
  uint32_t rballoc;

  generate_RIV_tables();

  for (i=0;i<512;i++) {
    msg("RIV %d: nb_rb %d, alloc %x, alloc_dist %x\n",
	i,
	RIV2nb_rb_LUT25[i],
	localRIV2alloc_LUT25[i],
	distRIV2alloc_LUT25[i]);

  }

  rah = 0;
  rballoc = 0x1fff;
  msg("rballoc 0 %x => %x\n",rballoc,conv_rballoc(rah,rballoc));
  rah = 1;

  rballoc = 0x1678;
  msg("rballoc 1 %x => %x\n",rballoc,conv_rballoc(rah,rballoc));

  rballoc = 0xfffc;
  msg("rballoc 1 %x => %x\n",rballoc,conv_rballoc(rah,rballoc));
  rballoc = 0xfffd;
  msg("rballoc 1 %x => %x\n",rballoc,conv_rballoc(rah,rballoc));
  rballoc = 0xffff;
  msg("rballoc 1 %x => %x\n",rballoc,conv_rballoc(rah,rballoc));
  rballoc = 0xfffe;
  msg("rballoc 1 %x => %x\n",rballoc,conv_rballoc(rah,rballoc));
}

#endif