Commit bf819df6 authored by Sakthivel Velumani's avatar Sakthivel Velumani

changed dci_pdu_rel15 struct to hold bitwidth for each dci field

parent b4d273d6
develop 1 128-ues 256_QAM_demod NCTU_OpinConnect_LDPC NR-PHY-MAC-IF-multi-UE NR_10MHz NR_CSI_reporting NR_DCI_01 NR_DLUL_PF NR_DLUL_PF_rebased NR_DL_sched_fixes NR_DL_scheduler NR_FAPI_beamindex_SSB_RO NR_FR2_RA NR_FR2_RRC_SSB NR_MAC_Multi_Rach_GlobalEdge NR_MAC_SSB_RO_GlobalEdge NR_MAC_SSB_RO_UE_IDCC NR_MAC_SSB_RO_merge NR_MAC_TCI_UCI_GlobalEdge NR_NGAP NR_PDCP_noS1 NR_PUCCH_MultiUE NR_RA_updates NR_RRCConfiguration_FR2 NR_RRC_PDCP NR_RRC_config_simplified NR_RRC_harq NR_RRC_harq_b NR_RRC_harq_hacks NR_RRC_harq_newdcipdu NR_SA_F1AP_dev NR_SA_NGAP_RRC NR_SA_NGAP_RRC_wk42 NR_SA_itti_sim_wk48 NR_SA_itti_sim_wk48_hs NR_SA_itti_sim_wk48_hs1 NR_SCHED_HARQ NR_SCHED_PDCCH_PUCCH_HARQ NR_SCHED_PDCCH_PUCCH_HARQ_rebased NR_SCHED_fixes NR_SRB_Config NR_UE_MAC_scheduler NR_UE_RA_fixes NR_UE_UL_DCI_improvements NR_UE_dlsch_bugfix NR_UE_enable_parallelization NR_UE_stability_fixes NR_UL_FAPI_programming NR_UL_scheduler NR_UL_scheduler_rebased NR_UL_scheduling NR_beam_simulation NR_ipaccess_testing NR_mac_uci_functions_rework NR_msg2_phytest NR_scheduling_CSIRS NR_scheduling_request NR_scheduling_request2 NR_ue_dlsch_dmrs_cdm PUSCH_TA_update RA_CI_test UE_DL_DCI_hotfix bch-fixes-bitmap benetel_5g_prach_fix benetel_driver_update benetel_phase_rotation benetel_phase_rotation_old bugfix-nr-bands bugfix-nr-ldpc-post-processing bugfix-nr-ldpc-size-typo bugfix-nr-pdcp-sn-size bugfix-nr-rate-matching-assertion cce_indexing_fix cce_indexing_fix2 ci-deploy-asterix ci-deploy-docker-compose ci-test ci-ul-iperf-from-trf-container cleanup_softmodem_main constant_power develop-SnT develop-oriecpriupdates develop-sib1 develop-sib1-local develop-sib1-lts develop_stable dfts_alternatives dlsch-all-dlslots dlsch_encode_mthread dlsch_parallel dongzhanyi-zte-develop dongzhanyi-zte-develop2 feature/make-s1-mme-port-configurable feature/make-s1-mme-port-configurable-with-astyle-fixes fembms-enb-ue finalize-oaicn-integration firas fix-ci-tun fix-itti-segv fix-softmodem-restart fix_NR_DLUL_PF fix_do_ra_data fix_pdsch_low_prb fix_rfsim_mimo fix_rrc_x2_ticking fixes-CE-RLC-PDU-size fixes-mac-sched-nfapi fixes-mac-sched-tun fixes-tun flexran-apps flexran-repair-mme-mgmt fujitsu_lte_contribution fujitsu_lte_contribution-128 gnb-only-test harq-hotfix hotfix-minor-remove-nr-rlc-cppcheck-error hotfix-nr-rlc-tick hotfix-ocp-executable improve_nr_modulation improve_ue_stability integration_2020_wk40 integration_2020_wk41 integration_2020_wk42_2 integration_2020_wk45 integration_2020_wk45_2 integration_2020_wk46 integration_2020_wk46_2 integration_2020_wk47 integration_2020_wk48 integration_2020_wk48_2 integration_2020_wk49 integration_2020_wk50 integration_2020_wk50_1 integration_2020_wk51 integration_2020_wk51_2 integration_2021_wk02 integration_2021_wk02_wMR988 inter-RRU-final itti-enhancement ldpc-decoder-codegen ldpc-decoder-codegen2 ldpc_short_codeword_fixes load_gnb lte_uplink_improvement mac-fixes-wk45_2 minor-fix-doc-basic-sim mosaic5g-oai-ran mosaic5g-oai-sim nasmesh_kernel_5.8 nfapi_nr_develop ngap-dlul ngap-support ngap-w48-merge2 ngap-wf ngap-wf-1120 ngap-wf-1120-srb ngap-wf-1120-srb-gtp ngap-wf-1120-srb-gtp-hs ngap-wf-1120-srb-gtp-hs1 ngap-wf-1120-srb-gtp-hs2 ngap-wf-1120-srb-gtp-yhz ngap-wf-1203-yunsdr ngap-wf-liuyu ngap_lfq_1120 ngap_merge noCore nr-mac-pdu-wireshark nr-mac-remove-ue-list nr-rlc-am-bugfix-w44 nr-rlc-bugfix-w44 nrUE nrUE-hs nrUE-upper-layer nr_bsr nr_dl_dmrs_type2 nr_dl_pf nr_dl_pf2 nr_dl_ul_ptrs nr_fdd_if_fix nr_prach_fr2 nr_ue_msg3 nr_ue_tti_cleanup nr_ul_pf nr_ul_scfdma nrue_msg2_reception nsa-ue nsa_remove_band_hardcodings oai-sim oairu oc-docker-october-improvements openxg/develop ptrs_rrc_config pusch-mthread-scaling-fix pusch-retrans-fix-ue ra-dl-ul remove_nos1_hack_pdcp remove_x2_gnb_hardcoding repair-TA revert_memcpy rh-ci-add-ue-parallelization rh_ci_fix_autoterminate rh_ci_fr1_update rh_ci_oc rh_ci_py rh_ci_rfsim_ra rh_fr1_newjenkins rh_fr1_update rh_gnb_compile_fix rh_wk50_debug rlc-v2-bugfix-status-reporting rlc-v2-tick rrc-enb-phy-testmode s1-subnormal_rewrite s1_subnormal s1_subnormal-robert s1ap-bugfix-rab_setup sa-demo sa-merge-rrc-srb sa-msg4 sa-msg4-rrc sa-msg4-rrc-yihz sa-msg4-rrc-yihz-hs sa_rrc_yihz small-bugfixes-w40 small-config-change smallcleanup testing_2symb_pdcch testing_with_external_txdata ue-csi ue_beam_selection ul-freq-iq-samps-to-file ul_dl_dci_same_slot ul_harq ulsch_decode_mthread ulsim_changes wireshark-log-scheduling-requests x2-endc-processing xiangwab xiangwan yihongzheng_srb zzs 2021.w02 2020.w51_2 2020.w51 2020.w50 2020.w49 2020.w48_2 2020.w48 2020.w47 2020.w46_2 2020.w46 2020.w45_2 2020.w45 2020.w44 2020.w42_2 2020.w42 2020.w41 2020.w39 2020.w38 2020.w37 2020.w36 2020.w34 2020.w33 2020.w31 2020.w30 2020.w29 2020.w28 benetel_phase_rotation
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...@@ -336,37 +336,37 @@ int configure_fapi_dl_pdu(int Mod_idP, ...@@ -336,37 +336,37 @@ int configure_fapi_dl_pdu(int Mod_idP,
scc->dmrs_TypeA_Position, scc->dmrs_TypeA_Position,
pdsch_pdu_rel15->NrOfSymbols); pdsch_pdu_rel15->NrOfSymbols);
dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; dci_pdu_rel15_t *dci_pdu_rel15 = calloc(MAX_DCI_CORESET,sizeof(dci_pdu_rel15));
dci_pdu_rel15[0].frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize, dci_pdu_rel15[0].frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize,
pdsch_pdu_rel15->rbStart, pdsch_pdu_rel15->rbStart,
NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275)); NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275));
dci_pdu_rel15[0].time_domain_assignment = time_domain_assignment; // row index used here instead of SLIV; dci_pdu_rel15[0].time_domain_assignment.val = time_domain_assignment; // row index used here instead of SLIV;
dci_pdu_rel15[0].vrb_to_prb_mapping = 1; dci_pdu_rel15[0].vrb_to_prb_mapping.val = 1;
dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0]; dci_pdu_rel15[0].mcs[0].val = pdsch_pdu_rel15->mcsIndex[0];
dci_pdu_rel15[0].tb_scaling = 1; dci_pdu_rel15[0].tb_scaling.val = 1;
dci_pdu_rel15[0].ra_preamble_index = 25; dci_pdu_rel15[0].ra_preamble_index.val = 25;
dci_pdu_rel15[0].format_indicator = 1; dci_pdu_rel15[0].format_indicator.val = 1;
dci_pdu_rel15[0].ndi = 1; dci_pdu_rel15[0].ndi[0].val = 1;
dci_pdu_rel15[0].rv = 0; dci_pdu_rel15[0].rv[0].val = 0;
dci_pdu_rel15[0].harq_pid = 0; dci_pdu_rel15[0].harq_pid.val = 0;
dci_pdu_rel15[0].dai = 2; dci_pdu_rel15[0].dai.val = 2;
dci_pdu_rel15[0].tpc = 2; dci_pdu_rel15[0].tpc.val = 2;
dci_pdu_rel15[0].pucch_resource_indicator = 7; dci_pdu_rel15[0].pucch_resource_indicator.val = 7;
dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator = 7; dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator.val = 7;
LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n",
dci_pdu_rel15[0].frequency_domain_assignment, dci_pdu_rel15[0].frequency_domain_assignment.val,
pdsch_pdu_rel15->rbStart, pdsch_pdu_rel15->rbStart,
pdsch_pdu_rel15->rbSize, pdsch_pdu_rel15->rbSize,
NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275), NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275),
dci_pdu_rel15[0].time_domain_assignment, dci_pdu_rel15[0].time_domain_assignment.val,
dci_pdu_rel15[0].vrb_to_prb_mapping, dci_pdu_rel15[0].vrb_to_prb_mapping.val,
dci_pdu_rel15[0].mcs, dci_pdu_rel15[0].mcs[0].val,
dci_pdu_rel15[0].tb_scaling, dci_pdu_rel15[0].tb_scaling.val,
dci_pdu_rel15[0].ndi, dci_pdu_rel15[0].ndi[0].val,
dci_pdu_rel15[0].rv); dci_pdu_rel15[0].rv[0].val);
nr_configure_pdcch(pdcch_pdu_rel15, nr_configure_pdcch(pdcch_pdu_rel15,
1, // ue-specific 1, // ue-specific
...@@ -386,8 +386,8 @@ int configure_fapi_dl_pdu(int Mod_idP, ...@@ -386,8 +386,8 @@ int configure_fapi_dl_pdu(int Mod_idP,
dci_formats[0] = NR_DL_DCI_FORMAT_1_0; dci_formats[0] = NR_DL_DCI_FORMAT_1_0;
rnti_types[0] = NR_RNTI_C; rnti_types[0] = NR_RNTI_C;
pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[0],dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
fill_dci_pdu_rel15(secondaryCellGroup,pdsch_pdu_rel15,pdcch_pdu_rel15,NULL,&dci_pdu_rel15[0],dci_formats,rnti_types); fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types);
LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \ LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \
coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n",
...@@ -419,29 +419,29 @@ int configure_fapi_dl_pdu(int Mod_idP, ...@@ -419,29 +419,29 @@ int configure_fapi_dl_pdu(int Mod_idP,
void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types) { void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types) {
dci_pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, dci_pdu_rel15->frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size,
pusch_pdu->rb_start, pusch_pdu->rb_start,
NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275)); NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275));
dci_pdu_rel15->time_domain_assignment = 2; // row index used here instead of SLIV; dci_pdu_rel15->time_domain_assignment.val = 2; // row index used here instead of SLIV;
dci_pdu_rel15->frequency_hopping_flag = 0; dci_pdu_rel15->frequency_hopping_flag.val = 0;
dci_pdu_rel15->mcs = 9; dci_pdu_rel15->mcs[0].val = 9;
dci_pdu_rel15->format_indicator = 0; dci_pdu_rel15->format_indicator.val = 0;
dci_pdu_rel15->ndi = 1; dci_pdu_rel15->ndi[0].val = 1;
dci_pdu_rel15->rv = 0; dci_pdu_rel15->rv[0].val = 0;
dci_pdu_rel15->harq_pid = 0; dci_pdu_rel15->harq_pid.val = 0;
dci_pdu_rel15->tpc = 2; dci_pdu_rel15->tpc.val = 2;
LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n", LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n",
pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci], pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci],
dci_pdu_rel15->frequency_domain_assignment, dci_pdu_rel15->frequency_domain_assignment.val,
dci_pdu_rel15->time_domain_assignment, dci_pdu_rel15->time_domain_assignment.val,
dci_pdu_rel15->frequency_hopping_flag, dci_pdu_rel15->frequency_hopping_flag.val,
dci_pdu_rel15->mcs, dci_pdu_rel15->mcs[0].val,
dci_pdu_rel15->tpc, dci_pdu_rel15->tpc.val,
dci_pdu_rel15->ndi, dci_pdu_rel15->ndi[0].val,
dci_pdu_rel15->rv); dci_pdu_rel15->rv[0].val);
dci_formats[pdcch_pdu_rel15->numDlDci] = NR_UL_DCI_FORMAT_0_0; dci_formats[pdcch_pdu_rel15->numDlDci] = NR_UL_DCI_FORMAT_0_0;
rnti_types[pdcch_pdu_rel15->numDlDci] = NR_RNTI_C; rnti_types[pdcch_pdu_rel15->numDlDci] = NR_RNTI_C;
...@@ -832,8 +832,8 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, ...@@ -832,8 +832,8 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types);
pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[0],dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
fill_dci_pdu_rel15(secondaryCellGroup,NULL,pdcch_pdu_rel15,pusch_pdu,&dci_pdu_rel15[0],dci_formats,rnti_types); fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types);
} }
...@@ -130,10 +130,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, ...@@ -130,10 +130,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
NR_ServingCellConfigCommon_t *scc, NR_ServingCellConfigCommon_t *scc,
NR_BWP_Downlink_t *bwp); NR_BWP_Downlink_t *bwp);
void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15,
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
nfapi_nr_pusch_pdu_t *pusch_pdu,
dci_pdu_rel15_t *dci_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15,
int *dci_formats, int *dci_formats,
int *rnti_types); int *rnti_types);
...@@ -166,9 +163,11 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP); ...@@ -166,9 +163,11 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP);
int get_num_dmrs(uint16_t dmrs_mask ); int get_num_dmrs(uint16_t dmrs_mask );
uint16_t nr_dci_size(nr_dci_format_t format, uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup,
nr_rnti_type_t rnti_type, dci_pdu_rel15_t *dci_pdu,
uint16_t N_RB); nr_dci_format_t format,
nr_rnti_type_t rnti_type,
uint16_t N_RB);
int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
int bwp_id, int bwp_id,
......
...@@ -190,7 +190,7 @@ typedef struct gNB_MAC_INST_s { ...@@ -190,7 +190,7 @@ typedef struct gNB_MAC_INST_s {
int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE]; int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE];
} gNB_MAC_INST; } gNB_MAC_INST;
typedef struct { /*typedef struct {
uint8_t format_indicator; //1 bit uint8_t format_indicator; //1 bit
...@@ -250,8 +250,74 @@ uint8_t antenna_ports; ...@@ -250,8 +250,74 @@ uint8_t antenna_ports;
uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits
uint16_t padding; uint16_t padding;
} dci_pdu_rel15_t; } dci_pdu_rel15_t;*/
typedef struct {
uint16_t val;
uint8_t nbits;
} dci_field_t;
typedef struct {
dci_field_t format_indicator; //1 bit
dci_field_t frequency_domain_assignment; //up to 16 bits
dci_field_t time_domain_assignment; // 4 bits
dci_field_t frequency_hopping_flag; //1 bit
dci_field_t ra_preamble_index; //6 bits
dci_field_t ss_pbch_index; //6 bits
dci_field_t prach_mask_index; //4 bits
dci_field_t vrb_to_prb_mapping; //0 or 1 bit
dci_field_t mcs[2]; //5 bits
dci_field_t ndi[2]; //1 bit
dci_field_t rv[2]; //2 bits
dci_field_t harq_pid; //4 bits
dci_field_t dai; //0, 2 or 4 bits
dci_field_t dai1; //1 or 2 bits
dci_field_t dai2; //0 or 2 bits
dci_field_t tpc; //2 bits
dci_field_t pucch_resource_indicator; //3 bits
dci_field_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits
dci_field_t short_messages_indicator; //2 bits
dci_field_t short_messages; //8 bits
dci_field_t tb_scaling; //2 bits
dci_field_t carrier_indicator; //0 or 3 bits
dci_field_t bwp_indicator; //0, 1 or 2 bits
dci_field_t prb_bundling_size_indicator; //0 or 1 bits
dci_field_t rate_matching_indicator; //0, 1 or 2 bits
dci_field_t zp_csi_rs_trigger; //0, 1 or 2 bits
dci_field_t transmission_configuration_indication; //0 or 3 bits
dci_field_t srs_request; //2 bits
dci_field_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits
dci_field_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit
dci_field_t dmrs_sequence_initialization; //0 or 1 bit
dci_field_t srs_resource_indicator;
dci_field_t precoding_information;
dci_field_t csi_request;
dci_field_t ptrs_dmrs_association;
dci_field_t beta_offset_indicator; //0 or 2 bits
dci_field_t slot_format_indicator_count;
dci_field_t *slot_format_indicators;
dci_field_t pre_emption_indication_count;
dci_field_t *pre_emption_indications; //14 bit
dci_field_t block_number_count;
dci_field_t *block_numbers;
dci_field_t ul_sul_indicator; //0 or 1 bit
dci_field_t antenna_ports;
dci_field_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits
dci_field_t padding;
} dci_pdu_rel15_t;
#endif /*__LAYER2_NR_MAC_GNB_H__ */ #endif /*__LAYER2_NR_MAC_GNB_H__ */
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