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wangwenhui
OpenXG-RAN
Commits
fe724b55
Commit
fe724b55
authored
4 years ago
by
cig
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Cleanup RA procedure
parent
68391d72
develop
1
128-ues
256_QAM_demod
NR-PHY-MAC-IF-multi-UE
NR_10MHz
NR_CSI_reporting
NR_DLUL_PF
NR_DLUL_PF_rebased
NR_DL_sched_fixes
NR_DL_scheduler
NR_FAPI_beamindex_SSB_RO
NR_FR2_RA
NR_FR2_RRC_SSB
NR_MAC_Multi_Rach_GlobalEdge
NR_MAC_SSB_RO_GlobalEdge
NR_MAC_SSB_RO_UE_IDCC
NR_MAC_SSB_RO_merge
NR_MAC_TCI_UCI_GlobalEdge
NR_NGAP
NR_PUCCH_MultiUE
NR_RA_updates
NR_RRCConfiguration_FR2
NR_SA_F1AP_dev
NR_SA_NGAP_RRC
NR_SA_NGAP_RRC_wk42
NR_SA_itti_sim_wk48
NR_SA_itti_sim_wk48_hs
NR_SA_itti_sim_wk48_hs1
NR_SCHED_HARQ
NR_SCHED_PDCCH_PUCCH_HARQ
NR_SCHED_PDCCH_PUCCH_HARQ_rebased
NR_SCHED_fixes
NR_SRB_Config
NR_UE_MAC_scheduler
NR_UE_RA_fixes
NR_UE_UL_DCI_improvements
NR_UE_dlsch_bugfix
NR_UE_enable_parallelization
NR_UE_stability_fixes
NR_UL_scheduler
NR_UL_scheduler_rebased
NR_beam_simulation
NR_mac_uci_functions_rework
NR_scheduling_CSIRS
NR_scheduling_request
NR_scheduling_request2
PUSCH_TA_update
RA_CI_test
UE_DL_DCI_hotfix
bch-fixes-bitmap
benetel_5g_prach_fix
benetel_driver_update
benetel_phase_rotation
benetel_phase_rotation_old
bugfix-nr-bands
bugfix-nr-ldpc-post-processing
bugfix-nr-ldpc-size-typo
bugfix-nr-pdcp-sn-size
bugfix-nr-rate-matching-assertion
cce_indexing_fix
cce_indexing_fix2
ci-deploy-asterix
ci-deploy-docker-compose
ci-test
ci-ul-iperf-from-trf-container
cleanup_softmodem_main
constant_power
develop-SnT
develop-oriecpriupdates
develop-sib1
develop-sib1-local
develop-sib1-lts
develop_stable
dfts_alternatives
dlsch_encode_mthread
dlsch_parallel
dongzhanyi-zte-develop2
feature/make-s1-mme-port-configurable
feature/make-s1-mme-port-configurable-with-astyle-fixes
finalize-oaicn-integration
fix-ci-tun
fix-itti-segv
fix_NR_DLUL_PF
fix_do_ra_data
fix_pdsch_low_prb
fix_rrc_x2_ticking
fixes-CE-RLC-PDU-size
fixes-mac-sched-nfapi
fixes-mac-sched-tun
fixes-tun
flexran-apps
flexran-repair-mme-mgmt
fujitsu_lte_contribution
fujitsu_lte_contribution-128
gnb-only-test
harq-hotfix
hotfix-minor-remove-nr-rlc-cppcheck-error
hotfix-nr-rlc-tick
integration_2020_wk40
integration_2020_wk41
integration_2020_wk42_2
integration_2020_wk45
integration_2020_wk45_2
integration_2020_wk46
integration_2020_wk46_2
integration_2020_wk47
integration_2020_wk48
integration_2020_wk48_2
integration_2020_wk49
integration_2020_wk50
integration_2020_wk50_1
integration_2020_wk51
integration_2020_wk51_2
integration_2021_wk02
integration_2021_wk02_wMR988
inter-RRU-final
itti-enhancement
ldpc-decoder-codegen
ldpc-decoder-codegen2
ldpc_short_codeword_fixes
load_gnb
lte_uplink_improvement
mac-fixes-wk45_2
minor-fix-doc-basic-sim
mosaic5g-oai-ran
mosaic5g-oai-sim
nasmesh_kernel_5.8
nfapi_nr_develop
ngap-dlul
ngap-support
ngap-w48-merge2
ngap-wf
ngap-wf-1120
ngap-wf-1120-srb
ngap-wf-1120-srb-gtp
ngap-wf-1120-srb-gtp-hs
ngap-wf-1120-srb-gtp-hs1
ngap-wf-1120-srb-gtp-hs2
ngap-wf-1120-srb-gtp-yhz
ngap-wf-1203-yunsdr
ngap-wf-liuyu
ngap_lfq_1120
ngap_merge
noCore
nr-mac-pdu-wireshark
nr-mac-remove-ue-list
nr-rlc-am-bugfix-w44
nr-rlc-bugfix-w44
nrUE
nrUE-hs
nrUE-upper-layer
nr_bsr
nr_dl_dmrs_type2
nr_dl_pf
nr_dl_pf2
nr_dl_ul_ptrs
nr_fdd_if_fix
nr_prach_fr2
nr_ue_msg3
nr_ue_tti_cleanup
nr_ul_pf
nr_ul_scfdma
nrue_msg2_reception
nsa-ue
nsa_remove_band_hardcodings
oai-sim
oairu
oc-docker-october-improvements
openxg/develop
ptrs_rrc_config
pusch-mthread-scaling-fix
pusch-retrans-fix-ue
ra-dl-ul
remove_nos1_hack_pdcp
remove_x2_gnb_hardcoding
repair-TA
revert_memcpy
rh-ci-add-ue-parallelization
rh_ci_fix_autoterminate
rh_ci_fr1_update
rh_ci_oc
rh_ci_py
rh_ci_rfsim_ra
rh_fr1_newjenkins
rh_fr1_update
rh_gnb_compile_fix
rh_wk50_debug
rlc-v2-bugfix-status-reporting
rlc-v2-tick
rrc-enb-phy-testmode
s1-subnormal_rewrite
s1_subnormal
s1_subnormal-robert
s1ap-bugfix-rab_setup
sa-demo
sa-merge-rrc-srb
sa-msg4
sa-msg4-rrc
sa-msg4-rrc-yihz
sa-msg4-rrc-yihz-hs
sa_rrc_yihz
small-bugfixes-w40
small-config-change
testing_with_external_txdata
ue_beam_selection
ul-freq-iq-samps-to-file
ul_dl_dci_same_slot
ulsch_decode_mthread
ulsim_changes
wireshark-log-scheduling-requests
x2-endc-processing
xiangwab
xiangwan
yihongzheng_srb
zzs
2021.w02
2020.w51_2
2020.w51
2020.w50
2020.w49
2020.w48_2
2020.w48
2020.w47
2020.w46_2
2020.w46
2020.w45_2
2020.w45
2020.w44
2020.w42_2
2020.w42
2020.w41
2020.w39
2020.w38
2020.w37
2020.w36
2020.w34
2020.w33
benetel_phase_rotation
No related merge requests found
Changes
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3 changed files
with
21 additions
and
30 deletions
+21
-30
openair1/PHY/NR_TRANSPORT/nr_prach.c
openair1/PHY/NR_TRANSPORT/nr_prach.c
+0
-1
openair1/PHY/NR_UE_TRANSPORT/nr_prach.c
openair1/PHY/NR_UE_TRANSPORT/nr_prach.c
+13
-20
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
+8
-9
No files found.
openair1/PHY/NR_TRANSPORT/nr_prach.c
View file @
fe724b55
...
...
@@ -37,7 +37,6 @@
extern
uint16_t
prach_root_sequence_map_0_3
[
838
];
extern
uint16_t
prach_root_sequence_map_abc
[
138
];
extern
uint16_t
nr_du
[
838
];
extern
int16_t
nr_ru
[
2
*
839
];
extern
const
char
*
prachfmt
[
9
];
void
init_prach_list
(
PHY_VARS_gNB
*
gNB
)
{
...
...
This diff is collapsed.
Click to expand it.
openair1/PHY/NR_UE_TRANSPORT/nr_prach.c
View file @
fe724b55
...
...
@@ -44,18 +44,8 @@
//#define NR_PRACH_DEBUG 1
extern
uint16_t
NCS_unrestricted_delta_f_RA_125
[
16
];
extern
uint16_t
NCS_restricted_TypeA_delta_f_RA_125
[
15
];
extern
uint16_t
NCS_restricted_TypeB_delta_f_RA_125
[
13
];
extern
uint16_t
NCS_unrestricted_delta_f_RA_5
[
16
];
extern
uint16_t
NCS_restricted_TypeA_delta_f_RA_5
[
16
];
extern
uint16_t
NCS_restricted_TypeB_delta_f_RA_5
[
14
];
extern
uint16_t
NCS_unrestricted_delta_f_RA_15
[
16
];
extern
uint16_t
prach_root_sequence_map_0_3
[
838
];
extern
uint16_t
prach_root_sequence_map_abc
[
138
];
extern
int64_t
table_6_3_3_2_2_prachConfig_Index
[
256
][
9
];
extern
int64_t
table_6_3_3_2_3_prachConfig_Index
[
256
][
9
];
extern
int64_t
table_6_3_3_2_4_prachConfig_Index
[
256
][
10
];
extern
uint16_t
nr_du
[
838
];
extern
int16_t
nr_ru
[
2
*
839
];
extern
const
char
*
prachfmt
[
9
];
...
...
@@ -118,7 +108,7 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){
else
samp_count
=
(
slot
%
(
fp
->
slots_per_subframe
/
2
))
?
fp
->
samples_per_slotN0
:
fp
->
samples_per_slot0
;
#if
defined (OAI_USRP)
#if
def OAI_USRP
prach_start
=
(
ue
->
rx_offset
+
slot
*
samp_count
-
ue
->
hw_timing_advance
-
ue
->
N_TA_offset
);
#else //normal case (simulation)
prach_start
=
slot
*
samp_count
-
ue
->
N_TA_offset
;
...
...
@@ -208,14 +198,17 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){
// now generate PRACH signal
#ifdef NR_PRACH_DEBUG
if
(
NCS
>
0
)
LOG_I
(
PHY
,
"PRACH [UE %d] generate PRACH for RootSeqIndex %d, Preamble Index %d, PRACH Format %s, NCS %d (N_ZC %d): Preamble_offset %d, Preamble_shift %d
\n
"
,
Mod_id
,
rootSequenceIndex
,
preamble_index
,
prach_sequence_length
==
0
?
prachfmt03
[
prach_fmt_id
]
:
prachfmt
[
prach_fmt_id
],
LOG_I
(
PHY
,
"PRACH [UE %d] generate PRACH in slot %d for RootSeqIndex %d, Preamble Index %d, PRACH Format %s, NCS %d (N_ZC %d): Preamble_offset %d, Preamble_shift %d msg1 frequency start %d
\n
"
,
Mod_id
,
slot
,
rootSequenceIndex
,
preamble_index
,
prach_sequence_length
==
0
?
prachfmt03
[
prach_fmt_id
]
:
prachfmt
[
prach_fmt_id
],
NCS
,
N_ZC
,
preamble_offset
,
preamble_shift
);
preamble_shift
,
n_ra_prb
);
#endif
// nsymb = (frame_parms->Ncp==0) ? 14:12;
...
...
@@ -383,8 +376,6 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){
}
else
{
//LOG_D(PHY, "PRACH [UE %d] in slot %d, format %d, msg1 frequency start %d startSymbol %d \n", Mod_id, slot, prachfmt[prach_fmt_id], n_ra_prb, prachStartSymbol);
switch
(
prach_fmt_id
)
{
case
0
:
//A1
Ncp
=
288
/
(
1
<<
mu
);
...
...
@@ -419,7 +410,9 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){
}
}
LOG_D
(
PHY
,
"PRACH [UE %d] Ncp %d, dftlen %d
\n
"
,
Mod_id
,
Ncp
,
dftlen
);
#ifdef NR_PRACH_DEBUG
LOG_D
(
PHY
,
"PRACH [UE %d] Ncp %d, dftlen %d
\n
"
,
Mod_id
,
Ncp
,
dftlen
);
#endif
if
(
fp
->
N_RB_UL
<=
100
)
AssertFatal
(
1
==
0
,
"N_RB_UL %d not supported for NR PRACH yet
\n
"
,
fp
->
N_RB_UL
);
...
...
@@ -844,7 +837,7 @@ int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){
//}
//printf(" \n");
#if
defined(PRACH_WRITE_OUTPUT_DEBUG)
#if
def PRACH_WRITE_OUTPUT_DEBUG
LOG_M
(
"prach_tx0.m"
,
"prachtx0"
,
prach
+
(
Ncp
<<
1
),
prach_len
-
Ncp
,
1
,
1
);
LOG_M
(
"Prach_txsig.m"
,
"txs"
,(
int16_t
*
)(
&
ue
->
common_vars
.
txdata
[
0
][
prach_start
]),
2
*
(
prach_start
+
prach_len
),
1
,
1
)
#endif
...
...
This diff is collapsed.
Click to expand it.
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
View file @
fe724b55
...
...
@@ -42,8 +42,7 @@
#include "SIMULATION/TOOLS/sim.h" // for taus
extern
RAN_CONTEXT_t
RC
;
const
uint8_t
nr_slots_per_frame_mac
[
5
]
=
{
10
,
20
,
40
,
80
,
160
};
extern
const
uint8_t
nr_slots_per_frame
[
5
];
uint8_t
DELTA
[
4
]
=
{
2
,
3
,
4
,
6
};
...
...
@@ -185,7 +184,7 @@ void nr_schedule_msg2(uint16_t rach_frame, uint16_t rach_slot,
tdd_period_slot
++
;
// computing start of next period
uint8_t
start_next_period
=
(
rach_slot
-
(
rach_slot
%
tdd_period_slot
)
+
tdd_period_slot
)
%
nr_slots_per_frame
_mac
[
mu
];
uint8_t
start_next_period
=
(
rach_slot
-
(
rach_slot
%
tdd_period_slot
)
+
tdd_period_slot
)
%
nr_slots_per_frame
[
mu
];
*
msg2_slot
=
start_next_period
+
last_dl_slot_period
;
// initializing scheduling of slot to next mixed (or last dl) slot
*
msg2_frame
=
(
*
msg2_slot
>
(
rach_slot
))
?
rach_frame
:
(
rach_frame
+
1
);
...
...
@@ -217,16 +216,16 @@ void nr_schedule_msg2(uint16_t rach_frame, uint16_t rach_slot,
default:
AssertFatal
(
1
==
0
,
"Invalid response window value %d
\n
"
,
response_window
);
}
AssertFatal
(
slot_window
<=
nr_slots_per_frame
_mac
[
mu
],
"Msg2 response window needs to be lower or equal to 10ms"
);
AssertFatal
(
slot_window
<=
nr_slots_per_frame
[
mu
],
"Msg2 response window needs to be lower or equal to 10ms"
);
// slot and frame limit to transmit msg2 according to response window
uint8_t
slot_limit
=
(
rach_slot
+
slot_window
)
%
nr_slots_per_frame
_mac
[
mu
];
uint8_t
slot_limit
=
(
rach_slot
+
slot_window
)
%
nr_slots_per_frame
[
mu
];
//uint8_t frame_limit = (slot_limit>(rach_slot))? rach_frame : (rach_frame +1);
// go to previous slot if the current scheduled slot is beyond the response window
// and if the slot is not among the PDCCH monitored ones (38.213 10.1)
while
((
*
msg2_slot
>
slot_limit
)
||
((
*
msg2_frame
*
nr_slots_per_frame
_mac
[
mu
]
+*
msg2_slot
-
monitoring_offset
)
%
monitoring_slot_period
!=
0
))
{
while
((
*
msg2_slot
>
slot_limit
)
||
((
*
msg2_frame
*
nr_slots_per_frame
[
mu
]
+*
msg2_slot
-
monitoring_offset
)
%
monitoring_slot_period
!=
0
))
{
if
((
*
msg2_slot
%
tdd_period_slot
)
>
0
)
(
*
msg2_slot
)
--
;
else
...
...
@@ -397,11 +396,11 @@ void nr_get_Msg3alloc(NR_ServingCellConfigCommon_t *scc,
uint8_t
k2
=
*
ubwp
->
bwp_Common
->
pusch_ConfigCommon
->
choice
.
setup
->
pusch_TimeDomainAllocationList
->
list
.
array
[
ra
->
Msg3_tda_id
]
->
k2
;
temp_slot
=
current_slot
+
k2
+
DELTA
[
mu
];
// msg3 slot according to 8.3 in 38.213
ra
->
Msg3_slot
=
temp_slot
%
nr_slots_per_frame
_mac
[
mu
];
if
(
nr_slots_per_frame
_mac
[
mu
]
>
temp_slot
)
ra
->
Msg3_slot
=
temp_slot
%
nr_slots_per_frame
[
mu
];
if
(
nr_slots_per_frame
[
mu
]
>
temp_slot
)
ra
->
Msg3_frame
=
current_frame
;
else
ra
->
Msg3_frame
=
current_frame
+
(
temp_slot
/
nr_slots_per_frame
_mac
[
mu
]);
ra
->
Msg3_frame
=
current_frame
+
(
temp_slot
/
nr_slots_per_frame
[
mu
]);
ra
->
msg3_nb_rb
=
18
;
ra
->
msg3_first_rb
=
0
;
...
...
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Click to expand it.
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