• Nathan Bronson's avatar
    switch to RDTSC spin loop timing · c9d712c3
    Nathan Bronson authored
    Summary:
    The PAUSE instruction's latency varies widely across x64
    architectures, resulting in too much spinning on Skylake in some
    scenarios.  This diff switches to using cycle counts to limit spinning
    on x64, so that the minimum and maximum spin durations are independent
    of asm_volatile_pause's latency.
    
    Reviewed By: yfeldblum
    
    Differential Revision: D17961663
    
    fbshipit-source-id: 6170bfa48d007ca21b73b1a5c7e68da0043cda2c
    c9d712c3
TurnSequencer.h 11.5 KB