Commit 39757230 authored by Robert Schmidt's avatar Robert Schmidt

Update config files

parent 03ad5fb7
......@@ -23,7 +23,6 @@ gNBs =
do_CSIRS = 1;
do_SRS = 0 ;
sib1_tda = 15;
force_UL256qam_off = 1;
pdcch_ConfigSIB1 = (
{
......@@ -59,7 +58,7 @@ gNBs =
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 1;
#pdcch-ConfigCommon
initialDLBWPcontrolResourceSetZero = 11; #thamizh change
initialDLBWPcontrolResourceSetZero = 11;
initialDLBWPsearchSpaceZero = 0;
#uplinkConfigCommon
......@@ -80,34 +79,34 @@ gNBs =
initialULBWPsubcarrierSpacing = 1;
#rach-ConfigCommon
#rach-ConfigGeneric
prach_ConfigurationIndex = 159; #thamizh change
prach_ConfigurationIndex = 159;
#prach_msg1_FDM
#0 = one, 1=two, 2=four, 3=eight
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 0;
zeroCorrelationZoneConfig = 0; #thamizh change
preambleReceivedTargetPower = -100; #-84 #Luis -70; #thamizh change
zeroCorrelationZoneConfig = 0;
preambleReceivedTargetPower = -100;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 7; #thamizh change
preambleTransMax = 7;
#powerRampingStep
# 0=dB0,1=dB2,2=dB4,3=dB6
powerRampingStep = 2;
#ra_ReponseWindow
#1,2,4,8,10,20,40,80
ra_ResponseWindow = 5; #thamizh change
ra_ResponseWindow = 5;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3; #thamizh change
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3;
#oneHalf (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15; #thamizh change
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
#(0..7) 8,16,24,32,40,48,56,64
ra_ContentionResolutionTimer = 7; #4 #thamizh change
rsrp_ThresholdSSB = 19; #31; #thamizh change
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
#1 = 839, 2 = 139
prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1; #thamizh change
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
msg1_SubcarrierSpacing = 1,
......@@ -116,19 +115,19 @@ gNBs =
restrictedSetConfig = 0,
# this is the offset between the last PRACH preamble power and the Msg3 PUSCH, 2 times the field value in dB
msg3_DeltaPreamble = 2; #thamizh change
p0_NominalWithGrant = -100 #-86; #Luis-70; #thamizh change
msg3_DeltaPreamble = 2;
p0_NominalWithGrant = -100;
# pucch-ConfigCommon setup :
# pucchGroupHopping
# 0 = neither, 1= group hopping, 2=sequence hopping
pucchGroupHopping = 0;
hoppingId = 0; #thamizh change
p0_nominal = -96; #Luis-70; #thamizh change
hoppingId = 0;
p0_nominal = -96;
# ssb_PositionsInBurs_BitmapPR
# 1=short, 2=medium, 3=long
ssb_PositionsInBurst_PR = 2;
ssb_PositionsInBurst_Bitmap = 0x1; #thamizh change
ssb_PositionsInBurst_Bitmap = 0x1;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
......@@ -150,17 +149,11 @@ gNBs =
# pattern1
# dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 5; #thamizh change
nrofDownlinkSlots = 3; #thamizh change
nrofDownlinkSymbols = 6; #thamizh change
nrofUplinkSlots = 1; #thamizh change
nrofUplinkSymbols = 4; #thamizh change
#luis config
#dl_UL_TransmissionPeriodicity = 6; #thamizh change
#nrofDownlinkSlots = 7; #thamizh change
#nrofDownlinkSymbols = 6; #thamizh change
#nrofUplinkSlots = 2; #thamizh change
#nrofUplinkSymbols = 4; #thamizh change
dl_UL_TransmissionPeriodicity = 5;
nrofDownlinkSlots = 3;
nrofDownlinkSymbols = 6;
nrofUplinkSlots = 1;
nrofUplinkSymbols = 4;
ssPBCH_BlockPower = 0;
}
......@@ -220,20 +213,20 @@ L1s = (
prach_dtx_threshold = 130
pucch0_dtx_threshold = 80;
pusch_dtx_threshold = -100;
# max_ldpc_iterations = 6;
max_ldpc_iterations = 10;
#thread_pool_size = 8;
tx_amp_backoff_dB = 3;
L1_rx_thread_core = 8;
L1_tx_thread_core = 10;
phase_compensation = 0;
L1_tx_thread_core = 10; # relevant after merge of l1_tx_thread
phase_compensation = 0; # needs to match O-RU configuration
}
);
RUs = (
{
local_rf = "no"; #thamizh change
nb_tx = 4; #thamizh change
nb_rx = 4; #thamizh change
local_rf = "no";
nb_tx = 4;
nb_rx = 4;
att_tx = 0
att_rx = 0;
bands = [77];
......@@ -245,12 +238,9 @@ RUs = (
sl_ahead = 5;
##beamforming 1x2 matrix: 1 layer x 2 antennas
bf_weights = [0x00007fff, 0x0000,0x00007fff, 0x0000];
#clock_src = "internal";
sdr_addrs = "dummy --usecasefile /home/eurecom/raymond/usecase_du_3999360000_4ant.cfg --num_eth_vfs 2 --vf_addr_o_xu_a \"0000:31:06.0,0000:31:06.1\""
clock_src = "internal"; #thamizh change
tr_preference = "raw_if4p5"; #thamizh change
do_precoding = 0; #thamizh change
clock_src = "internal";
tr_preference = "raw_if4p5"; # important: activate FHI7.2
do_precoding = 0; # needs to match O-RU configuration
}
);
......
......@@ -25,7 +25,7 @@ gNBs =
pdcch_ConfigSIB1 = (
{
controlResourceSetZero = 11; #10; #thamizh change
controlResourceSetZero = 11;
searchSpaceZero = 0;
}
);
......@@ -211,12 +211,11 @@ L1s = (
prach_dtx_threshold = 100;
pucch0_dtx_threshold = 80;
pusch_dtx_threshold = 10;
# max_ldpc_iterations = 6;
#thread_pool_size = 8;
tx_amp_backoff_dB = 20; #36; #6;
max_ldpc_iterations = 10;
tx_amp_backoff_dB = 20; # needs to match O-RU configuration
L1_rx_thread_core = 8;
L1_tx_thread_core = 10;
phase_compensation = 0;
L1_tx_thread_core = 10; # relevant after merge of l1_tx_thread
phase_compensation = 0; # needs to match O-RU configuration
}
);
......@@ -239,8 +238,8 @@ RUs = (
#clock_src = "internal";
sdr_addrs = "dummy --usecasefile /home/eurecom/raymond/usecase_du_3450_4ant.cfg --num_eth_vfs 2 --vf_addr_o_xu_a \"0000:31:06.0,0000:31:06.1\""
clock_src = "internal";
tr_preference = "raw_if4p5"; #thamizh change
do_precoding = 0; #thamizh change
tr_preference = "raw_if4p5"; # important: activate FHI7.2
do_precoding = 0; # needs to match O-RU configuration
}
);
......
......@@ -215,7 +215,7 @@ L1s = (
max_ldpc_iterations = 10;
tx_amp_backoff_dB = 20; # needs to match O-RU configuration
L1_rx_thread_core = 8;
# L1_tx_thread_core = 10; # relevant after merge of l1_tx_thread
L1_tx_thread_core = 10; # relevant after merge of l1_tx_thread
phase_compensation = 1; # needs to match O-RU configuration
}
);
......
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