Commit 9e686e44 authored by Ejaz Ahmed's avatar Ejaz Ahmed

5G sidelink PSFCH Tx implementation

Updates covered in this commit:
1) Computed feedback slot based on PSFCH time gap, PSFCH period and HARQ
	    feedback
2) Generated PSFCH pdu
3) Implemented PSFCH scheduling
4) Allocated PRBs based on slot and subchannel
5) Updated data structures accordingly
6) Modified configuration computation for PSFCH PRB set
7) Changed computation for number of PSFCH symbols
8) Moved sl_preconfiguration.conf under NR-SIDELINK/CONF
parent 5a88bb67
...@@ -624,12 +624,7 @@ void processSlotTX(void *arg) { ...@@ -624,12 +624,7 @@ void processSlotTX(void *arg) {
if (proc->tx_slot_type == NR_SIDELINK_SLOT && UE->sl_mode == 2) { if (proc->tx_slot_type == NR_SIDELINK_SLOT && UE->sl_mode == 2) {
// wait for rx slots to send indication (if any) that SLSCH decoding is finished
// for(int i=0; i < rxtxD->tx_wait_for_slsch; i++) {
// LOG_D(NR_PHY, "tx frame:slot %d:%d, rxtxD->tx_wait_for_slsch: %d pullNotifiedFIFO\n", proc->frame_tx, proc->nr_slot_tx, rxtxD->tx_wait_for_slsch);
// notifiedFIFO_elt_t *res = pullNotifiedFIFO(UE->tx_resume_ind_fifo[proc->nr_slot_tx]);
// delNotifiedFIFO_elt(res);
// }
// trigger L2 to run ue_scheduler thru IF module // trigger L2 to run ue_scheduler thru IF module
if(UE->if_inst != NULL && UE->if_inst->sl_indication != NULL) { if(UE->if_inst != NULL && UE->if_inst->sl_indication != NULL) {
start_meas(&UE->ue_ul_indication_stats); start_meas(&UE->ue_ul_indication_stats);
...@@ -646,7 +641,7 @@ void processSlotTX(void *arg) { ...@@ -646,7 +641,7 @@ void processSlotTX(void *arg) {
sl_indication.phy_data = &phy_data; sl_indication.phy_data = &phy_data;
sl_indication.slot_type = SIDELINK_SLOT_TYPE_TX; sl_indication.slot_type = SIDELINK_SLOT_TYPE_TX;
LOG_D(NR_PHY,"Sending SL indication RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__); LOG_D(NR_PHY,"Sending SL indication RX %d.%d TX %d.%d\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx);
UE->if_inst->sl_indication(&sl_indication); UE->if_inst->sl_indication(&sl_indication);
stop_meas(&UE->ue_ul_indication_stats); stop_meas(&UE->ue_ul_indication_stats);
...@@ -724,24 +719,10 @@ nr_phy_data_t UE_dl_preprocessing(PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) ...@@ -724,24 +719,10 @@ nr_phy_data_t UE_dl_preprocessing(PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc)
if(UE->if_inst != NULL && UE->if_inst->sl_indication != NULL) { if(UE->if_inst != NULL && UE->if_inst->sl_indication != NULL) {
nr_sidelink_indication_t sl_indication; nr_sidelink_indication_t sl_indication;
nr_fill_sl_indication(&sl_indication, NULL, NULL, proc, UE, &phy_data); nr_fill_sl_indication(&sl_indication, NULL, NULL, proc, UE, &phy_data);
LOG_D(NR_PHY, "calling sl_indication: RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
UE->if_inst->sl_indication(&sl_indication); UE->if_inst->sl_indication(&sl_indication);
} }
uint64_t a=rdtsc_oai(); uint64_t a=rdtsc_oai();
psbch_pscch_pssch_processing(UE, proc, &phy_data); psbch_pscch_pssch_processing(UE, proc, &phy_data);
// if (phy_data.sl_active) {
// LOG_I(NR_PHY, "%s sl_active: %d\n", __FUNCTION__, phy_data.sl_active);
// // indicate to tx thread to wait for DLSCH decoding
// sl_nr_phy_config_request_t *sl_cfg = NULL;
// sl_cfg = &UE->SL_UE_PHY_PARAMS.sl_config;
// uint8_t psfch_period = sl_cfg->psfch_period;
// uint8_t psfch_min_time_gap = sl_cfg->time_gap;
// int delta_slots = (proc->nr_slot_rx + psfch_min_time_gap) % psfch_period ? psfch_period - (proc->nr_slot_rx + psfch_min_time_gap) % psfch_period: 0;
// uint8_t feedback_slot = proc->nr_slot_rx + psfch_min_time_gap + delta_slots;
// feedback_slot %= NR_MAX_SLOTS_PER_FRAME;
// UE->tx_wait_for_slsch[feedback_slot]++;
// phy_data.sl_active = false;
// }
LOG_D(PHY, "In %s: slot %d:%d, time %llu\n", __FUNCTION__, proc->frame_rx, proc->nr_slot_rx, (rdtsc_oai()-a)/3500); LOG_D(PHY, "In %s: slot %d:%d, time %llu\n", __FUNCTION__, proc->frame_rx, proc->nr_slot_rx, (rdtsc_oai()-a)/3500);
} }
} else { } else {
...@@ -936,7 +917,6 @@ void *UE_thread(void *arg) ...@@ -936,7 +917,6 @@ void *UE_thread(void *arg)
int num_ind_fifo = nb_slot_frame; int num_ind_fifo = nb_slot_frame;
for(int i=0; i < num_ind_fifo; i++) { for(int i=0; i < num_ind_fifo; i++) {
UE->tx_wait_for_dlsch[num_ind_fifo] = 0; UE->tx_wait_for_dlsch[num_ind_fifo] = 0;
// UE->tx_wait_for_slsch[num_ind_fifo] = 0;
UE->tx_resume_ind_fifo[i] = malloc(sizeof(*UE->tx_resume_ind_fifo[i])); UE->tx_resume_ind_fifo[i] = malloc(sizeof(*UE->tx_resume_ind_fifo[i]));
initNotifiedFIFO(UE->tx_resume_ind_fifo[i]); initNotifiedFIFO(UE->tx_resume_ind_fifo[i]);
} }
...@@ -1105,13 +1085,8 @@ void *UE_thread(void *arg) ...@@ -1105,13 +1085,8 @@ void *UE_thread(void *arg)
curMsgTx->writeBlockSize = writeBlockSize; curMsgTx->writeBlockSize = writeBlockSize;
curMsgTx->proc.timestamp_tx = writeTimestamp; curMsgTx->proc.timestamp_tx = writeTimestamp;
curMsgTx->UE = UE; curMsgTx->UE = UE;
// if (UE->tx_wait_for_slsch[curMsgTx->proc.nr_slot_tx] > 0) {
// curMsgTx->tx_wait_for_slsch = UE->tx_wait_for_slsch[curMsgTx->proc.nr_slot_tx];
// UE->tx_wait_for_slsch[curMsgTx->proc.nr_slot_tx] = 0;
// } else {
curMsgTx->tx_wait_for_dlsch = UE->tx_wait_for_dlsch[curMsgTx->proc.nr_slot_tx]; curMsgTx->tx_wait_for_dlsch = UE->tx_wait_for_dlsch[curMsgTx->proc.nr_slot_tx];
UE->tx_wait_for_dlsch[curMsgTx->proc.nr_slot_tx] = 0; UE->tx_wait_for_dlsch[curMsgTx->proc.nr_slot_tx] = 0;
//}
pushTpool(&(get_nrUE_params()->Tpool), newElt); pushTpool(&(get_nrUE_params()->Tpool), newElt);
// RX slot processing. We launch and forget. // RX slot processing. We launch and forget.
......
...@@ -85,7 +85,6 @@ typedef struct { ...@@ -85,7 +85,6 @@ typedef struct {
int N_RB_DL; int N_RB_DL;
int ssb_start_subcarrier; int ssb_start_subcarrier;
uint32_t sync_ref; uint32_t sync_ref;
int send_psfch_with_pucch;
} nrUE_params_t; } nrUE_params_t;
extern uint64_t get_nrUE_optmask(void); extern uint64_t get_nrUE_optmask(void);
extern uint64_t set_nrUE_optmask(uint64_t bitmask); extern uint64_t set_nrUE_optmask(uint64_t bitmask);
......
...@@ -30,7 +30,6 @@ typedef enum sl_nr_rx_config_type_enum { ...@@ -30,7 +30,6 @@ typedef enum sl_nr_rx_config_type_enum {
SL_NR_CONFIG_TYPE_RX_PSCCH, SL_NR_CONFIG_TYPE_RX_PSCCH,
SL_NR_CONFIG_TYPE_RX_PSSCH_SCI, SL_NR_CONFIG_TYPE_RX_PSSCH_SCI,
SL_NR_CONFIG_TYPE_RX_PSSCH_SLSCH, SL_NR_CONFIG_TYPE_RX_PSSCH_SLSCH,
SL_NR_CONFIG_TYPE_RX_PSFCH,
SL_NR_CONFIG_TYPE_RX_MAXIMUM SL_NR_CONFIG_TYPE_RX_MAXIMUM
} sl_nr_rx_config_type_enum_t; } sl_nr_rx_config_type_enum_t;
...@@ -38,7 +37,7 @@ typedef enum sl_nr_rx_config_type_enum { ...@@ -38,7 +37,7 @@ typedef enum sl_nr_rx_config_type_enum {
typedef enum sl_nr_tx_config_type_enum { typedef enum sl_nr_tx_config_type_enum {
SL_NR_CONFIG_TYPE_TX_PSBCH = SL_NR_CONFIG_TYPE_RX_MAXIMUM + 1, SL_NR_CONFIG_TYPE_TX_PSBCH = SL_NR_CONFIG_TYPE_RX_MAXIMUM + 1,
SL_NR_CONFIG_TYPE_TX_PSCCH_PSSCH, SL_NR_CONFIG_TYPE_TX_PSCCH_PSSCH,
SL_NR_CONFIG_TYPE_TX_PSFCH, SL_NR_CONFIG_TYPE_TX_PSCCH_PSSCH_PSFCH,
SL_NR_CONFIG_TYPE_TX_MAXIMUM SL_NR_CONFIG_TYPE_TX_MAXIMUM
} sl_nr_tx_config_type_enum_t; } sl_nr_tx_config_type_enum_t;
...@@ -210,8 +209,23 @@ typedef struct { ...@@ -210,8 +209,23 @@ typedef struct {
sl_nr_rx_config_request_pdu_t sl_rx_config_list[SL_NR_RX_CONFIG_LIST_NUM]; sl_nr_rx_config_request_pdu_t sl_rx_config_list[SL_NR_RX_CONFIG_LIST_NUM];
} sl_nr_rx_config_request_t; } sl_nr_rx_config_request_t;
typedef struct sl_nr_tx_config_psfch_pdu {
// These fields can be mapped directly to the same fields in nfapi_nr_ul_config_pucch_pdu
uint8_t freq_hop_flag;
uint8_t group_hop_flag;
uint8_t sequence_hop_flag;
uint16_t second_hop_prb;
uint8_t nr_of_symbols;
uint8_t start_symbol_index;
uint8_t hopping_id;
uint16_t prb;
uint16_t sl_bwp_start;
uint16_t initial_cyclic_shift;
uint8_t mcs;
uint8_t bit_len_harq;
} sl_nr_tx_config_psfch_pdu_t;
//MAC commands PHY to transmit Data on PSCCH, PSSCH. //MAC commands PHY to transmit Data on PSCCH, PSSCH.
typedef struct sl_nr_tx_config_pscch_pssch_pdu { typedef struct sl_nr_tx_config_pscch_pssch_psfch_pdu {
//SCI 1A Payload Prepared by MAC, to be sent on PSCCH //SCI 1A Payload Prepared by MAC, to be sent on PSCCH
uint8_t pscch_sci_payload[SL_NR_MAX_PSCCH_SCI_LENGTH_IN_BYTES]; uint8_t pscch_sci_payload[SL_NR_MAX_PSCCH_SCI_LENGTH_IN_BYTES];
...@@ -270,7 +284,8 @@ typedef struct sl_nr_tx_config_pscch_pssch_pdu { ...@@ -270,7 +284,8 @@ typedef struct sl_nr_tx_config_pscch_pssch_pdu {
// Table from SPEC 38.211, Table 8.4.1.1.2-1 // Table from SPEC 38.211, Table 8.4.1.1.2-1
uint16_t dmrs_symbol_position; uint16_t dmrs_symbol_position;
// PSFCH related parameters
sl_nr_tx_config_psfch_pdu_t psfch_pdu;
//....TBD.. any additional parameters //....TBD.. any additional parameters
//TX Power for PSSCH in symbol without PSCCH. //TX Power for PSSCH in symbol without PSCCH.
...@@ -280,7 +295,7 @@ typedef struct sl_nr_tx_config_pscch_pssch_pdu { ...@@ -280,7 +295,7 @@ typedef struct sl_nr_tx_config_pscch_pssch_pdu {
uint16_t slsch_payload_length; uint16_t slsch_payload_length;
uint8_t *slsch_payload; uint8_t *slsch_payload;
} sl_nr_tx_config_pscch_pssch_pdu_t; } sl_nr_tx_config_pscch_pssch_psfch_pdu_t;
// MAC indicates PHY to send PSBCH. // MAC indicates PHY to send PSBCH.
typedef struct sl_nr_tx_config_psbch_pdu { typedef struct sl_nr_tx_config_psbch_pdu {
...@@ -291,44 +306,12 @@ typedef struct sl_nr_tx_config_psbch_pdu { ...@@ -291,44 +306,12 @@ typedef struct sl_nr_tx_config_psbch_pdu {
} sl_nr_tx_config_psbch_pdu_t; } sl_nr_tx_config_psbch_pdu_t;
typedef struct sl_nr_tx_config_psfch_pdu {
// These fields map directly to the same fields in nfapi_nr_ul_config_pucch_pdu
uint8_t freq_hop_flag;
uint8_t group_hop_flag;
uint8_t sequence_hop_flag;
uint16_t second_hop_prb;
uint8_t nr_of_symbols;
uint8_t start_symbol_index;
uint8_t hopping_id;
uint8_t prb;
uint16_t initial_cyclic_shift;
uint8_t mcs;
uint8_t bit_len_harq;
uint8_t psfch_payload;
} sl_nr_tx_config_psfch_pdu_t;
typedef struct sl_nr_rx_config_psfch_pdu {
// These fields map directly to the same fields in nfapi_nr_ul_config_pucch_pdu
uint8_t freq_hop_flag;
uint8_t group_hop_flag;
uint8_t sequence_hop_flag;
uint16_t second_hop_prb;
uint8_t nr_of_symbols;
uint8_t start_symbol_index;
uint8_t hopping_id;
uint8_t prb;
uint16_t initial_cyclic_shift;
uint8_t mcs;
uint8_t psfch_payload;
} sl_nr_rx_config_psfch_pdu_t;
// MAC commands PHY to perform an action on TX RESOURCE POOL or TX PSBCH using this TX CONFIG // MAC commands PHY to perform an action on TX RESOURCE POOL or TX PSBCH using this TX CONFIG
typedef struct { typedef struct {
sl_nr_tx_config_type_enum_t pdu_type; // indicates the type of TX config request sl_nr_tx_config_type_enum_t pdu_type; // indicates the type of TX config request
union { union {
sl_nr_tx_config_psbch_pdu_t tx_psbch_config_pdu; sl_nr_tx_config_psbch_pdu_t tx_psbch_config_pdu;
sl_nr_tx_config_pscch_pssch_pdu_t tx_pscch_pssch_config_pdu; sl_nr_tx_config_pscch_pssch_psfch_pdu_t tx_pscch_pssch_psfch_config_pdu;
sl_nr_tx_config_psfch_pdu_t tx_psfch_config_pdu;
}; };
} sl_nr_tx_config_request_pdu_t; } sl_nr_tx_config_request_pdu_t;
...@@ -407,7 +390,6 @@ typedef struct ...@@ -407,7 +390,6 @@ typedef struct
} sl_nr_carrier_config_t; } sl_nr_carrier_config_t;
typedef struct { typedef struct {
// Mask indicating which of the below configs are changed // Mask indicating which of the below configs are changed
// Bit0 - carrier_config, Bit1 - syncsource cfg // Bit0 - carrier_config, Bit1 - syncsource cfg
...@@ -423,10 +405,6 @@ typedef struct { ...@@ -423,10 +405,6 @@ typedef struct {
sl_nr_bwp_config_t sl_bwp_config; sl_nr_bwp_config_t sl_bwp_config;
uint32_t sl_DMRS_ScrambleId; uint32_t sl_DMRS_ScrambleId;
// PSFCH related configuration to find feedback slot
uint8_t time_gap;
uint8_t psfch_period;
} sl_nr_phy_config_request_t; } sl_nr_phy_config_request_t;
......
...@@ -140,13 +140,12 @@ double nr_cyclic_shift_hopping(uint32_t n_id, ...@@ -140,13 +140,12 @@ double nr_cyclic_shift_hopping(uint32_t n_id,
* - lprime: lprime is the index of the OFDM symbol in the slot that corresponds to the first OFDM symbol of the PUCCH transmission in the slot given by [5, TS 38.213] * - lprime: lprime is the index of the OFDM symbol in the slot that corresponds to the first OFDM symbol of the PUCCH transmission in the slot given by [5, TS 38.213]
*/ */
// alpha_init initialized to 2*PI/12=0.5235987756 // alpha_init initialized to 2*PI/12=0.5235987756
uint8_t is_sidelink = get_softmodem_params()->sl_mode ? 1 : 0;
double alpha = 0.5235987756; double alpha = 0.5235987756;
uint32_t c_init = n_id; // we initialize c_init again to calculate n_cs uint32_t c_init = n_id; // we initialize c_init again to calculate n_cs
uint32_t x1,s = lte_gold_generic(&x1, &c_init, 1); // TS 38.211 Subclause 5.2.1 uint32_t x1,s = lte_gold_generic(&x1, &c_init, 1); // TS 38.211 Subclause 5.2.1
uint8_t n_cs=0; uint8_t n_cs=0;
int l = is_sidelink ? 0 : 32; int l = get_softmodem_params()->sl_mode ? 0 : 32;
int minShift = (14*8*nr_slot_tx) + 8*(lnormal+lprime); int minShift = (14*8*nr_slot_tx) + 8*(lnormal+lprime);
int tmpShift =0; int tmpShift =0;
#ifdef DEBUG_NR_PUCCH_TX #ifdef DEBUG_NR_PUCCH_TX
......
...@@ -2260,7 +2260,7 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, ...@@ -2260,7 +2260,7 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB,
pssch_pdu->sci2_len, pssch_pdu->sci2_len,
sci2_re); sci2_re);
// send SCI indication with SCI2 payload and get SLSCH information if CRC is OK // send SCI indication with SCI2 payload and get SLSCH information if CRC is OK
LOG_I(NR_PHY,"SCI indication (crc %x)\n",crc); LOG_D(NR_PHY,"SCI indication (crc %x)\n",crc);
if (crc==0) ue->SL_UE_PHY_PARAMS.pssch.rx_sci2_ok++; if (crc==0) ue->SL_UE_PHY_PARAMS.pssch.rx_sci2_ok++;
else ue->SL_UE_PHY_PARAMS.pssch.rx_sci2_errors++; else ue->SL_UE_PHY_PARAMS.pssch.rx_sci2_errors++;
sl_nr_sci_indication_t sci_ind={0}; sl_nr_sci_indication_t sci_ind={0};
...@@ -2277,10 +2277,9 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB, ...@@ -2277,10 +2277,9 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB,
memcpy(sci_ind.sci_pdu[sci_ind.number_of_SCIs].sci_payloadBits,&sci_estimation,8); memcpy(sci_ind.sci_pdu[sci_ind.number_of_SCIs].sci_payloadBits,&sci_estimation,8);
sci_ind.number_of_SCIs++; sci_ind.number_of_SCIs++;
nr_sidelink_indication_t sl_indication; nr_sidelink_indication_t sl_indication;
LOG_D(NR_PHY, "calling sl_indication: RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
nr_fill_sl_indication(&sl_indication, NULL, &sci_ind, proc, ue, phy_data); nr_fill_sl_indication(&sl_indication, NULL, &sci_ind, proc, ue, phy_data);
ue->if_inst->sl_indication(&sl_indication); ue->if_inst->sl_indication(&sl_indication);
LOG_I(NR_PHY,"Returning from SCI2 SL indication\n"); LOG_D(NR_PHY,"Returning from SCI2 SL indication\n");
// //
} }
} // (not ML || nrOfLayers==1 ) AND pssch and sci2 REs to handle } // (not ML || nrOfLayers==1 ) AND pssch and sci2 REs to handle
......
...@@ -891,7 +891,7 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, ...@@ -891,7 +891,7 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
sl_nr_sci_indication_t *sci_ind=NULL; sl_nr_sci_indication_t *sci_ind=NULL;
if (pscch_flag == 0) dci_ind = (fapi_nr_dci_indication_t*)ind; if (pscch_flag == 0) dci_ind = (fapi_nr_dci_indication_t*)ind;
else sci_ind = (sl_nr_sci_indication_t *)ind; else sci_ind = (sl_nr_sci_indication_t *)ind;
for (int j=0;j<rel15->number_of_candidates;j++) { for (int j=0;j<rel15->number_of_candidates;j++) {
int CCEind = rel15->CCE[j]; int CCEind = rel15->CCE[j];
int L = rel15->L[j]; int L = rel15->L[j];
......
...@@ -575,7 +575,7 @@ int sl_nr_slss_search(PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc, int num_frame ...@@ -575,7 +575,7 @@ int sl_nr_slss_search(PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc, int num_frame
LOG_D(PHY,"Sidelink SLSS SEARCH PSBCH RX OK. Send SL-SSB TO MAC\n"); LOG_D(PHY,"Sidelink SLSS SEARCH PSBCH RX OK. Send SL-SSB TO MAC\n");
LOG_D(NR_PHY, "calling sl_indication: RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
if (UE->if_inst && UE->if_inst->sl_indication) if (UE->if_inst && UE->if_inst->sl_indication)
UE->if_inst->sl_indication(&sl_indication); UE->if_inst->sl_indication(&sl_indication);
......
...@@ -55,7 +55,7 @@ uint32_t nr_generate_sci1(const PHY_VARS_NR_UE *ue, ...@@ -55,7 +55,7 @@ uint32_t nr_generate_sci1(const PHY_VARS_NR_UE *ue,
const NR_DL_FRAME_PARMS *frame_parms, const NR_DL_FRAME_PARMS *frame_parms,
const int16_t amp, const int16_t amp,
const int nr_slot_tx, const int nr_slot_tx,
const sl_nr_tx_config_pscch_pssch_pdu_t *pscch_pssch_pdu) const sl_nr_tx_config_pscch_pssch_psfch_pdu_t *pscch_pssch_pdu)
{ {
nfapi_nr_dl_tti_pdcch_pdu_rel15_t pdcch_pdu_rel15={0}; nfapi_nr_dl_tti_pdcch_pdu_rel15_t pdcch_pdu_rel15={0};
......
...@@ -60,7 +60,10 @@ void nr_generate_psfch0(const PHY_VARS_NR_UE *ue, ...@@ -60,7 +60,10 @@ void nr_generate_psfch0(const PHY_VARS_NR_UE *ue,
pucch_pdu.initial_cyclic_shift = psfch_pdu->initial_cyclic_shift; pucch_pdu.initial_cyclic_shift = psfch_pdu->initial_cyclic_shift;
pucch_pdu.mcs = psfch_pdu->mcs; pucch_pdu.mcs = psfch_pdu->mcs;
pucch_pdu.nr_of_symbols = psfch_pdu->nr_of_symbols; pucch_pdu.nr_of_symbols = psfch_pdu->nr_of_symbols;
pucch_pdu.payload = psfch_pdu->psfch_payload;
pucch_pdu.n_bit = psfch_pdu->bit_len_harq; pucch_pdu.n_bit = psfch_pdu->bit_len_harq;
nr_generate_pucch0(ue,txdataF,frame_parms,amp,nr_slot_tx,&pucch_pdu); pucch_pdu.bwp_start = psfch_pdu->sl_bwp_start;
pucch_pdu.freq_hop_flag = psfch_pdu->freq_hop_flag;
pucch_pdu.group_hop_flag = psfch_pdu->group_hop_flag;
pucch_pdu.second_hop_prb = psfch_pdu->second_hop_prb;
nr_generate_pucch0(ue, txdataF, frame_parms, amp, nr_slot_tx, &pucch_pdu);
} }
...@@ -211,7 +211,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue, ...@@ -211,7 +211,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
int nr_ulsch_encoding(PHY_VARS_NR_UE *ue, int nr_ulsch_encoding(PHY_VARS_NR_UE *ue,
NR_UE_ULSCH_t *ulsch, NR_UE_ULSCH_t *ulsch,
sl_nr_tx_config_pscch_pssch_pdu_t *pscch_pssch_pdu, sl_nr_tx_config_pscch_pssch_psfch_pdu_t *pscch_pssch_pdu,
NR_DL_FRAME_PARMS* frame_parms, NR_DL_FRAME_PARMS* frame_parms,
uint8_t harq_pid, uint8_t harq_pid,
unsigned int G); unsigned int G);
...@@ -434,7 +434,7 @@ uint32_t nr_generate_sci1(const PHY_VARS_NR_UE *ue, ...@@ -434,7 +434,7 @@ uint32_t nr_generate_sci1(const PHY_VARS_NR_UE *ue,
const NR_DL_FRAME_PARMS *frame_parms, const NR_DL_FRAME_PARMS *frame_parms,
const int16_t amp, const int16_t amp,
const int nr_slot_tx, const int nr_slot_tx,
const sl_nr_tx_config_pscch_pssch_pdu_t *pscch_pssch_pdu); const sl_nr_tx_config_pscch_pssch_psfch_pdu_t *pscch_pssch_pdu);
/**@}*/ /**@}*/
#endif #endif
......
...@@ -43,7 +43,7 @@ ...@@ -43,7 +43,7 @@
int nr_ulsch_encoding(PHY_VARS_NR_UE *ue, int nr_ulsch_encoding(PHY_VARS_NR_UE *ue,
NR_UE_ULSCH_t *ulsch, NR_UE_ULSCH_t *ulsch,
sl_nr_tx_config_pscch_pssch_pdu_t *pscch_pssch_pdu, sl_nr_tx_config_pscch_pssch_psfch_pdu_t *pscch_pssch_pdu,
NR_DL_FRAME_PARMS* frame_parms, NR_DL_FRAME_PARMS* frame_parms,
uint8_t harq_pid, uint8_t harq_pid,
unsigned int G) { unsigned int G) {
......
...@@ -177,7 +177,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE, ...@@ -177,7 +177,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
uint16_t number_dmrs_symbols = 0; uint16_t number_dmrs_symbols = 0;
NR_UE_ULSCH_t *ulsch_ue = &phy_data->ulsch; NR_UE_ULSCH_t *ulsch_ue = &phy_data->ulsch;
sl_nr_tx_config_pscch_pssch_pdu_t *pscch_pssch_pdu = &phy_data->nr_sl_pssch_pscch_pdu; sl_nr_tx_config_pscch_pssch_psfch_pdu_t *pscch_pssch_pdu = &phy_data->nr_sl_pssch_pscch_psfch_pdu;
NR_UL_UE_HARQ_t *harq_process_ul_ue = &UE->ul_harq_processes[harq_pid]; NR_UL_UE_HARQ_t *harq_process_ul_ue = &UE->ul_harq_processes[harq_pid];
const nfapi_nr_ue_pusch_pdu_t *pusch_pdu = &ulsch_ue->pusch_pdu; const nfapi_nr_ue_pusch_pdu_t *pusch_pdu = &ulsch_ue->pusch_pdu;
......
...@@ -40,7 +40,6 @@ ...@@ -40,7 +40,6 @@
#include <openair1/PHY/CODING/nrSmallBlock/nr_small_block_defs.h> #include <openair1/PHY/CODING/nrSmallBlock/nr_small_block_defs.h>
#include "common/utils/LOG/log.h" #include "common/utils/LOG/log.h"
#include "common/utils/LOG/vcd_signal_dumper.h" #include "common/utils/LOG/vcd_signal_dumper.h"
# include "executables/softmodem-common.h"
#include "T.h" #include "T.h"
//#define NR_UNIT_TEST 1 //#define NR_UNIT_TEST 1
......
...@@ -222,7 +222,6 @@ typedef struct { ...@@ -222,7 +222,6 @@ typedef struct {
} NR_UE_PUCCH; } NR_UE_PUCCH;
typedef struct { typedef struct {
int max_nb_pucch;
/// \brief Holds the transmit data in time domain. /// \brief Holds the transmit data in time domain.
/// For IFFT_FPGA this points to the same memory as PHY_vars->tx_vars[a].TX_DMA_BUFFER. /// For IFFT_FPGA this points to the same memory as PHY_vars->tx_vars[a].TX_DMA_BUFFER.
/// - first index: tx antenna [0..nb_antennas_tx[ /// - first index: tx antenna [0..nb_antennas_tx[
...@@ -654,7 +653,6 @@ typedef struct PHY_VARS_NR_UE_s { ...@@ -654,7 +653,6 @@ typedef struct PHY_VARS_NR_UE_s {
notifiedFIFO_t phy_config_ind; notifiedFIFO_t phy_config_ind;
notifiedFIFO_t *tx_resume_ind_fifo[NR_MAX_SLOTS_PER_FRAME]; notifiedFIFO_t *tx_resume_ind_fifo[NR_MAX_SLOTS_PER_FRAME];
int tx_wait_for_dlsch[NR_MAX_SLOTS_PER_FRAME]; int tx_wait_for_dlsch[NR_MAX_SLOTS_PER_FRAME];
// int tx_wait_for_slsch[NR_MAX_SLOTS_PER_FRAME];
//Sidelink parameters //Sidelink parameters
sl_nr_sidelink_mode_t sl_mode; sl_nr_sidelink_mode_t sl_mode;
...@@ -697,22 +695,19 @@ typedef struct nr_phy_data_tx_s { ...@@ -697,22 +695,19 @@ typedef struct nr_phy_data_tx_s {
//Sidelink Tx action decided by MAC //Sidelink Tx action decided by MAC
sl_nr_tx_config_type_enum_t sl_tx_action; sl_nr_tx_config_type_enum_t sl_tx_action;
sl_nr_tx_config_psbch_pdu_t psbch_vars; sl_nr_tx_config_psbch_pdu_t psbch_vars;
sl_nr_tx_config_pscch_pssch_pdu_t nr_sl_pssch_pscch_pdu; sl_nr_tx_config_pscch_pssch_psfch_pdu_t nr_sl_pssch_pscch_psfch_pdu;
uint32_t pscch_Nid; uint32_t pscch_Nid;
sl_nr_tx_config_psfch_pdu_t nr_sl_psfch_pdu;
} nr_phy_data_tx_t; } nr_phy_data_tx_t;
typedef struct nr_phy_data_s { typedef struct nr_phy_data_s {
NR_UE_PDCCH_CONFIG phy_pdcch_config; NR_UE_PDCCH_CONFIG phy_pdcch_config;
NR_UE_DLSCH_t dlsch[2]; NR_UE_DLSCH_t dlsch[2];
bool sl_active;
//Sidelink Rx action decided by MAC //Sidelink Rx action decided by MAC
sl_nr_rx_config_type_enum_t sl_rx_action; sl_nr_rx_config_type_enum_t sl_rx_action;
sl_nr_rx_config_pscch_pdu_t nr_sl_pscch_pdu; sl_nr_rx_config_pscch_pdu_t nr_sl_pscch_pdu;
sl_nr_rx_config_pssch_sci_pdu_t nr_sl_pssch_sci_pdu; sl_nr_rx_config_pssch_sci_pdu_t nr_sl_pssch_sci_pdu;
sl_nr_rx_config_pssch_pdu_t nr_sl_pssch_pdu; sl_nr_rx_config_pssch_pdu_t nr_sl_pssch_pdu;
sl_nr_rx_config_psfch_pdu_t nr_sl_psfch_pdu;
} nr_phy_data_t; } nr_phy_data_t;
/* this structure is used to pass both UE phy vars and /* this structure is used to pass both UE phy vars and
* proc to the function UE_thread_rxn_txnp4 * proc to the function UE_thread_rxn_txnp4
...@@ -724,7 +719,6 @@ typedef struct nr_rxtx_thread_data_s { ...@@ -724,7 +719,6 @@ typedef struct nr_rxtx_thread_data_s {
notifiedFIFO_t txFifo; notifiedFIFO_t txFifo;
nr_phy_data_t phy_data; nr_phy_data_t phy_data;
int tx_wait_for_dlsch; int tx_wait_for_dlsch;
// int tx_wait_for_slsch;
} nr_rxtx_thread_data_t; } nr_rxtx_thread_data_t;
typedef struct LDPCDecode_ue_s { typedef struct LDPCDecode_ue_s {
......
...@@ -186,7 +186,6 @@ typedef struct SL_NR_UE_PSBCH { ...@@ -186,7 +186,6 @@ typedef struct SL_NR_UE_PSBCH {
typedef struct SL_NR_UE_PSFCH { typedef struct SL_NR_UE_PSFCH {
// STATS - transmissions of PSFCH by the UE // STATS - transmissions of PSFCH by the UE
uint16_t num_psfch_tx; uint16_t num_psfch_tx;
} SL_NR_UE_PSFCH_t; } SL_NR_UE_PSFCH_t;
typedef struct sl_nr_ue_phy_params { typedef struct sl_nr_ue_phy_params {
......
...@@ -270,7 +270,7 @@ ...@@ -270,7 +270,7 @@
/* FFS_NR_TODO it defines ue capability which is the number of slots */ /* FFS_NR_TODO it defines ue capability which is the number of slots */
/* - between reception of pdsch and tarnsmission of its acknowlegment */ /* - between reception of pdsch and tarnsmission of its acknowlegment */
/* - between reception of un uplink grant and its related transmission */ /* - between reception of un uplink grant and its related transmission */
#define NR_UE_CAPABILITY_SLOT_RX_TO_TX (3) #define NR_UE_CAPABILITY_SLOT_RX_TO_TX (4)
#ifndef NO_RAT_NR #ifndef NO_RAT_NR
#define DURATION_RX_TO_TX (NR_UE_CAPABILITY_SLOT_RX_TO_TX) /* for NR this will certainly depends to such UE capability which is not yet defined */ #define DURATION_RX_TO_TX (NR_UE_CAPABILITY_SLOT_RX_TO_TX) /* for NR this will certainly depends to such UE capability which is not yet defined */
......
...@@ -749,20 +749,22 @@ int8_t sl_handle_scheduled_response(nr_scheduled_response_t *scheduled_response) ...@@ -749,20 +749,22 @@ int8_t sl_handle_scheduled_response(nr_scheduled_response_t *scheduled_response)
sl_tx_config->tx_config_list[0].tx_psbch_config_pdu.tx_slss_id; sl_tx_config->tx_config_list[0].tx_psbch_config_pdu.tx_slss_id;
break; break;
case SL_NR_CONFIG_TYPE_TX_PSCCH_PSSCH: case SL_NR_CONFIG_TYPE_TX_PSCCH_PSSCH:
phy_data_tx->sl_tx_action = SL_NR_CONFIG_TYPE_TX_PSCCH_PSSCH; case SL_NR_CONFIG_TYPE_TX_PSCCH_PSSCH_PSFCH:
phy_data_tx->nr_sl_pssch_pscch_pdu = sl_tx_config->tx_config_list[0].tx_pscch_pssch_config_pdu; phy_data_tx->sl_tx_action = sl_tx_config->tx_config_list[0].pdu_type;
LOG_D(NR_PHY,"sl_handle_scheduled_response: Received CONFIG_TYPE_TX_PSCCH_PSSCH, PSCCH startRB %d, PSCCH numRB %d\n",phy_data_tx->nr_sl_pssch_pscch_pdu.startrb,phy_data_tx->nr_sl_pssch_pscch_pdu.pscch_numrbs); phy_data_tx->nr_sl_pssch_pscch_psfch_pdu = sl_tx_config->tx_config_list[0].tx_pscch_pssch_psfch_config_pdu;
LOG_D(NR_PHY,"format 1A length %d :%llx, format 2x length %d : %llx, PSSCH mcs %d, PSSCH tbslrm %d\n",phy_data_tx->nr_sl_pssch_pscch_pdu.pscch_sci_payload_len, LOG_D(NR_PHY, "sl_handle_scheduled_response: Received CONFIG_TYPE_TX_PSCCH_PSSCH, PSCCH startRB %d, PSCCH numRB %d\n", phy_data_tx->nr_sl_pssch_pscch_psfch_pdu.startrb,phy_data_tx->nr_sl_pssch_pscch_psfch_pdu.pscch_numrbs);
(unsigned long long)*phy_data_tx->nr_sl_pssch_pscch_pdu.pscch_sci_payload, LOG_D(NR_PHY, "format 1A length %d :%llx, format 2x length %d : %llx, PSSCH mcs %d, PSSCH tbslrm %d\n",phy_data_tx->nr_sl_pssch_pscch_psfch_pdu.pscch_sci_payload_len,
phy_data_tx->nr_sl_pssch_pscch_pdu.sci2_payload_len, (unsigned long long)*phy_data_tx->nr_sl_pssch_pscch_psfch_pdu.pscch_sci_payload,
(unsigned long long)*phy_data_tx->nr_sl_pssch_pscch_pdu.sci2_payload, phy_data_tx->nr_sl_pssch_pscch_psfch_pdu.sci2_payload_len,
phy_data_tx->nr_sl_pssch_pscch_pdu.mcs, (unsigned long long)*phy_data_tx->nr_sl_pssch_pscch_psfch_pdu.sci2_payload,
phy_data_tx->nr_sl_pssch_pscch_pdu.tbslbrm); phy_data_tx->nr_sl_pssch_pscch_psfch_pdu.mcs,
break; phy_data_tx->nr_sl_pssch_pscch_psfch_pdu.tbslbrm);
case SL_NR_CONFIG_TYPE_TX_PSFCH: if (phy_data_tx->sl_tx_action == SL_NR_CONFIG_TYPE_TX_PSCCH_PSSCH_PSFCH) {
LOG_I(NR_PHY, "Recvd CONFIG_TYPE_TX_PSFCH\n"); LOG_D(NR_PHY, "Recvd SL_NR_CONFIG_TYPE_TX_PSCCH_PSSCH_PSFCH\n");
phy_data_tx->sl_tx_action = SL_NR_CONFIG_TYPE_TX_PSFCH; phy_data_tx->nr_sl_pssch_pscch_psfch_pdu.psfch_pdu = sl_tx_config->tx_config_list[0].tx_pscch_pssch_psfch_config_pdu.psfch_pdu;
phy_data_tx->nr_sl_psfch_pdu = sl_tx_config->tx_config_list[0].tx_psfch_config_pdu; } else {
LOG_D(NR_PHY, "Recvd SL_NR_CONFIG_TYPE_TX_PSCCH_PSSCH\n");
}
break; break;
default: default:
AssertFatal(0,"Incorrect sl_tx config req pdutype \n"); AssertFatal(0,"Incorrect sl_tx config req pdutype \n");
......
...@@ -150,7 +150,7 @@ int sl_nr_ue_slot_select(sl_nr_phy_config_request_t *cfg, ...@@ -150,7 +150,7 @@ int sl_nr_ue_slot_select(sl_nr_phy_config_request_t *cfg,
ul_sym++; ul_sym++;
} }
} }
LOG_D(NR_MAC, "frame:slot %d:%d num of ul_sym %d, NR_NUMBER_OF_SYMBOLS_PER_SLOT %d\n", nr_frame, nr_slot, ul_sym, NR_NUMBER_OF_SYMBOLS_PER_SLOT);
if(ul_sym == NR_NUMBER_OF_SYMBOLS_PER_SLOT) { if(ul_sym == NR_NUMBER_OF_SYMBOLS_PER_SLOT) {
slot_type = NR_SIDELINK_SLOT; slot_type = NR_SIDELINK_SLOT;
} else if (ul_sym){ } else if (ul_sym){
......
...@@ -494,7 +494,6 @@ int nr_ue_pdcch_procedures(PHY_VARS_NR_UE *ue, ...@@ -494,7 +494,6 @@ int nr_ue_pdcch_procedures(PHY_VARS_NR_UE *ue,
sci_ind.number_of_SCIs = dci_cnt; sci_ind.number_of_SCIs = dci_cnt;
// fill sl_indication message // fill sl_indication message
nr_fill_sl_indication(&sl_indication, NULL, &sci_ind, proc, ue, phy_data); nr_fill_sl_indication(&sl_indication, NULL, &sci_ind, proc, ue, phy_data);
LOG_D(NR_PHY, "calling sl_indication: RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
// send to mac // send to mac
ue->if_inst->sl_indication(&sl_indication); ue->if_inst->sl_indication(&sl_indication);
} }
...@@ -658,7 +657,6 @@ void send_slot_ind(notifiedFIFO_t *nf, int slot) { ...@@ -658,7 +657,6 @@ void send_slot_ind(notifiedFIFO_t *nf, int slot) {
notifiedFIFO_elt_t *newElt = newNotifiedFIFO_elt(sizeof(int), 0, NULL, NULL); notifiedFIFO_elt_t *newElt = newNotifiedFIFO_elt(sizeof(int), 0, NULL, NULL);
int *msgData = (int *) NotifiedFifoData(newElt); int *msgData = (int *) NotifiedFifoData(newElt);
*msgData = slot; *msgData = slot;
LOG_I(PHY, "Pushed slot %d in notified fifo\n", slot);
pushNotifiedFIFO(nf, newElt); pushNotifiedFIFO(nf, newElt);
} }
} }
......
...@@ -92,6 +92,7 @@ void nr_fill_sl_rx_indication(sl_nr_rx_indication_t *rx_ind, ...@@ -92,6 +92,7 @@ void nr_fill_sl_rx_indication(sl_nr_rx_indication_t *rx_ind,
rx_slsch_pdu->pdu_length = slsch_status->rdata->ulsch_harq->TBS; rx_slsch_pdu->pdu_length = slsch_status->rdata->ulsch_harq->TBS;
rx_slsch_pdu->harq_pid = slsch_status->rdata->harq_pid; rx_slsch_pdu->harq_pid = slsch_status->rdata->harq_pid;
rx_slsch_pdu->ack_nack = (slsch_status->rxok==true) ? 1 : 0; rx_slsch_pdu->ack_nack = (slsch_status->rxok==true) ? 1 : 0;
if (slsch_status->rxok==true) ue->SL_UE_PHY_PARAMS.pssch.rx_ok++; if (slsch_status->rxok==true) ue->SL_UE_PHY_PARAMS.pssch.rx_ok++;
else ue->SL_UE_PHY_PARAMS.pssch.rx_errors[0]++; else ue->SL_UE_PHY_PARAMS.pssch.rx_errors[0]++;
} }
...@@ -218,18 +219,6 @@ int nr_slsch_procedures(PHY_VARS_NR_UE *ue, int frame_rx, int slot_rx, int SLSCH ...@@ -218,18 +219,6 @@ int nr_slsch_procedures(PHY_VARS_NR_UE *ue, int frame_rx, int slot_rx, int SLSCH
int nbDecode = int nbDecode =
nr_ulsch_decoding(NULL, ue, SLSCH_id, ue->pssch_vars[SLSCH_id].llr, fp, &pusch_pdu, frame_rx, slot_rx, harq_pid, G,proc,phy_data); nr_ulsch_decoding(NULL, ue, SLSCH_id, ue->pssch_vars[SLSCH_id].llr, fp, &pusch_pdu, frame_rx, slot_rx, harq_pid, G,proc,phy_data);
// sl_nr_phy_config_request_t *sl_cfg = NULL;
// sl_cfg = &ue->SL_UE_PHY_PARAMS.sl_config;
// uint8_t psfch_period = sl_cfg->psfch_period;
// uint8_t psfch_min_time_gap = sl_cfg->time_gap;
// int delta_slots = (slot_rx + psfch_min_time_gap) % psfch_period ? psfch_period - (slot_rx + psfch_min_time_gap) % psfch_period: 0;
// uint8_t feedback_slot = slot_rx + psfch_min_time_gap + delta_slots;
// feedback_slot %= NR_MAX_SLOTS_PER_FRAME;
// phy_data->sl_active = true;
// send_slot_ind(ue->tx_resume_ind_fifo[feedback_slot], slot_rx);
// LOG_D(NR_PHY, "%s Sent slot indication: slot_rx %d feedback_slot %d, sl_active %d\n", __FUNCTION__, slot_rx, feedback_slot, phy_data->sl_active);
// LOG_I(NR_MAC, "harq pid: %d Sent slot indication psfch_period %d, slot_rx %d, delta_slots %d, feedback_slot %d, time_gap %d\n", harq_pid, psfch_period, slot_rx, delta_slots, feedback_slot, psfch_min_time_gap);
return nbDecode; return nbDecode;
} }
...@@ -300,12 +289,10 @@ void nr_postDecode_slsch(PHY_VARS_NR_UE *UE, notifiedFIFO_elt_t *req,UE_nr_rxtx_ ...@@ -300,12 +289,10 @@ void nr_postDecode_slsch(PHY_VARS_NR_UE *UE, notifiedFIFO_elt_t *req,UE_nr_rxtx_
// dumpsig=1; // dumpsig=1;
} }
slsch->last_iteration_cnt = rdata->decodeIterations; slsch->last_iteration_cnt = rdata->decodeIterations;
// FIXME: There may be need to add condition for PSFCH
sl_rx_indication.sfn = proc->frame_rx; sl_rx_indication.sfn = proc->frame_rx;
sl_rx_indication.slot = proc->nr_slot_rx; sl_rx_indication.slot = proc->nr_slot_rx;
nr_fill_sl_rx_indication(&sl_rx_indication,SL_NR_RX_PDU_TYPE_SLSCH,UE,1,proc,(void*)&slsch_status,0); nr_fill_sl_rx_indication(&sl_rx_indication,SL_NR_RX_PDU_TYPE_SLSCH,UE,1,proc,(void*)&slsch_status,0);
nr_fill_sl_indication(&sl_indication,&sl_rx_indication,NULL,proc,UE,phy_data); nr_fill_sl_indication(&sl_indication,&sl_rx_indication,NULL,proc,UE,phy_data);
LOG_D(NR_PHY, "calling sl_indication: RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
if (UE->if_inst && UE->if_inst->sl_indication) if (UE->if_inst && UE->if_inst->sl_indication)
UE->if_inst->sl_indication(&sl_indication); UE->if_inst->sl_indication(&sl_indication);
/* /*
...@@ -396,7 +383,7 @@ static int nr_ue_psbch_procedures(PHY_VARS_NR_UE *ue, ...@@ -396,7 +383,7 @@ static int nr_ue_psbch_procedures(PHY_VARS_NR_UE *ue,
nr_fill_sl_indication(&sl_indication, &rx_ind, NULL, proc, ue, phy_data); nr_fill_sl_indication(&sl_indication, &rx_ind, NULL, proc, ue, phy_data);
nr_fill_sl_rx_indication(&rx_ind, SL_NR_RX_PDU_TYPE_SSB, ue, number_pdus, proc, (void *)result, rx_slss_id); nr_fill_sl_rx_indication(&rx_ind, SL_NR_RX_PDU_TYPE_SSB, ue, number_pdus, proc, (void *)result, rx_slss_id);
LOG_D(NR_PHY, "calling sl_indication: RX %d.%d TX %d.%d %s\n",proc->frame_rx,proc->nr_slot_rx,proc->frame_tx,proc->nr_slot_tx, __FUNCTION__);
if (ue->if_inst && ue->if_inst->sl_indication) if (ue->if_inst && ue->if_inst->sl_indication)
ue->if_inst->sl_indication(&sl_indication); ue->if_inst->sl_indication(&sl_indication);
...@@ -451,7 +438,7 @@ void psbch_pscch_pssch_processing(PHY_VARS_NR_UE *ue, ...@@ -451,7 +438,7 @@ void psbch_pscch_pssch_processing(PHY_VARS_NR_UE *ue,
sl_phy_params->pssch.rx_errors[1], sl_phy_params->pssch.rx_errors[1],
sl_phy_params->pssch.rx_errors[2], sl_phy_params->pssch.rx_errors[2],
sl_phy_params->pssch.rx_errors[3]); sl_phy_params->pssch.rx_errors[3]);
LOG_I(NR_PHY, "%s[UE%d] %d:%d PSFCH Stats: TX %d, RX \n",KGRN, LOG_I(NR_PHY, "%s[UE%d] %d:%d PSFCH Stats: TX %d\n", KGRN,
ue->Mod_id, frame_rx, nr_slot_rx, ue->Mod_id, frame_rx, nr_slot_rx,
sl_phy_params->psfch.num_psfch_tx sl_phy_params->psfch.num_psfch_tx
); );
...@@ -724,31 +711,31 @@ int phy_procedures_nrUE_SL_TX(PHY_VARS_NR_UE *ue, ...@@ -724,31 +711,31 @@ int phy_procedures_nrUE_SL_TX(PHY_VARS_NR_UE *ue,
tx_action = 1; tx_action = 1;
} }
else if (phy_data->sl_tx_action == SL_NR_CONFIG_TYPE_TX_PSCCH_PSSCH) { else if (phy_data->sl_tx_action == SL_NR_CONFIG_TYPE_TX_PSCCH_PSSCH ||
LOG_D(NR_PHY,"Generating PSCCH (%d.%d) \n",frame_tx,slot_tx); phy_data->sl_tx_action == SL_NR_CONFIG_TYPE_TX_PSCCH_PSSCH_PSFCH) {
LOG_D(NR_PHY, "Generating PSCCH (%d.%d) \n", frame_tx, slot_tx);
phy_data->pscch_Nid = nr_generate_sci1(ue,txdataF[0],fp,AMP,slot_tx,&phy_data->nr_sl_pssch_pscch_pdu) &0xFFFF;
phy_data->pscch_Nid = nr_generate_sci1(ue, txdataF[0], fp, AMP, slot_tx, &phy_data->nr_sl_pssch_pscch_psfch_pdu) &0xFFFF;
nr_ue_ulsch_procedures(ue,0,frame_tx,slot_tx,0,phy_data,txdataF);
nr_ue_ulsch_procedures(ue,0,frame_tx,slot_tx,0,phy_data,txdataF);
sl_phy_params->pscch.num_pscch_tx ++;
sl_phy_params->pssch.num_pssch_sci2_tx ++; sl_phy_params->pscch.num_pscch_tx ++;
sl_phy_params->pssch.num_pssch_tx ++; sl_phy_params->pssch.num_pssch_sci2_tx ++;
tx_action = 1; sl_phy_params->pssch.num_pssch_tx ++;
} if (phy_data->sl_tx_action == SL_NR_CONFIG_TYPE_TX_PSCCH_PSSCH_PSFCH) {
else if (phy_data->sl_tx_action == SL_NR_CONFIG_TYPE_TX_PSFCH) { LOG_D(NR_PHY, "Generating PSFCH (%d.%d) \n", frame_tx, slot_tx);
LOG_I(NR_PHY,"Generating PSFCH ( )\n"); nr_generate_psfch0(ue,
nr_generate_psfch0(ue, txdataF,
txdataF, fp,
fp, AMP,
AMP, slot_tx,
slot_tx, &phy_data->nr_sl_pssch_pscch_psfch_pdu.psfch_pdu);
&phy_data->nr_sl_psfch_pdu); sl_phy_params->psfch.num_psfch_tx ++;
sl_phy_params->psfch.num_psfch_tx ++; }
tx_action = 1; tx_action = 1;
LOG_I(NR_PHY, "Sending SL data frame %d slot %d\n", frame_tx, slot_tx);
} }
if (tx_action) { if (tx_action) {
LOG_D(PHY, "Sending SL data \n");
nr_ue_pusch_common_procedures(ue, nr_ue_pusch_common_procedures(ue,
proc->nr_slot_tx, proc->nr_slot_tx,
fp, fp,
......
...@@ -230,7 +230,7 @@ void pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, const UE_nr_rxtx_proc_t *proc, n ...@@ -230,7 +230,7 @@ void pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, const UE_nr_rxtx_proc_t *proc, n
tx_amp = AMP; tx_amp = AMP;
LOG_I(PHY,"Generation of PUCCH format %d at frame.slot %d.%d\n",pucch_pdu->format_type,proc->frame_tx,nr_slot_tx); LOG_D(PHY,"Generation of PUCCH format %d at frame.slot %d.%d\n",pucch_pdu->format_type,proc->frame_tx,nr_slot_tx);
switch(pucch_pdu->format_type) { switch(pucch_pdu->format_type) {
case 0: case 0:
......
...@@ -457,13 +457,6 @@ int nr_rrc_mac_config_req_sl_preconfig(module_id_t module_id, ...@@ -457,13 +457,6 @@ int nr_rrc_mac_config_req_sl_preconfig(module_id_t module_id,
nr_sl_phy_config_t *sl_phy_cfg = &sl_mac->sl_phy_config; nr_sl_phy_config_t *sl_phy_cfg = &sl_mac->sl_phy_config;
sl_phy_cfg->Mod_id = module_id; sl_phy_cfg->Mod_id = module_id;
sl_phy_cfg->CC_id = 0; sl_phy_cfg->CC_id = 0;
const uint8_t psfch_periods[] = {0,1,2,4};
const uint8_t time_gaps[] = {2, 3};
NR_SL_PSFCH_Config_r16_t *psfch_config = mac->sl_tx_res_pool->sl_PSFCH_Config_r16->choice.setup;
uint8_t psfch_period_index = *psfch_config->sl_PSFCH_Period_r16;
uint8_t psfch_time_gap_indx = *psfch_config->sl_MinTimeGapPSFCH_r16;
sl_phy_cfg->sl_config_req.psfch_period = psfch_periods[psfch_period_index];
sl_phy_cfg->sl_config_req.time_gap = time_gaps[psfch_time_gap_indx];
sl_prepare_phy_config(module_id, &sl_phy_cfg->sl_config_req, sl_prepare_phy_config(module_id, &sl_phy_cfg->sl_config_req,
freqcfg, sync_source, sl_OffsetDFN, sl_mac->sl_TDD_config); freqcfg, sync_source, sl_OffsetDFN, sl_mac->sl_TDD_config);
......
...@@ -499,10 +499,13 @@ bool nr_schedule_slsch(NR_UE_MAC_INST_t *mac, int frameP, int slotP, nr_sci_pdu_ ...@@ -499,10 +499,13 @@ bool nr_schedule_slsch(NR_UE_MAC_INST_t *mac, int frameP, int slotP, nr_sci_pdu_
nr_sci_format_t format2, nr_sci_format_t format2,
uint16_t *slsch_pdu_length); uint16_t *slsch_pdu_length);
void config_psfch_pdu_rx(NR_UE_MAC_INST_t *mac, void nr_ue_sl_psfch_scheduler(NR_UE_MAC_INST_t *mac,
sl_nr_rx_config_psfch_pdu_t *nr_sl_psfch_pdu, long psfch_period,
const NR_SL_BWP_Generic_r16_t *sl_bwp, nr_sidelink_indication_t *sl_ind,
const NR_SL_ResourcePool_r16_t *sl_res_pool); const NR_SL_BWP_ConfigCommon_r16_t *sl_bwp,
const NR_SL_ResourcePool_r16_t *sl_res_pool,
sl_nr_tx_config_request_t *tx_config,
uint8_t *config_type);
void config_pscch_pdu_rx(sl_nr_rx_config_pscch_pdu_t *nr_sl_pscch_pdu, void config_pscch_pdu_rx(sl_nr_rx_config_pscch_pdu_t *nr_sl_pscch_pdu,
const NR_SL_BWP_ConfigCommon_r16_t *sl_bwp, const NR_SL_BWP_ConfigCommon_r16_t *sl_bwp,
...@@ -516,7 +519,7 @@ int config_pssch_sci_pdu_rx(sl_nr_rx_config_pssch_sci_pdu_t *nr_sl_pssch_sci_pdu ...@@ -516,7 +519,7 @@ int config_pssch_sci_pdu_rx(sl_nr_rx_config_pssch_sci_pdu_t *nr_sl_pssch_sci_pdu
const NR_SL_BWP_ConfigCommon_r16_t *sl_bwp, const NR_SL_BWP_ConfigCommon_r16_t *sl_bwp,
const NR_SL_ResourcePool_r16_t *sl_res_pool); const NR_SL_ResourcePool_r16_t *sl_res_pool);
void fill_pssch_pscch_pdu(sl_nr_tx_config_pscch_pssch_pdu_t *nr_sl_pssch_pscch_pdu, void fill_pssch_pscch_pdu(sl_nr_tx_config_pscch_pssch_psfch_pdu_t *nr_sl_pssch_pscch_pdu,
const NR_SL_BWP_ConfigCommon_r16_t *sl_bwp, const NR_SL_BWP_ConfigCommon_r16_t *sl_bwp,
const NR_SL_ResourcePool_r16_t *sl_res_pool, const NR_SL_ResourcePool_r16_t *sl_res_pool,
nr_sci_pdu_t *sci_pdu, nr_sci_pdu_t *sci_pdu,
...@@ -524,5 +527,9 @@ void fill_pssch_pscch_pdu(sl_nr_tx_config_pscch_pssch_pdu_t *nr_sl_pssch_pscch_p ...@@ -524,5 +527,9 @@ void fill_pssch_pscch_pdu(sl_nr_tx_config_pscch_pssch_pdu_t *nr_sl_pssch_pscch_p
uint16_t slsch_pdu_length, uint16_t slsch_pdu_length,
const nr_sci_format_t format1, const nr_sci_format_t format1,
const nr_sci_format_t format2); const nr_sci_format_t format2);
void fill_psfch_pdu(sl_nr_tx_config_psfch_pdu_t *mac_psfch_pdu,
sl_nr_tx_config_request_t *tx_config,
int num_psfch_symbols);
#endif #endif
/** @}*/ /** @}*/
...@@ -39,15 +39,19 @@ ...@@ -39,15 +39,19 @@
#include "NR_MAC_UE/mac_proto.h" #include "NR_MAC_UE/mac_proto.h"
#include "NR_MAC_UE/mac_extern.h" #include "NR_MAC_UE/mac_extern.h"
#include "NR_MAC_UE/nr_ue_sci.h" #include "NR_MAC_UE/nr_ue_sci.h"
#include <executables/nr-uesoftmodem.h>
bool nr_schedule_slsch(NR_UE_MAC_INST_t *mac, int frameP,int slotP, nr_sci_pdu_t *sci_pdu,nr_sci_pdu_t *sci2_pdu,uint8_t *slsch_pdu,nr_sci_format_t format2, uint16_t *slsch_pdu_length_max) { bool nr_schedule_slsch(NR_UE_MAC_INST_t *mac, int frameP,int slotP, nr_sci_pdu_t *sci_pdu,nr_sci_pdu_t *sci2_pdu,uint8_t *slsch_pdu,nr_sci_format_t format2, uint16_t *slsch_pdu_length_max) {
mac_rlc_status_resp_t rlc_status = mac_rlc_status_ind(0, mac->src_id, 0,frameP,slotP,ENB_FLAG_NO,MBMS_FLAG_NO, 4, 0, 0); mac_rlc_status_resp_t rlc_status = mac_rlc_status_ind(0, mac->src_id, 0,frameP,slotP,ENB_FLAG_NO,MBMS_FLAG_NO, 4, 0, 0);
uint8_t psfch_period = 0;
if (mac->sl_tx_res_pool->sl_PSFCH_Config_r16)
psfch_period = *mac->sl_tx_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16;
// rlc_status.bytes_in_buffer = 0; // rlc_status.bytes_in_buffer = 0;
*slsch_pdu_length_max = 0; *slsch_pdu_length_max = 0;
if (rlc_status.bytes_in_buffer > 0) { if (rlc_status.bytes_in_buffer > 0 || mac->sci_pdu_rx.harq_feedback) {
// Fill SCI1A // Fill SCI1A
sci_pdu->priority = 0; sci_pdu->priority = 0;
sci_pdu->frequency_resource_assignment.val=0; sci_pdu->frequency_resource_assignment.val=0;
...@@ -64,13 +68,13 @@ bool nr_schedule_slsch(NR_UE_MAC_INST_t *mac, int frameP,int slotP, nr_sci_pdu_t ...@@ -64,13 +68,13 @@ bool nr_schedule_slsch(NR_UE_MAC_INST_t *mac, int frameP,int slotP, nr_sci_pdu_t
sci_pdu->beta_offset_indicator = 0; sci_pdu->beta_offset_indicator = 0;
// Fill SCI2A // Fill SCI2A
sci2_pdu->harq_pid = slotP; // slotP FIXIT - The value should only be 0-15 which can be in 4-bits sci2_pdu->harq_pid = 0;
sci2_pdu->ndi = (1-sci2_pdu->ndi)&1; sci2_pdu->ndi = (1-sci2_pdu->ndi)&1;
sci2_pdu->rv_index=0; sci2_pdu->rv_index=0;
sci2_pdu->source_id=0x12; sci2_pdu->source_id = get_softmodem_params()->node_number;
sci2_pdu->dest_id=0xabcd; sci2_pdu->dest_id=0xabcd;
sci2_pdu->harq_feedback=1; sci2_pdu->harq_feedback = psfch_period ? 1 : 0;
sci2_pdu->cast_type=2; sci2_pdu->cast_type = 1;
if (format2==NR_SL_SCI_FORMAT_2C || format2==NR_SL_SCI_FORMAT_2A) if (format2==NR_SL_SCI_FORMAT_2C || format2==NR_SL_SCI_FORMAT_2A)
sci2_pdu->csi_req=1; sci2_pdu->csi_req=1;
if (format2==NR_SL_SCI_FORMAT_2B) if (format2==NR_SL_SCI_FORMAT_2B)
......
This diff is collapsed.
...@@ -194,7 +194,7 @@ int get_nREDMRS(const NR_SL_ResourcePool_r16_t *sl_res_pool) { ...@@ -194,7 +194,7 @@ int get_nREDMRS(const NR_SL_ResourcePool_r16_t *sl_res_pool) {
return(nREDMRS/cnt); return(nREDMRS/cnt);
} }
void fill_pssch_pscch_pdu(sl_nr_tx_config_pscch_pssch_pdu_t *nr_sl_pssch_pscch_pdu, void fill_pssch_pscch_pdu(sl_nr_tx_config_pscch_pssch_psfch_pdu_t *nr_sl_pssch_pscch_pdu,
const NR_SL_BWP_ConfigCommon_r16_t *sl_bwp, const NR_SL_BWP_ConfigCommon_r16_t *sl_bwp,
const NR_SL_ResourcePool_r16_t *sl_res_pool, const NR_SL_ResourcePool_r16_t *sl_res_pool,
nr_sci_pdu_t *sci_pdu, nr_sci_pdu_t *sci_pdu,
...@@ -245,11 +245,10 @@ void fill_pssch_pscch_pdu(sl_nr_tx_config_pscch_pssch_pdu_t *nr_sl_pssch_pscch_p ...@@ -245,11 +245,10 @@ void fill_pssch_pscch_pdu(sl_nr_tx_config_pscch_pssch_pdu_t *nr_sl_pssch_pscch_p
nr_sl_pssch_pscch_pdu->num_subch, nr_sl_pssch_pscch_pdu->num_subch,
nr_sl_pssch_pscch_pdu->subchannel_size); nr_sl_pssch_pscch_pdu->subchannel_size);
if (sl_res_pool->sl_PSFCH_Config_r16 && sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16 && *sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16>0) { if (sl_res_pool->sl_PSFCH_Config_r16 && sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16 && *sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16>0) {
num_psfch_symbols = *sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16; // As per 38214 8.1.3.2, num_psfch_symbols can be 3 if psfch_overhead_indication.nbits is 1; FYI psfch_overhead_indication.nbits is set to 1 in case of PSFCH period 2 or 4 in sl_determine_sci_1a_len()
if (num_psfch_symbols == 3) num_psfch_symbols++; num_psfch_symbols = 3;
} }
nr_sl_pssch_pscch_pdu->pssch_numsym=7+*sl_bwp->sl_BWP_Generic_r16->sl_LengthSymbols_r16-num_psfch_symbols-2; nr_sl_pssch_pscch_pdu->pssch_numsym=7+*sl_bwp->sl_BWP_Generic_r16->sl_LengthSymbols_r16-num_psfch_symbols-2;
LOG_D(NR_PHY, "num_psfch_symbols %d, sl_LengthSymbols: %d, pssch_numsym: %d\n", num_psfch_symbols, *sl_bwp->sl_BWP_Generic_r16->sl_LengthSymbols_r16, nr_sl_pssch_pscch_pdu->pssch_numsym);
nr_sl_pssch_pscch_pdu->pssch_startsym = *sl_bwp->sl_BWP_Generic_r16->sl_StartSymbol_r16; nr_sl_pssch_pscch_pdu->pssch_startsym = *sl_bwp->sl_BWP_Generic_r16->sl_StartSymbol_r16;
nr_sl_pssch_pscch_pdu->sci2_beta_offset = *sl_res_pool->sl_PSSCH_Config_r16->choice.setup->sl_BetaOffsets2ndSCI_r16->list.array[sci_pdu->beta_offset_indicator]; nr_sl_pssch_pscch_pdu->sci2_beta_offset = *sl_res_pool->sl_PSSCH_Config_r16->choice.setup->sl_BetaOffsets2ndSCI_r16->list.array[sci_pdu->beta_offset_indicator];
...@@ -462,26 +461,6 @@ void fill_pssch_pscch_pdu(sl_nr_tx_config_pscch_pssch_pdu_t *nr_sl_pssch_pscch_p ...@@ -462,26 +461,6 @@ void fill_pssch_pscch_pdu(sl_nr_tx_config_pscch_pssch_pdu_t *nr_sl_pssch_pscch_p
nr_sl_pssch_pscch_pdu->slsch_payload_length = slsch_pdu_length; nr_sl_pssch_pscch_pdu->slsch_payload_length = slsch_pdu_length;
}; };
void config_psfch_pdu_rx(NR_UE_MAC_INST_t *mac,
sl_nr_rx_config_psfch_pdu_t *nr_sl_psfch_pdu,
const NR_SL_BWP_Generic_r16_t *sl_bwp,
const NR_SL_ResourcePool_r16_t *sl_res_pool) {
nr_sl_psfch_pdu->freq_hop_flag = 0;
nr_sl_psfch_pdu->group_hop_flag = 0;
nr_sl_psfch_pdu->sequence_hop_flag = 0;
nr_sl_psfch_pdu->second_hop_prb = 0;
nr_sl_psfch_pdu->nr_of_symbols = 1;
const uint8_t values[] = {7, 8, 9, 10, 11, 12, 13, 14};
uint8_t sl_num_symbols = *sl_bwp->sl_LengthSymbols_r16 ?
values[*sl_bwp->sl_LengthSymbols_r16] : 0;
nr_sl_psfch_pdu->start_symbol_index = *sl_bwp->sl_StartSymbol_r16 + sl_num_symbols - 2;
nr_sl_psfch_pdu->hopping_id = 0;
nr_sl_psfch_pdu->prb = 1;
//TODO
// nr_sl_psfch_pdu->initial_cyclic_shift = mac->sl_;
// nr_sl_psfch_pdu->mcs = mac->sl_;
}
void config_pscch_pdu_rx(sl_nr_rx_config_pscch_pdu_t *nr_sl_pscch_pdu, void config_pscch_pdu_rx(sl_nr_rx_config_pscch_pdu_t *nr_sl_pscch_pdu,
const NR_SL_BWP_ConfigCommon_r16_t *sl_bwp, const NR_SL_BWP_ConfigCommon_r16_t *sl_bwp,
const NR_SL_ResourcePool_r16_t *sl_res_pool){ const NR_SL_ResourcePool_r16_t *sl_res_pool){
...@@ -511,8 +490,8 @@ void config_pscch_pdu_rx(sl_nr_rx_config_pscch_pdu_t *nr_sl_pscch_pdu, ...@@ -511,8 +490,8 @@ void config_pscch_pdu_rx(sl_nr_rx_config_pscch_pdu_t *nr_sl_pscch_pdu,
//Indicates the number of symbols for PSCCH+PSSCH txn //Indicates the number of symbols for PSCCH+PSSCH txn
int num_psfch_symbols=0; int num_psfch_symbols=0;
if (sl_res_pool->sl_PSFCH_Config_r16 && sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16 && *sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16>0) { if (sl_res_pool->sl_PSFCH_Config_r16 && sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16 && *sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16>0) {
num_psfch_symbols = *sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16; // As per 38214 8.1.3.2, num_psfch_symbols can be 3 if psfch_overhead_indication.nbits is 1; FYI psfch_overhead_indication.nbits is set to 1 in case of PSFCH period 2 or 4 in sl_determine_sci_1a_len()
if (num_psfch_symbols == 3) num_psfch_symbols++; num_psfch_symbols = 3;
} }
nr_sl_pscch_pdu->pssch_numsym=7+*sl_bwp->sl_BWP_Generic_r16->sl_LengthSymbols_r16-num_psfch_symbols-2; nr_sl_pscch_pdu->pssch_numsym=7+*sl_bwp->sl_BWP_Generic_r16->sl_LengthSymbols_r16-num_psfch_symbols-2;
//sci 1A length used to decode on PSCCH. //sci 1A length used to decode on PSCCH.
...@@ -671,8 +650,8 @@ void config_pssch_slsch_pdu_rx(sl_nr_rx_config_pssch_pdu_t *nr_sl_pssch_pdu, ...@@ -671,8 +650,8 @@ void config_pssch_slsch_pdu_rx(sl_nr_rx_config_pssch_pdu_t *nr_sl_pssch_pdu,
nr_sl_pssch_pdu->num_layers); nr_sl_pssch_pdu->num_layers);
int num_psfch_symbols=0; int num_psfch_symbols=0;
if (sl_res_pool->sl_PSFCH_Config_r16 && sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16 && *sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16>0) { if (sl_res_pool->sl_PSFCH_Config_r16 && sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16 && *sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16>0) {
num_psfch_symbols = *sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16; // As per 38214 8.1.3.2, num_psfch_symbols can be 3 if psfch_overhead_indication.nbits is 1; FYI psfch_overhead_indication.nbits is set to 1 in case of PSFCH period 2 or 4 in sl_determine_sci_1a_len()
if (num_psfch_symbols == 3) num_psfch_symbols++; num_psfch_symbols = 3;
} }
int pssch_numsym=7+*sl_bwp->sl_BWP_Generic_r16->sl_LengthSymbols_r16-num_psfch_symbols-2; int pssch_numsym=7+*sl_bwp->sl_BWP_Generic_r16->sl_LengthSymbols_r16-num_psfch_symbols-2;
uint16_t l_subch; uint16_t l_subch;
...@@ -765,11 +744,11 @@ int config_pssch_sci_pdu_rx(sl_nr_rx_config_pssch_sci_pdu_t *nr_sl_pssch_sci_pdu ...@@ -765,11 +744,11 @@ int config_pssch_sci_pdu_rx(sl_nr_rx_config_pssch_sci_pdu_t *nr_sl_pssch_sci_pdu
//Indicates the number of symbols for PSCCH+PSSCH txn //Indicates the number of symbols for PSCCH+PSSCH txn
int num_psfch_symbols=0; int num_psfch_symbols=0;
if (sl_res_pool->sl_PSFCH_Config_r16 && sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16 && *sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16>0) { if (sl_res_pool->sl_PSFCH_Config_r16 && sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16 && *sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16>0) {
num_psfch_symbols = *sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16; // As per 38214 8.1.3.2, num_psfch_symbols can be 3 if psfch_overhead_indication.nbits is 1; FYI psfch_overhead_indication.nbits is set to 1 in case of PSFCH period 2 or 4 in sl_determine_sci_1a_len()
if (num_psfch_symbols == 3) num_psfch_symbols++; num_psfch_symbols = 3;
} }
nr_sl_pssch_sci_pdu->pssch_numsym = 7+*sl_bwp->sl_BWP_Generic_r16->sl_LengthSymbols_r16-num_psfch_symbols-2; nr_sl_pssch_sci_pdu->pssch_numsym = 7+*sl_bwp->sl_BWP_Generic_r16->sl_LengthSymbols_r16-num_psfch_symbols-2;
//DMRS SYMBOL MASK. If bit set to 1 indicates it is a DMRS symbol. LSB is symbol 0 //DMRS SYMBOL MASK. If bit set to 1 indicates it is a DMRS symbol. LSB is symbol 0
// Table from SPEC 38.211, Table 8.4.1.1.2-1 // Table from SPEC 38.211, Table 8.4.1.1.2-1
int num_dmrs_symbols; int num_dmrs_symbols;
......
...@@ -143,13 +143,8 @@ static void prepare_NR_SL_ResourcePool(NR_SL_ResourcePool_r16_t *sl_res_pool, ...@@ -143,13 +143,8 @@ static void prepare_NR_SL_ResourcePool(NR_SL_ResourcePool_r16_t *sl_res_pool,
sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16 = calloc(1, sizeof(long)); sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_Period_r16 = calloc(1, sizeof(long));
// Set of PRBs that are actually used for PSFCH transmission and reception (bitmap) // Set of PRBs that are actually used for PSFCH transmission and reception (bitmap)
// 0xAAAAAAAAAAAA8 (PRBs bitmap) // 0xFFFFFFFFFFFF (PRBs bitmap) Multiple of sl_NumSubchannel * sl_PSFCH_Period
sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_RB_Set_r16 = calloc(1, sizeof(*sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_RB_Set_r16)); sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_RB_Set_r16 = calloc(1, sizeof(*sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_RB_Set_r16));
sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_RB_Set_r16->size = 7;
sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_RB_Set_r16->bits_unused = 6;
sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_RB_Set_r16->buf = calloc(sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_RB_Set_r16->size, sizeof(uint8_t));
memset(sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_RB_Set_r16->buf, 0xAA, 6); // 48 bits
sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_RB_Set_r16->buf[6] = (0b01 << 6); // 2 bits
// Number of cyclic shift pairs used for a PSFCH transmission that can be multiplexed in a PRB // Number of cyclic shift pairs used for a PSFCH transmission that can be multiplexed in a PRB
sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_NumMuxCS_Pair_r16 = calloc(1, sizeof(long)); sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_NumMuxCS_Pair_r16 = calloc(1, sizeof(long));
...@@ -245,6 +240,25 @@ static void prepare_NR_SL_ResourcePool(NR_SL_ResourcePool_r16_t *sl_res_pool, ...@@ -245,6 +240,25 @@ static void prepare_NR_SL_ResourcePool(NR_SL_ResourcePool_r16_t *sl_res_pool,
sprintf(aprefix, "%s.[%i].%s.[%i]", SL_CONFIG_STRING_SL_PRECONFIGURATION, 0,SL_CONFIG_STRING_SL_RX_RPOOL_LIST, 0); sprintf(aprefix, "%s.[%i].%s.[%i]", SL_CONFIG_STRING_SL_PRECONFIGURATION, 0,SL_CONFIG_STRING_SL_RX_RPOOL_LIST, 0);
config_get(SL_POOLPARAMS,sizeof(SL_POOLPARAMS)/sizeof(paramdef_t),aprefix); config_get(SL_POOLPARAMS,sizeof(SL_POOLPARAMS)/sizeof(paramdef_t),aprefix);
struct NR_SL_PSFCH_Config_r16 *nr_sl_psfch_config = sl_res_pool->sl_PSFCH_Config_r16->choice.setup;
const uint8_t psfch_periods[] = {0,1,2,4};
AssertFatal(*nr_sl_psfch_config->sl_PSFCH_Period_r16 < 4, "sl_PSFCH_Period_r16 index must be less than 4\n");
uint8_t psfch_period = psfch_periods[*nr_sl_psfch_config->sl_PSFCH_Period_r16];
uint16_t prod_numCh_period = *sl_res_pool->sl_NumSubchannel_r16*psfch_period;
uint16_t num_prbs = (*sl_res_pool->sl_RB_Number_r16 / prod_numCh_period) * prod_numCh_period;
uint16_t num_bytes = (num_prbs % 8) ? (num_prbs / 8) + 1 : (num_prbs / 8);
sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_RB_Set_r16->size = num_bytes;
sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_RB_Set_r16->bits_unused = (num_prbs % 8) ? 8 - (num_prbs % 8) : 0;
sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_RB_Set_r16->buf = calloc(sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_RB_Set_r16->size, sizeof(uint8_t));
memset(sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_RB_Set_r16->buf, 0xFF, num_prbs / 8);
uint8_t remaining_prbs = 0;
for (int i = 8 - (num_prbs % 8); i < 8; i++)
remaining_prbs |= 1 << i;
if ( num_prbs % 8 != 0 )
sl_res_pool->sl_PSFCH_Config_r16->choice.setup->sl_PSFCH_RB_Set_r16->buf[num_prbs/8] = remaining_prbs;
LOG_D(RRC, "M: %d, PRBs %d, size in bytes %d, unused bits %d, full size bytes %d, remaining prbs %d\n", prod_numCh_period, num_prbs, num_bytes, (num_prbs % 8) ? 8 - (num_prbs % 8) : 0, num_prbs / 8, remaining_prbs);
} }
static void prepare_NR_SL_BWPConfigCommon(NR_SL_BWP_ConfigCommon_r16_t *sl_bwp, static void prepare_NR_SL_BWPConfigCommon(NR_SL_BWP_ConfigCommon_r16_t *sl_bwp,
......
...@@ -237,3 +237,20 @@ where: ...@@ -237,3 +237,20 @@ where:
# Caveats # Caveats
Still issues in power control: txgain, rxgain are not used. Still issues in power control: txgain, rxgain are not used.
# Running 5G Sidelink mode 2 on rfsimulator
```bash
cd openairinterface5g/cmake_targets/ran_build/build
```
### Launch SyncRef UE in one window
```bash
sudo -E ./nr-uesoftmodem -O ../../../targets/PROJECTS/NR-SIDELINK/CONF/sl_preconfiguration.conf --sa --sl-mode 2 --sync-ref --rfsim --thread-pool -1,-1,-1,-1 --rfsimulator.serveraddr server --rfsimulator.serverport 4048 --node-number 2
```
### Launch NearBy UE in another window
```bash
sudo -E ./nr-uesoftmodem -O ../../../targets/PROJECTS/NR-SIDELINK/CONF/sl_preconfiguration.conf --rfsim --sa --sl-mode 2 --thread-pool -1,-1,-1,-1 --rfsimulator.serveraddr 127.0.0.1 --rfsimulator.serverport 4048 --node-number 3
```
SIDELINK_PRECONFIGURATION = (
{
# TDD ULDL CONFIG used for sidelink
sl_dl_UL_TransmissionPeriodicity = 6;
sl_nrofDownlinkSlots = 1;
sl_nrofDownlinkSymbols = 10;
sl_nrofUplinkSlots = 8;
sl_nrofUplinkSymbols = 4;
sl_FrequencyCommonConfig = (
{
sl_offstToCarrier = 0;
sl_subcarrierSpacing = 1;//0-15Khz, 1-30Khz
sl_carrierBandwidth = 106;//numPRBs
#NR bands for Sidelink n47, n38. N47 - 5855Mhz - 5925Mhz
#SL SSB chosen to be located from RB10 to RB21. points to the middle of the SSB block.
#SSB location should be within Sidelink BWP
# this is 2584.95 MHz => 301 REs from PointA 25 PRBs + 1 RE
sl_absoluteFrequencySSB = 516990;
# this is 2575.92 MHz (center frequency is 2585.1 MHz
sl_absoluteFrequencyPointA = 515184;
}
);
sl_BWP = (
{
#RB start 0, RB size = 106. occupies complete Bw.
sl_locationAndBandwidth = 28875;
#Num Symbols used for Sidelink in an uplink slot
#Value can be between symbols 7 to 14
sl_LengthSymbols = 5;
#Sidelink Starting symbol in a slot
#Value can be between symbols 0 to 7
sl_StartSymbol = 0;
}
);
sl_syncCfg = (
{
#NUM SL-SSB within 16 frames
sl_NumSSB_WithinPeriod_0 = 4;
#Slot Offset for the first txn in the 16 frame period
sl_TimeOffsetSSB_0 = 8;
#interval in slots for repetition of SL-SSB
sl_TimeInterval_0 = 120;
}
);
sl_RxResPools = (
{
#Number of symbols which carry PSCCH.
#Possible values 0 means 2 symbols, 1 - means 3 symbols.
sl_TimeResourcePSCCH = 0;
#Number of RBS which carry PSCCH
#Possible values {n10,n12,n15,n20,n25}
sl_FreqResourcePSCCH = 1; //12RBs
#Size of subchannel in RBs
#Possible values - {n10,n12,n15,n20,n25,n50,n75,n100}
sl_SubchannelSize = 5;//10RBs
#start in RB of the lowest subchannel in a rpool
sl_StartRB_Subchannel = 0;
#number of PRBs in a rpool
sl_RB_Number = 50;
sl_NumSubchannel = 1;
# period of PSFCH resource in units of slots within this resource pool
# Possible values sl0 means no PSFCH resource, {sl0, sl1, sl2, sl4}
sl_PSFCH_Period = 3; //sl4
# set of PRBs used for PSFCH transmission and reception
# leftmost bit of the bitmap is lowest RB index in the resource pool
# value 0 in the bitmap means PRB is not used for PSFCH operations
#sl_PSFCH_RB_Set = 0xAAAAAAAAAAAA8;
# Number of cyclic shift pairs used for a PSFCH transmission that can be multiplexed in a PRB
# Possible values {n1, n2, n3, n4}
sl_NumMuxCS_Pair = 1;
# Minimum time gap between PSFCH and the associated PSSCH in the unit of slots {sl2, sl3}
sl_MinTimeGapPSFCH = 1; //sl3
# Scrambling ID {0..1023} for sequence hopping of the PSFCH used in the resource pool
sl_PSFCH_HopID = 1;
# Number of PSFCH resources available {startSubCH, allocSubCH} for multiplexing HARQ-ACK information in a PSFCH transmission
sl_PSFCH_CandidateResourceType = 0; // startSubCH
}
);
sl_TxResPools = (
{
#Number of symbols which carry PSCCH.
#Possible values 0 means 2 symbols, 1 - means 3 symbols.
sl_TimeResourcePSCCH = 0;
#Number of RBS which carry PSCCH
#Possible values {n10,n12,n15,n20,n25}
sl_FreqResourcePSCCH = 1; //12RBs
#Size of subchannel in RBs
#Possible values - {n10,n12,n15,n20,n25,n50,n75,n100}
sl_SubchannelSize = 5;//50RBs
#start in RB of the lowest subchannel in a rpool
sl_StartRB_Subchannel = 0;
#number of PRBs in a rpool
sl_RB_Number = 50;
sl_NumSubchannel = 1;
}
);
sl_UEINFO = (
{
srcid = 0;
thirdOctet = 0;
fourthOctet = 1;
}
);
}
);
\ No newline at end of file
...@@ -28,7 +28,7 @@ SIDELINK_PRECONFIGURATION = ( ...@@ -28,7 +28,7 @@ SIDELINK_PRECONFIGURATION = (
sl_locationAndBandwidth = 28875; sl_locationAndBandwidth = 28875;
#Num Symbols used for Sidelink in an uplink slot #Num Symbols used for Sidelink in an uplink slot
#Value can be between symbols 7 to 14 #Value can be between symbols 7 to 14
sl_LengthSymbols = 5; sl_LengthSymbols = 7;
#Sidelink Starting symbol in a slot #Sidelink Starting symbol in a slot
#Value can be between symbols 0 to 7 #Value can be between symbols 0 to 7
sl_StartSymbol = 0; sl_StartSymbol = 0;
......
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