* [NEON] Add -ffloat-store to test/arm/neon/meson.build

* [NEON] Add 5 intrinsics (vdiv{h/q}_f{16/64}).
* [NEON] Add 11 dup_lane series intrinsics.
- 2 dup{q}_laneq_f16
- 9 dup{b,h}_lane{q}_{s/u}{8,16}, duph_laneq_f16
* [NEON] Add 8 intrinsics (veor3q{s/u}{8/16/32/64}).
* [NEON] Add fmlal, fmlsl, maxnmv, minnmv, pmaxnm, pminnm.
* [NEON] Add 12 fmlal series intrinsics.
* [NEON] Add 12 fmlsl series intrinsics.
* [NEON] Add 11 vmax series intrinsics.
- 1 vmaxh_f16
- 3 vmaxnm{/h/q}_f16
- 5 vmaxnmv{q}_f{16/32/64}
- 2 vmaxv{q}_f16
* [NEON] Add 11 vmin series intrinsics.
- 1 vminh_f16
- 3 vminnm{/h/q}_f16
- 5 vminnmv{q}_f{16/32/64}
- 2 vminv{q}_f16
* [NEON] Add 8 vpmax series intrinsics.
- 1 vpmaxq_f16
- 7 vpmaxnm{/s/q/qd}_f{16/32/64}
* [NEON] Add 9 vpmin series intrinsics.
- 2 vpmin{q}_f16
- 7 vpminnm{/s/q/qd}_f{16/32/64}
* [NEON] Add 8 intrinsic function families.
mmlaq, mull_high_lane, mull_high_n, mulx,
mulx_lane, mulx_n, qrdmlah, qmovun_high.
* [NEON] Add 3 vmmlaq series intrinsics.
* [NEON] Add 41 vmul-related intrinsics.
- 8 mull_high_lane series intrinsics
- 4 mull_high_n series intrinsics
- 9 vmulx series intrinsics
- 2 vmulx{q}_n_f16 series intrinsics
- 18 vmulx_lane series intrinsics
* [NEON] Add 1 vpaddq_f16 intrinsic.
* [NEON] Add 3 vqmovun_high_s{16/32/64} intrinsic.
* [NEON] Add 6 vqrdmlah series intrinsics.
* [NEON] Add 11 series intrinsics.
qrdmlah_lane, qrdmlsh, qrdmlsh_lane, qshrun_high_n,
rnd32x, rnd32z, rnd64x, rnd64z, rnda, rndx, shll_high_n.
* [NEON] Add 30 vqrdmlah, vqrdmlsh related intrinsics.
- 12 vqrdmlah{h/s/q}_lane{q}_s{16/32}
- 6 vqrdmlsh{h/s/q}_s{16/32}
- 12 vqrdmlsh{h/s/q}_lane{q}_s{16/32}
* [NEON] Add 2 vqrdmulhh_lane{q}_s16 intrinsics.
* [NEON] Add 5 vqsh related intrinsics.
- 1 vqshluh_n_s16
- 3 vqshrun_high_n_s{16/32/64}
- 1 vqshrun_n_s16
* [NEON] Add 16 vrnd32x, vrnd32z, vrnd64x, vrnd64z related intrinsics.
- 4 vrnd32x{q}_f{32/64}
- 4 vrnd32z{q}_f{32/64}
- 4 vrnd64x{q}_f{32/64}
- 4 vrnd64x{q}_f{32/64}
* [NEON] Add vrnd{/a/i/m/p/x} related intrinsics.
- 3 vrnd{/h/q}_f16
- 3 vrndi{/h/q}_f16
- 3 vrndm{/h/q}_f16
- 3 vrndp{/h/q}_f16
- 7 vrnda{q}_f{16/32/64}, vrndah_f16
- 7 vrndx{q}_f{16/32/64}, vrndxh_f16
* [NEON] Add 6 vshll_high_n series intrinsics.
* [NEON] Add 7 intrinsic series.
cadd_rot270, cadd_rot90, shrn_high_n, subhn_high,
sudot_lane, usdot, usdot_lane
* [NEON] Add 2 vcmla{q}_f16 intrinsics
* [NEON] Add 6 vshrn_high_n series intrinsics
* [NEON] Add 6 vsubhn_high series intrinsics
* [NEON] Add 10 vsudot_lane, vusdot, and vusdot_lane series intrinsics.
- 4 sudot{q}_lane{q}_s32
- 2 vusdot{q}_s32
- 4 vusdot{q}_lane{q}_s32
* [NEON] Add 10 vadd{q}_rot{90/270}_f{16/32/64} intrinsics.
* [NEON] Add 5 series intrinsics.
cmla_lane, cmla_rot180_lane, cmla_rot270_lane, cmla_rot90_lane, recpx.
* [NEON] Add 38 vcmla related intrinsics.
- 8 cvmla{q}_lane{q}_f{16/32}
- 2 cvmla{q}_rot90_f16
- 8 cvmla{q}_rot90_lane{q}_f{16/32}
- 2 cvmla{q}_rot180_f16
- 8 cvmla{q}_rot180_lane{q}_f{16/32}
- 2 cvmla{q}_rot270_f16
- 8 cvmla{q}_rot270_lane{q}_f{16/32}
* [NEON] Add vrecpeh_f16 and vrecpsh_f16 intrinsics.
* [NEON] Add 3 vrecpx{h,s,d}_f{16,32,64} intrinsics.
* [NEON] Add 8 series intrinsics.
__crc32, ras, sha1, sha256, sha512, sm3, sm4
* [NEON] Add 8 __crc series intrinsics.
* [NEON] Add vrax1q_u64 intrinsic
* [NEON] Add sha1, sha256, and sha512 series intrinsics
* [NEON] Add sm3 and sm4 series intrinsics
* [NEON] Include <arm_acle.h> for __crc32 intrinsics
* [NEON] Use uint to simulate the poly type and implement it
* [NEON] Add poly type related intrinsics
* [NEON] Add ldr and str related intrinsics.
Co-authored-by: Eric Yi-Yen Chung <eric681@andestech.com>
Co-authored-by: Michael R. Crusoe <michael.crusoe@gmail.com>

Fixes: https://github.com/simd-everywhere/simde/issues/1104

Closes: https://github.com/simd-everywhere/simde/issues/1069

Co-authored-by: Florent Hivert <Florent.Hivert@lri.fr>

Fixes: https://github.com/simd-everywhere/simde/issues/1094

fix casts for GCC<9

add tests for all `simde_mm512_set_*` functions

Add 368 initial implementations and corresponding test cases in 88 families which are listed below:
- `abd`, `abdl_high`, `add`, `addhn_high`, `bsl`, `ceq`, `ceqz`, `cgez`, `cgtz`, `cle`,
- `cltz`, `cmla`, `cmla_rot180`, `cmla_rot270`, `cmla_rot90`, `cnt`, `copy_lane`, `cvt`, `cvt_n`, `cvtm`,
-  `cvtp`, `dot`, `dot_lane`, `dup_n`, `eor`, `fms_n`, `ld1`, `ld3`, `ld4`, `maxnm`,
-  `maxv`, `minnm`, `minv`, `mull`, `mull_high`, `mvn`, `pmin`, `qrdmulh_lane`, `qrshl`, `qrshrn_high_n`,
-  `qrshrun_high_n`, `qshl_n`, `qshlu_n`, `qshrn_high_n`, `qshrn_n`, `qshrun_n`, `qtbl`, `qtbx`, `raddhn`, `raddhn_high`,
-  `rbit`, `reinterpret`, `rev16`, `rev32`, `rev64`, `rnd`, `rndi`, `rndm`, `rndp`, `rshrn_high_n`,
-  `rsubhn`, `rsubhn_high`, `shr_n`, `shrn_n`, `sli_n`, `sri_n`, `st1`, `st1_lane`, `st1_x2`, `st1_x3`,
-  `st1_x4`, `st1q_x2`, `st1q_x3`, `st1q_x4`, `st2_lane`, `st3`, `st3_lane`, `st4`, `st4_lane`, `tbl`,
-  `tbx`, `trn`, `trn1`, `trn2`, `tst`, `uzp`, `uzp1`, `uzp2`

Like the Intel compiler, it can lead to emiting AVX512 ops even when
/arch:AVX512 is not set.

However, the ClangCL compiler, which pretends to be MSVC, does not have
this issue.
Co-authored-by: Steven Noonan <steven@uplinklabs.net>

and don't always enable AVX512F_NATIVE

Fixes: #906

ci clang-16: silence "unsafe-buffer-usage" warning

Seems to be a false positive

Fixes: https://github.com/simd-everywhere/simde/issues/1084

Co-authored-by: Décio Luiz Gazzoni Filho <decio@decpp.net>
Co-authored-by: Michael R. Crusoe <michael.crusoe@gmail.com>

* [NEON] Add vabal_{s/u}{8/16/32}

* [NEON] Add vabal_high_{s/u}{8/16/32}

* [NEON] Add all vcale* intrinsics (9)

* [NEON] Add all vcalt intrinsics (9)

* [NEON] Add vcreate_f16

* [NEON] Add vreinterpret_u64_f16

* [NEON] Add vcvth_f16_s16 and vcvth_f16_u16

* [NEON] Add vduph_lane_f16, vdup_lane_f16, and vdupq_lane_f16

* [NEON] Add vext_f16

* [NEON] Add 16 vcvt{q}_n_* intrinsics

* [Fix] Correct function input parameters

* [NEON] Add 6 vcvtn_{s/u}{16/32/64}_f{*} intrinsics

* [Fix] Correct vdup_lane_f16 and vdupq_lane_f16.

* [Fix] Correct function input parameters.

* [NEON] Add 24 vcvt{q}_n_* intrinsics

* [NEON] Add all vcvtn* intrinsics

* [NEON] Add vfmah_f16 and vfma_f16

* [NEON] Add vfma_n_f16 and vfmaq_n_f16

* [NEON] Add vmulh_f16

* [NEON] Add fma_lane related intrinsics.

* [NEON] Add 5 vmul* related intrinsics
vmulh_lane_f16, vmulh_laneq_f16, vmul_lane_f16,
vmul_laneq_f16, vmulq_laneq_f16.

* [NEON] Add neg related intrinsics.

* [NEON] Add all fms, fms_n, and fms_lane intrinsics

* [NEON] Add types float16x{4/8}x{2/3/4}

* [NEON] Add 9 vld1 related intrinsics

* [Fix] Modified wrong rounding implementation.
Modified wrong implementation "Ties to Away" to "rounding to nearest
with ties to Away"
add.h: Remove redundant code.

* [Fix] Fix wrong intrinsic alias names.

* [Refactor] Remove redundant functions.

* [NEON] Add 45 ld2 related intrinsics
one ld2_f16, twenty-two ld2_lane series, and twenty-two ld2_dup series.

* [NEON] Add ld3_dup, ld3_lane, and ld4_dup

* [NEON] Add vld3_f16 and vld4_f16.

* [NEON] Add vld{3/4}_{dup/lane} series intrinsics

* [NEON] Add mla_{high}_lane series intrinsics

* [NEON] Add qdmlal_{high}_{lane} series intrinsics.

* [NEON] Add qdmlal_lane and qdmlal_n series intrinsics

* [NEON] Add mls_lane and mlsl_high_lane series intrinsics

* [NEON] Add 22 qdmlsl series intrinsics

* [NEON] Add 10 qdmull_* series intrinsics

* [NEON] Add 3 qdmulh series intrinsics

* [Fix] Fix wrong function name.

* [Fix] Correct the wrong alias function name.

* [NEON] Add qdmullh_lane{q}_s{16/32} related intrinsics

* [NEON] Add qdmull_n and qdmull_high_lane series intrinsics

* [Fix] Add conditions for fp16 intrinsics

* [Hack] Skip functions that trigger compiler bugs.

* [Neon] Add vcadd_rot270_f{16/32} and vcaddq_rot270_f{16/32/64}
* [Neon] Add vcadd_rot90_f{16/32} and vcaddq_rot90_f{16/32/64}
* [Neon] Add vcmla_lane_f{16/32} and vcmla_laneq_f{16/32} and vcmlaq_lane_f{16/32} and vcmlaq_laneq_f{16/32}
* [Neon] Add vcmla_rot90_lane_f{16/32} and vcmla_rot90_laneq_f{16/32} and vcmlaq_rot90_lane_f{16/32} and vcmlaq_rot90_laneq_f{16/32}
* [Neon] Add vcmla_rot180_lane_f{16/32} and vcmla_rot180_laneq_f{16/32} and vcmlaq_rot180_lane_f{16/32} and vcmlaq_rot180_laneq_f{16/32}
* [Neon] Add vcadd_rot270_f{16/32} and vcaddq_rot270_f{16/32/64}

Adapted from https://github.com/DLTcollab/sse2neon/pull/6
and https://github.com/DLTcollab/sse2neon/pull/559

Inspired by https://github.com/DLTcollab/sse2neon/pull/579

* [NEON] Add vmulq_f16 and vmul_f16.

* [NEON] Add vmulq_f16 and vmul_f16 test.

* [NEON] Add vget_lane_f16 and vgetq_lane_f16.

* [NEON] Add vsubh_f16 and vsub_f16.

* [NEON] Add vextq_f16.

* [NEON] Add vget_low_f16.

* [NEON] Add vmulq_lane_f16.

* [NEON] Add vmul_n_f16.

* [NEON] Add vget_high_f16.

* [NEON] Add vsetq_lane_f16.

* [NEON] Add vcombine_f16.

* [NEON] Add vcvtaq_s32_f32, vcvtas_s32_f32, and vcvta_s32_f32.

* [NEON] Add vpadd_f16.

* [NEON] Add vuzp1_f16.

* [NEON] Add vuzp2_f16.

* [NEON] Add vmaxq_f16 and vmax_f16.

* [NEON] Add vcvtas_u32_f32, vcvta_u32_f32, vcvtaq_u32_f32.

* [NEON] Add type simde_float16x8x2_t.

* [NEON] Add vld2q_f16.

* [NEON] Add vld1q_dup_f16.

* [NEON] Add vpmax_f16.

* [NEON] Add vrsqrtsq_f16, vrsqrtsh_f16, vrsqrts_f16.

* [NEON] Add vcgtq_f16, vcgt_f16, vcgth_f16.

* [NEON] Add vdiv_f32 and vdivq_f32.

* [NEON] Add vrecps_f16 and vrecpsq_f16.

* [NEON] Add vset_lane_f16.

* [NEON] Add vrecpe_f16, vrecpeq_f16.

* [NEON] Add vfmaq_f16.

* [NEON] Add vabsq_f16 and vabs_f16.

* [NEON] Add vcltq_f16 and vclth_f16.

* [NEON] Add vmin_f16 and vminq_f16.

* [NEON] Add vclt_f16.

* [NEON] Add vclezq_f16, vclez_f16, and vclezh_f16.

* [NEON] Add vzip_f16 and vzipq_f16.

* [NEON] Add vzip1_f16 and vzip1q_f16.

* [NEON] Add vzip2_f16 and vzip2q_f16.

* [NEON] Add vst2_f16 and vst2q_f16.

* [NEON] Add type simde_float16x4x2.

* [NEON] Add 16 intrinsics of vreinterpret series.

* [SIMDE] Add sqrtl() in simde_math_sqrtl.

* [NEON] Add vrndnq_f16, vrndns_f16, and vrndn_f16.

* [NEON] Add sqrt in meson.build.

* [NEON] Add 7 sqrt related intrinsics.

* [Fix] Add the judge whether define sqrt() or not.

* [NEON] Add vrsqrteq_f16, vrsqrte_f16, and vrsqrteh_f16.

* [NEON] Add vqrshrnh_n_s16 and vqrshrnh_n_u16.

* [NEON] Add vqrshrunh_n_s16.

* [Fix] Add new conditions for fp16 intrinsics.

* [License] Add Copyright.

Closes: #926
Co-authored-by: clin99 <34017491+clin99@users.noreply.github.com>

when using `/arch=AVX` or similar then SSE4.2 does not get activated (on MSVC at least, but should be similar on g++/clang)

This PR fixes this.

Fixes errors like

FAILED: test/x86/avx512/cast-emul-c (also load, loadu, max, min, permutexvar, reduce, set, setzero, set1, storeu, f16c)
clang-17  -o test/x86/avx512/cast-emul-c test/x86/avx512/cast-emul-c.p/cast.c.o -Wl,--as-needed -Wl,--no-undefined --target=riscv64-linux-gnu -Wl,--start-group -lm -Wl,--end-group
/usr/bin/riscv64-linux-gnu-ld: test/x86/avx512/cast-emul-c.p/cast.c.o: in function `simde_test_x86_assert_equal_f16x32_':
/opt/simde/riscv64-clang-17/../../../usr/local/src/simde/test/x86/avx512/test-avx512.h:14: undefined reference to `__truncsfhf2'

FAILED: test/x86/avx512/cmp-emul-c (also reduce)
clang-17  -o test/x86/avx512/cmp-emul-c test/x86/avx512/cmp-emul-c.p/cmp.c.o -Wl,--as-needed -Wl,--no-undefined --target=riscv64-linux-gnu -Wl,--start-group -lm -Wl,--end-group
/usr/bin/riscv64-linux-gnu-ld: test/x86/avx512/cmp-emul-c.p/cmp.c.o: in function `simde_mm512_cmp_ph_mask':
/opt/simde/riscv64-clang-17/../../../usr/local/src/simde/simde/x86/avx512/cmp.h:741: undefined reference to `__extendhfsf2'
/usr/bin/riscv64-linux-gnu-ld: /opt/simde/riscv64-clang-17/../../../usr/local/src/simde/simde/x86/avx512/cmp.h:741: undefined reference to `__extendhfsf2'
/usr/bin/riscv64-linux-gnu-ld: /opt/simde/riscv64-clang-17/../../../usr/local/src/simde/simde/x86/avx512/cmp.h:741: undefined reference to `__extendhfsf2'
/usr/bin/riscv64-linux-gnu-ld: /opt/simde/riscv64-clang-17/../../../usr/local/src/simde/simde/x86/avx512/cmp.h:741: undefined reference to `__extendhfsf2'
/usr/bin/riscv64-linux-gnu-ld: /opt/simde/riscv64-clang-17/../../../usr/local/src/simde/simde/x86/avx512/cmp.h:741: undefined reference to `__extendhfsf2'
/usr/bin/riscv64-linux-gnu-ld: test/x86/avx512/cmp-emul-c.p/cmp.c.o:/opt/simde/riscv64-clang-17/../../../usr/local/src/simde/simde/x86/avx512/cmp.h:741: more undefined references to `__extendhfsf2' follow
clang: error: linker command failed with exit code 1 (use -v to see invocation)