Inspired by https://github.com/DLTcollab/sse2neon/pull/579

* [NEON] Add vmulq_f16 and vmul_f16.

* [NEON] Add vmulq_f16 and vmul_f16 test.

* [NEON] Add vget_lane_f16 and vgetq_lane_f16.

* [NEON] Add vsubh_f16 and vsub_f16.

* [NEON] Add vextq_f16.

* [NEON] Add vget_low_f16.

* [NEON] Add vmulq_lane_f16.

* [NEON] Add vmul_n_f16.

* [NEON] Add vget_high_f16.

* [NEON] Add vsetq_lane_f16.

* [NEON] Add vcombine_f16.

* [NEON] Add vcvtaq_s32_f32, vcvtas_s32_f32, and vcvta_s32_f32.

* [NEON] Add vpadd_f16.

* [NEON] Add vuzp1_f16.

* [NEON] Add vuzp2_f16.

* [NEON] Add vmaxq_f16 and vmax_f16.

* [NEON] Add vcvtas_u32_f32, vcvta_u32_f32, vcvtaq_u32_f32.

* [NEON] Add type simde_float16x8x2_t.

* [NEON] Add vld2q_f16.

* [NEON] Add vld1q_dup_f16.

* [NEON] Add vpmax_f16.

* [NEON] Add vrsqrtsq_f16, vrsqrtsh_f16, vrsqrts_f16.

* [NEON] Add vcgtq_f16, vcgt_f16, vcgth_f16.

* [NEON] Add vdiv_f32 and vdivq_f32.

* [NEON] Add vrecps_f16 and vrecpsq_f16.

* [NEON] Add vset_lane_f16.

* [NEON] Add vrecpe_f16, vrecpeq_f16.

* [NEON] Add vfmaq_f16.

* [NEON] Add vabsq_f16 and vabs_f16.

* [NEON] Add vcltq_f16 and vclth_f16.

* [NEON] Add vmin_f16 and vminq_f16.

* [NEON] Add vclt_f16.

* [NEON] Add vclezq_f16, vclez_f16, and vclezh_f16.

* [NEON] Add vzip_f16 and vzipq_f16.

* [NEON] Add vzip1_f16 and vzip1q_f16.

* [NEON] Add vzip2_f16 and vzip2q_f16.

* [NEON] Add vst2_f16 and vst2q_f16.

* [NEON] Add type simde_float16x4x2.

* [NEON] Add 16 intrinsics of vreinterpret series.

* [SIMDE] Add sqrtl() in simde_math_sqrtl.

* [NEON] Add vrndnq_f16, vrndns_f16, and vrndn_f16.

* [NEON] Add sqrt in meson.build.

* [NEON] Add 7 sqrt related intrinsics.

* [Fix] Add the judge whether define sqrt() or not.

* [NEON] Add vrsqrteq_f16, vrsqrte_f16, and vrsqrteh_f16.

* [NEON] Add vqrshrnh_n_s16 and vqrshrnh_n_u16.

* [NEON] Add vqrshrunh_n_s16.

* [Fix] Add new conditions for fp16 intrinsics.

* [License] Add Copyright.

Closes: #926
Co-authored-by: clin99 <34017491+clin99@users.noreply.github.com>

when using `/arch=AVX` or similar then SSE4.2 does not get activated (on MSVC at least, but should be similar on g++/clang)

This PR fixes this.

Fixes errors like

FAILED: test/x86/avx512/cast-emul-c (also load, loadu, max, min, permutexvar, reduce, set, setzero, set1, storeu, f16c)
clang-17  -o test/x86/avx512/cast-emul-c test/x86/avx512/cast-emul-c.p/cast.c.o -Wl,--as-needed -Wl,--no-undefined --target=riscv64-linux-gnu -Wl,--start-group -lm -Wl,--end-group
/usr/bin/riscv64-linux-gnu-ld: test/x86/avx512/cast-emul-c.p/cast.c.o: in function `simde_test_x86_assert_equal_f16x32_':
/opt/simde/riscv64-clang-17/../../../usr/local/src/simde/test/x86/avx512/test-avx512.h:14: undefined reference to `__truncsfhf2'

FAILED: test/x86/avx512/cmp-emul-c (also reduce)
clang-17  -o test/x86/avx512/cmp-emul-c test/x86/avx512/cmp-emul-c.p/cmp.c.o -Wl,--as-needed -Wl,--no-undefined --target=riscv64-linux-gnu -Wl,--start-group -lm -Wl,--end-group
/usr/bin/riscv64-linux-gnu-ld: test/x86/avx512/cmp-emul-c.p/cmp.c.o: in function `simde_mm512_cmp_ph_mask':
/opt/simde/riscv64-clang-17/../../../usr/local/src/simde/simde/x86/avx512/cmp.h:741: undefined reference to `__extendhfsf2'
/usr/bin/riscv64-linux-gnu-ld: /opt/simde/riscv64-clang-17/../../../usr/local/src/simde/simde/x86/avx512/cmp.h:741: undefined reference to `__extendhfsf2'
/usr/bin/riscv64-linux-gnu-ld: /opt/simde/riscv64-clang-17/../../../usr/local/src/simde/simde/x86/avx512/cmp.h:741: undefined reference to `__extendhfsf2'
/usr/bin/riscv64-linux-gnu-ld: /opt/simde/riscv64-clang-17/../../../usr/local/src/simde/simde/x86/avx512/cmp.h:741: undefined reference to `__extendhfsf2'
/usr/bin/riscv64-linux-gnu-ld: /opt/simde/riscv64-clang-17/../../../usr/local/src/simde/simde/x86/avx512/cmp.h:741: undefined reference to `__extendhfsf2'
/usr/bin/riscv64-linux-gnu-ld: test/x86/avx512/cmp-emul-c.p/cmp.c.o:/opt/simde/riscv64-clang-17/../../../usr/local/src/simde/simde/x86/avx512/cmp.h:741: more undefined references to `__extendhfsf2' follow
clang: error: linker command failed with exit code 1 (use -v to see invocation)

sse/sse2: added ".f16" float16 accessor for m128 & m128i

mm{256,512}_cvt{ph_ps,ps_ph}: use .f16 instead of converting from u16

mm512_cvt{epi8_epi16,epi32_ps,cvtph_ps}: added _mm256_cvt* native fallbacks

https://github.com/llvm/llvm-project/commit/f253bb640d97756d2808bb7c7b2bb31b1090a654
https://reviews.llvm.org/D144169

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105339

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98521

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94482

Clang incorrectly sets the alignment bit on 32-bit for the multiple load
instructions. This results in a bus error on hardware.

Similar to _mm_shuffle_epi8, qtbl/qtbx now split up to multiple shuffles on
A32V7. With multi-vector shuffles, two tables are created, the indexes
are subtracted, and either TBX'd on the result of the other table or ORR'd
together (TBX is mandatory for qtbx, but ORR is chosen when the lookups would
not be theoretically dual issued).

Caught by clang-14+

_make
_const
_extract_lane
_splat
_const_splat (also signed variants)

My attempt for the unsigned versions did not work